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[2620:52:3:1:0:246e:9693:128c]) by mx.google.com with ESMTPS id d3-20020a056402078300b0050491fcd851si2224528edy.390.2023.04.20.13.12.46 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 20 Apr 2023 13:12:47 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) client-ip=2620:52:3:1:0:246e:9693:128c; Authentication-Results: mx.google.com; dkim=pass header.i=@gcc.gnu.org header.s=default header.b=kuBP6NX4; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=gnu.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 9987F385840A for ; Thu, 20 Apr 2023 20:12:44 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 9987F385840A DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1682021564; bh=1jEVObKj2Ti2q1Tf0W7fJl56Q5ei9JlJDPNYSB1zMTc=; h=Date:Subject:To:List-Id:List-Unsubscribe:List-Archive:List-Post: List-Help:List-Subscribe:From:Reply-To:From; b=kuBP6NX4A9V4K6RUdXHOVCBJ3kHWCeV6gC8v5xWK12EIXmTTp6vEr7f3/WNtCraUK 2GMIgtLRDbRkVAwqc0R/j5k97OMEjbcsy7mogJ7nB2cnbdApLBituvED3T60+JGVv5 vkfRcDa+1UXPVxFuK7/ogAVCWhL087sZ60s9agaQ= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mail-pf1-x430.google.com (mail-pf1-x430.google.com [IPv6:2607:f8b0:4864:20::430]) by sourceware.org (Postfix) with ESMTPS id 3CDCA3858D37 for ; Thu, 20 Apr 2023 20:12:00 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 3CDCA3858D37 Received: by mail-pf1-x430.google.com with SMTP id d2e1a72fcca58-63b57c49c4cso1336859b3a.3 for ; Thu, 20 Apr 2023 13:12:00 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1682021519; x=1684613519; h=to:subject:message-id:date:from:mime-version:x-gm-message-state :from:to:cc:subject:date:message-id:reply-to; bh=7gwiOUIknzbv8pxRRKGqH8Zrmw5pj++11K4qXaZJpJ4=; b=Ryb7cVi7vcx3P9na/KPg/0QOTByXvB2sb88U98VDdlnce317N50WXpivAhVpNTgGMs Jq1ChVD+3w8Nw3VpI3ctnBWI4PQLLH3WDDNGlXacv9fOibK/K49j85NxWj0j/oe1ZNT4 SDYm4wPYUf6UOiBLrrjDx2nQb5FqGBiwk/cM1Qtq0QMdgMhLdpdCKWbxiA9O6qjI5wXR +/SY5/5p1zmLRChJ7rt1n3t5++83+RpwI0k8q23FJLHa64JGeObLTNKwSSWL7Gj1V2zZ MfNTpjOEmOKjf2VzNaVDL/RABPZCWwdJ7gU1VIantPfEK5F/cJpMEkc25Zghn9VzMXLg ObgQ== X-Gm-Message-State: AAQBX9csm/YWL91NyYreP9DAg9IwkIIDGw3TYBzPgQtZfOJf4L7LjG5C QRjHBWaj8WSUUwamN5oRb48gw70lJlQTqM27WMlwM6xT7H11SQ== X-Received: by 2002:a17:902:e849:b0:1a9:3a8c:d590 with SMTP id t9-20020a170902e84900b001a93a8cd590mr2117178plg.16.1682021518521; Thu, 20 Apr 2023 13:11:58 -0700 (PDT) MIME-Version: 1.0 Date: Fri, 21 Apr 2023 00:11:42 +0400 Message-ID: Subject: RISC-V: avoid splitting small constants in bcrli_nottwobits patterns To: gcc-patches@gcc.gnu.org X-Spam-Status: No, score=-7.2 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, FREEMAIL_ENVFROM_END_DIGIT, FREEMAIL_FROM, GIT_PATCH_0, HTML_MESSAGE, KAM_SHORT, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-Content-Filtered-By: Mailman/MimeDel 2.1.29 X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Jivan Hakobyan via Gcc-patches From: Jivan Hakobyan Reply-To: Jivan Hakobyan Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1763727446624938964?= X-GMAIL-MSGID: =?utf-8?q?1763727446624938964?= Hi all. I have noticed that in the case when we try to clear two bits through a small constant, and ZBS is enabled then GCC split it into two "andi" instructions. For example for the following C code: int foo(int a) { return a & ~ 0x101; } GCC generates the following: foo: andi a0,a0,-2 andi a0,a0,-257 ret but should be this one: foo: andi a0,a0,-258 ret This patch solves the mentioned issue. RISC-V: avoid splitting small constant in *bclri_nottwobits and *bclridisi_nottwobit patterns gcc/ * config/riscv/bitmanip.md Updated predicats of bclri_nottwobits and bclridisi_nottwobits patterns * config/riscv/predicates.md (not_uimm_extra_bit_or_nottwobits): Adjust predicate to avoid splitting arith constants * config/riscv/predicates.md (const_nottwobits_not_arith_operand): New predicate gcc/testsuite * gcc.target/riscv/zbs-bclri-nottwobits.c: New test. diff --git a/gcc/config/riscv/bitmanip.md b/gcc/config/riscv/bitmanip.md index 388ef662820..f3d29a466e7 100644 --- a/gcc/config/riscv/bitmanip.md +++ b/gcc/config/riscv/bitmanip.md @@ -507,7 +507,7 @@ (define_insn_and_split "*bclri_nottwobits" [(set (match_operand:X 0 "register_operand" "=r") (and:X (match_operand:X 1 "register_operand" "r") - (match_operand:X 2 "const_nottwobits_operand" "i")))] + (match_operand:X 2 "const_nottwobits_not_arith_operand" "i")))] "TARGET_ZBS && !paradoxical_subreg_p (operands[1])" "#" "&& reload_completed" @@ -526,7 +526,7 @@ (define_insn_and_split "*bclridisi_nottwobits" [(set (match_operand:DI 0 "register_operand" "=r") (and:DI (match_operand:DI 1 "register_operand" "r") - (match_operand:DI 2 "const_nottwobits_operand" "i")))] + (match_operand:DI 2 "const_nottwobits_not_arith_operand" "i")))] "TARGET_64BIT && TARGET_ZBS && clz_hwi (~UINTVAL (operands[2])) > 33" "#" diff --git a/gcc/config/riscv/predicates.md b/gcc/config/riscv/predicates.md index 8654dbc5943..e5adf06fa25 100644 --- a/gcc/config/riscv/predicates.md +++ b/gcc/config/riscv/predicates.md @@ -366,6 +366,11 @@ (and (match_code "const_int") (match_test "popcount_hwi (~UINTVAL (op)) == 2"))) +(define_predicate "const_nottwobits_not_arith_operand" + (and (match_code "const_int") + (and (not (match_operand 0 "arith_operand")) + (match_operand 0 "const_nottwobits_operand")))) + ;; A CONST_INT operand that consists of a single run of 32 consecutive ;; set bits. (define_predicate "consecutive_bits32_operand" @@ -411,4 +416,4 @@ (define_predicate "not_uimm_extra_bit_or_nottwobits" (and (match_code "const_int") (ior (match_operand 0 "not_uimm_extra_bit_operand") - (match_operand 0 "const_nottwobits_operand")))) + (match_operand 0 "const_nottwobits_not_arith_operand")))) diff --git a/gcc/testsuite/gcc.target/riscv/zbs-bclri-nottwobits.c b/gcc/testsuite/gcc.target/riscv/zbs-bclri-nottwobits.c new file mode 100644 index 00000000000..5a58e0a1185 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/zbs-bclri-nottwobits.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_zbs -mabi=lp64" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" } } */ + +int and_two_bit(int idx) { + return idx & ~3; +} + +int and_bclr_two_bit(int idx) { + return idx & ~(0x4001); +} + +/* { dg-final { scan-assembler-times "\tandi\t" 2 } } */ +/* { dg-final { scan-assembler-times "\tbclri\t" 1 } } */