diff mbox series

[RFC,RFA] i386: Handle multiple address register classes

Message ID CAFULd4bKQg28H+6fx4KtT9OFGMOf9xK1OiV4oPhyt3gJiG4k9g@mail.gmail.com
State Unresolved
Headers
Series [RFC,RFA] i386: Handle multiple address register classes |

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Context Check Description
snail/gcc-patch-check warning Git am fail log

Commit Message

Uros Bizjak Nov. 3, 2023, 10:34 a.m. UTC 
  The patch generalizes address register class handling to allow multiple
address register classes.  For APX EGPR targets, some instructions can't be
encoded with REX2 prefix, so it is necessary to limit address register
class to avoid REX2 registers.  The same situation happens for instructions
with high registers, where the REX register can not be used in the address,
so the existing infrastructure can be adapted to also handle this case.

The patch is mostly a mechanical rename of "gpr32" attribute to "addr" and
introduces no functional changes, although it fixes a couple of inconsistent
attribute values in passing.

A follow-up patch will use the above infrastructure to limit address register
class to legacy registers for instructions with high registers.

gcc/ChangeLog:

    * config/i386/i386.cc (ix86_memory_address_use_extended_reg_class_p):
    Rename to ...
    (ix86_memory_address_reg_class): ... this.  Generalize address
    register class handling to allow multiple address register classes.
    Return maximal class for unrecognized instructions.  Improve comments.
    (ix86_insn_base_reg_class): Rewrite to handle
    multiple address register classes.
    (ix86_regno_ok_for_insn_base_p): Ditto.
    (ix86_insn_index_reg_class): Ditto.
    * config/i386/i386.md: Rename "gpr32" attribute to "addr"
    and substitute its values with "0" -> "rex", "1" -> "*".
    (addr): New attribute to limit allowed address register set.
    (gpr32): Remove.
    * config/i386/mmx.md: Rename "gpr32" attribute to "addr"
    and substitute its values with "0" -> "rex", "1" -> "*".
    * config/i386/sse.md: Ditto.

Bootstrapped and regression tested on x86_64-linux-gnu {,-m32}.

Comments welcome.

Uros.

Comments

Hongtao Liu Nov. 3, 2023, 12:49 p.m. UTC | #1 
On Fri, Nov 3, 2023 at 6:34 PM Uros Bizjak <ubizjak@gmail.com> wrote:
>
> The patch generalizes address register class handling to allow multiple
> address register classes.  For APX EGPR targets, some instructions can't be
> encoded with REX2 prefix, so it is necessary to limit address register
> class to avoid REX2 registers.  The same situation happens for instructions
> with high registers, where the REX register can not be used in the address,
> so the existing infrastructure can be adapted to also handle this case.
>
> The patch is mostly a mechanical rename of "gpr32" attribute to "addr" and
> introduces no functional changes, although it fixes a couple of inconsistent
> attribute values in passing.

@@ -22569,9 +22578,8 @@ (define_insn "<sse4_1_avx2>_mpsadbw"
    mpsadbw\t{%3, %2, %0|%0, %2, %3}
    vmpsadbw\t{%3, %2, %1, %0|%0, %1, %2, %3}"
   [(set_attr "isa" "noavx,noavx,avx")
-   (set_attr "gpr32" "0,0,1")
+   (set_attr "addr" "rex")
    (set_attr "type" "sselog1")
-   (set_attr "gpr32" "0")
    (set_attr "length_immediate" "1")
    (set_attr "prefix_extra" "1")
    (set_attr "prefix" "orig,orig,vex")

I believe your fix is correct.

>
> A follow-up patch will use the above infrastructure to limit address register
> class to legacy registers for instructions with high registers.

The patch looks good to me, but please leave some time for Hongyu in
case he has any comments.

>
> gcc/ChangeLog:
>
>     * config/i386/i386.cc (ix86_memory_address_use_extended_reg_class_p):
>     Rename to ...
>     (ix86_memory_address_reg_class): ... this.  Generalize address
>     register class handling to allow multiple address register classes.
>     Return maximal class for unrecognized instructions.  Improve comments.
>     (ix86_insn_base_reg_class): Rewrite to handle
>     multiple address register classes.
>     (ix86_regno_ok_for_insn_base_p): Ditto.
>     (ix86_insn_index_reg_class): Ditto.
>     * config/i386/i386.md: Rename "gpr32" attribute to "addr"
>     and substitute its values with "0" -> "rex", "1" -> "*".
>     (addr): New attribute to limit allowed address register set.
>     (gpr32): Remove.
>     * config/i386/mmx.md: Rename "gpr32" attribute to "addr"
>     and substitute its values with "0" -> "rex", "1" -> "*".
>     * config/i386/sse.md: Ditto.
>
> Bootstrapped and regression tested on x86_64-linux-gnu {,-m32}.
>
> Comments welcome.
>
> Uros.
Hongyu Wang Nov. 3, 2023, 1:21 p.m. UTC | #2 
Thanks for the fix and refinement!

I think the addr attr looks more reasonable, just one small issue that
EGPR was not only encoded with REX2 prefix, there are several
instructions that encode EGPR using evex prefix. So I think
addr_rex2/addr_rex may be a misleading note. I'd prefer still using
gpr16/gpr32 as the name which clearly shows which type of gpr was
adopted to an address.

Hongtao Liu <crazylht@gmail.com> 于2023年11月3日周五 20:50写道：
>
> On Fri, Nov 3, 2023 at 6:34 PM Uros Bizjak <ubizjak@gmail.com> wrote:
> >
> > The patch generalizes address register class handling to allow multiple
> > address register classes.  For APX EGPR targets, some instructions can't be
> > encoded with REX2 prefix, so it is necessary to limit address register
> > class to avoid REX2 registers.  The same situation happens for instructions
> > with high registers, where the REX register can not be used in the address,
> > so the existing infrastructure can be adapted to also handle this case.
> >
> > The patch is mostly a mechanical rename of "gpr32" attribute to "addr" and
> > introduces no functional changes, although it fixes a couple of inconsistent
> > attribute values in passing.
>
> @@ -22569,9 +22578,8 @@ (define_insn "<sse4_1_avx2>_mpsadbw"
>     mpsadbw\t{%3, %2, %0|%0, %2, %3}
>     vmpsadbw\t{%3, %2, %1, %0|%0, %1, %2, %3}"
>    [(set_attr "isa" "noavx,noavx,avx")
> -   (set_attr "gpr32" "0,0,1")
> +   (set_attr "addr" "rex")
>     (set_attr "type" "sselog1")
> -   (set_attr "gpr32" "0")
>     (set_attr "length_immediate" "1")
>     (set_attr "prefix_extra" "1")
>     (set_attr "prefix" "orig,orig,vex")
>
> I believe your fix is correct.
>
> >
> > A follow-up patch will use the above infrastructure to limit address register
> > class to legacy registers for instructions with high registers.
>
> The patch looks good to me, but please leave some time for Hongyu in
> case he has any comments.
>
> >
> > gcc/ChangeLog:
> >
> >     * config/i386/i386.cc (ix86_memory_address_use_extended_reg_class_p):
> >     Rename to ...
> >     (ix86_memory_address_reg_class): ... this.  Generalize address
> >     register class handling to allow multiple address register classes.
> >     Return maximal class for unrecognized instructions.  Improve comments.
> >     (ix86_insn_base_reg_class): Rewrite to handle
> >     multiple address register classes.
> >     (ix86_regno_ok_for_insn_base_p): Ditto.
> >     (ix86_insn_index_reg_class): Ditto.
> >     * config/i386/i386.md: Rename "gpr32" attribute to "addr"
> >     and substitute its values with "0" -> "rex", "1" -> "*".
> >     (addr): New attribute to limit allowed address register set.
> >     (gpr32): Remove.
> >     * config/i386/mmx.md: Rename "gpr32" attribute to "addr"
> >     and substitute its values with "0" -> "rex", "1" -> "*".
> >     * config/i386/sse.md: Ditto.
> >
> > Bootstrapped and regression tested on x86_64-linux-gnu {,-m32}.
> >
> > Comments welcome.
> >
> > Uros.
>
>
>
> --
> BR,
> Hongtao
Uros Bizjak Nov. 3, 2023, 1:24 p.m. UTC | #3 
On Fri, Nov 3, 2023 at 2:21 PM Hongyu Wang <wwwhhhyyy333@gmail.com> wrote:
>
> Thanks for the fix and refinement!
>
> I think the addr attr looks more reasonable, just one small issue that
> EGPR was not only encoded with REX2 prefix, there are several
> instructions that encode EGPR using evex prefix. So I think
> addr_rex2/addr_rex may be a misleading note. I'd prefer still using
> gpr16/gpr32 as the name which clearly shows which type of gpr was
> adopted to an address.

No problem, I will keep gpr8/gpr16/gpr32 as "addr" values.

Thanks,
Uros.

>
> Hongtao Liu <crazylht@gmail.com> 于2023年11月3日周五 20:50写道：
> >
> > On Fri, Nov 3, 2023 at 6:34 PM Uros Bizjak <ubizjak@gmail.com> wrote:
> > >
> > > The patch generalizes address register class handling to allow multiple
> > > address register classes.  For APX EGPR targets, some instructions can't be
> > > encoded with REX2 prefix, so it is necessary to limit address register
> > > class to avoid REX2 registers.  The same situation happens for instructions
> > > with high registers, where the REX register can not be used in the address,
> > > so the existing infrastructure can be adapted to also handle this case.
> > >
> > > The patch is mostly a mechanical rename of "gpr32" attribute to "addr" and
> > > introduces no functional changes, although it fixes a couple of inconsistent
> > > attribute values in passing.
> >
> > @@ -22569,9 +22578,8 @@ (define_insn "<sse4_1_avx2>_mpsadbw"
> >     mpsadbw\t{%3, %2, %0|%0, %2, %3}
> >     vmpsadbw\t{%3, %2, %1, %0|%0, %1, %2, %3}"
> >    [(set_attr "isa" "noavx,noavx,avx")
> > -   (set_attr "gpr32" "0,0,1")
> > +   (set_attr "addr" "rex")
> >     (set_attr "type" "sselog1")
> > -   (set_attr "gpr32" "0")
> >     (set_attr "length_immediate" "1")
> >     (set_attr "prefix_extra" "1")
> >     (set_attr "prefix" "orig,orig,vex")
> >
> > I believe your fix is correct.
> >
> > >
> > > A follow-up patch will use the above infrastructure to limit address register
> > > class to legacy registers for instructions with high registers.
> >
> > The patch looks good to me, but please leave some time for Hongyu in
> > case he has any comments.
> >
> > >
> > > gcc/ChangeLog:
> > >
> > >     * config/i386/i386.cc (ix86_memory_address_use_extended_reg_class_p):
> > >     Rename to ...
> > >     (ix86_memory_address_reg_class): ... this.  Generalize address
> > >     register class handling to allow multiple address register classes.
> > >     Return maximal class for unrecognized instructions.  Improve comments.
> > >     (ix86_insn_base_reg_class): Rewrite to handle
> > >     multiple address register classes.
> > >     (ix86_regno_ok_for_insn_base_p): Ditto.
> > >     (ix86_insn_index_reg_class): Ditto.
> > >     * config/i386/i386.md: Rename "gpr32" attribute to "addr"
> > >     and substitute its values with "0" -> "rex", "1" -> "*".
> > >     (addr): New attribute to limit allowed address register set.
> > >     (gpr32): Remove.
> > >     * config/i386/mmx.md: Rename "gpr32" attribute to "addr"
> > >     and substitute its values with "0" -> "rex", "1" -> "*".
> > >     * config/i386/sse.md: Ditto.
> > >
> > > Bootstrapped and regression tested on x86_64-linux-gnu {,-m32}.
> > >
> > > Comments welcome.
> > >
> > > Uros.
> >
> >
> >
> > --
> > BR,
> > Hongtao
diff mbox series

Patch

diff --git a/gcc/config/i386/i386.cc b/gcc/config/i386/i386.cc
index 0f17f7d0258..e934b14145f 100644
--- a/gcc/config/i386/i386.cc
+++ b/gcc/config/i386/i386.cc
@@ -11357,93 +11357,110 @@  ix86_validate_address_register (rtx op)
   return NULL_RTX;
 }
 
-/* Return true if insn memory address can use any available reg
-   in BASE_REG_CLASS or INDEX_REG_CLASS, otherwise false.
-   For APX, some instruction can't be encoded with gpr32
-   which is BASE_REG_CLASS or INDEX_REG_CLASS, for that case
-   returns false.  */
-static bool
-ix86_memory_address_use_extended_reg_class_p (rtx_insn* insn)
+/* Classify which memory address registers insn can use.  */
+
+static enum attr_addr
+ix86_memory_address_reg_class (rtx_insn* insn)
 {
-  /* LRA will do some initialization with insn == NULL,
-     return the maximum reg class for that.
-     For other cases, real insn will be passed and checked.  */
-  bool ret = true;
+  /* LRA can do some initialization with NULL insn,
+     return maximum register class in this case.  */
+  enum attr_addr addr_rclass = ADDR_REX2;
+
   if (TARGET_APX_EGPR && insn)
     {
       if (asm_noperands (PATTERN (insn)) >= 0
 	  || GET_CODE (PATTERN (insn)) == ASM_INPUT)
-	return ix86_apx_inline_asm_use_gpr32;
+	return ix86_apx_inline_asm_use_gpr32 ? ADDR_REX2 : ADDR_REX;
 
+      /* Return maximum register class for unrecognized instructions.  */
       if (INSN_CODE (insn) < 0)
-	return false;
+	return addr_rclass;
 
-      /* Try recog the insn before calling get_attr_gpr32. Save
-	 the current recog_data first.  */
-      /* Also save which_alternative for current recog.  */
+      /* Try to recognize the insn before calling get_attr_addr.
+	 Save current recog_data and current alternative.  */
+      struct recog_data_d old_recog_data = recog_data;
+      int old_alternative = which_alternative;
 
-      struct recog_data_d recog_data_save = recog_data;
-      int which_alternative_saved = which_alternative;
-
-      /* Update the recog_data for alternative check. */
+      /* Update recog_data for processing of alternatives.  */
       if (recog_data.insn != insn)
 	extract_insn_cached (insn);
 
-      /* If alternative is not set, loop throught each alternative
-	 of insn and get gpr32 attr for all enabled alternatives.
-	 If any enabled alternatives has 0 value for gpr32, disallow
-	 gpr32 for addressing.  */
-      if (which_alternative_saved == -1)
+      /* If current alternative is not set, loop throught enabled
+	 alternatives and get the most limited register class.  */
+      if (old_alternative == -1)
 	{
 	  alternative_mask enabled = get_enabled_alternatives (insn);
-	  bool curr_insn_gpr32 = false;
+
 	  for (int i = 0; i < recog_data.n_alternatives; i++)
 	    {
 	      if (!TEST_BIT (enabled, i))
 		continue;
+
 	      which_alternative = i;
-	      curr_insn_gpr32 = get_attr_gpr32 (insn);
-	      if (!curr_insn_gpr32)
-		ret = false;
+	      addr_rclass = MIN (addr_rclass, get_attr_addr (insn));
 	    }
 	}
       else
 	{
-	  which_alternative = which_alternative_saved;
-	  ret = get_attr_gpr32 (insn);
+	  which_alternative = old_alternative;
+	  addr_rclass = get_attr_addr (insn);
 	}
 
-      recog_data = recog_data_save;
-      which_alternative = which_alternative_saved;
+      recog_data = old_recog_data;
+      which_alternative = old_alternative;
     }
 
-  return ret;
+  return addr_rclass;
 }
 
-/* For APX, some instructions can't be encoded with gpr32.  */
+/* Return memory address register class insn can use.  */
+
 enum reg_class
 ix86_insn_base_reg_class (rtx_insn* insn)
 {
-  if (ix86_memory_address_use_extended_reg_class_p (insn))
-    return BASE_REG_CLASS;
-  return GENERAL_GPR16;
+  switch (ix86_memory_address_reg_class (insn))
+    {
+    case ADDR_NOREX:
+      gcc_unreachable ();
+    case ADDR_REX:
+      return GENERAL_GPR16;
+    case ADDR_REX2:
+      return BASE_REG_CLASS;
+    default:
+      gcc_unreachable ();
+    }
 }
 
 bool
 ix86_regno_ok_for_insn_base_p (int regno, rtx_insn* insn)
 {
-
-  if (ix86_memory_address_use_extended_reg_class_p (insn))
-    return GENERAL_REGNO_P (regno);
-  return GENERAL_GPR16_REGNO_P (regno);
+  switch (ix86_memory_address_reg_class (insn))
+    {
+    case ADDR_NOREX:
+      gcc_unreachable ();
+    case ADDR_REX:
+      return GENERAL_GPR16_REGNO_P (regno);
+    case ADDR_REX2:
+      return GENERAL_REGNO_P (regno);
+    default:
+      gcc_unreachable ();
+    }
 }
 
 enum reg_class
 ix86_insn_index_reg_class (rtx_insn* insn)
 {
-  if (ix86_memory_address_use_extended_reg_class_p (insn))
-    return INDEX_REG_CLASS;
-  return INDEX_GPR16;
+  switch (ix86_memory_address_reg_class (insn))
+    {
+    case ADDR_NOREX:
+      gcc_unreachable ();
+    case ADDR_REX:
+      return INDEX_GPR16;
+    case ADDR_REX2:
+      return INDEX_REG_CLASS;
+    default:
+      gcc_unreachable ();
+    }
 }
 
 /* Recognizes RTL expressions that are valid memory addresses for an
diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md
index 663db73707a..c7ff481a5e5 100644
--- a/gcc/config/i386/i386.md
+++ b/gcc/config/i386/i386.md
@@ -882,8 +882,8 @@  (define_attr "use_carry" "0,1" (const_string "0"))
 ;; Define attribute to indicate unaligned ssemov insns
 (define_attr "movu" "0,1" (const_string "0"))
 
-;; Define attribute to indicate gpr32 insns.
-(define_attr "gpr32" "0, 1" (const_string "1"))
+;; Define attribute to limit allowed address register set.
+(define_attr "addr" "norex,rex,rex2" (const_string "rex2"))
 
 ;; Define instruction set of MMX instructions
 (define_attr "mmx_isa" "base,native,sse,sse_noavx,avx"
@@ -2987,10 +2987,10 @@  (define_insn "*movhi_internal"
 		  (const_string "avx")
 	       ]
 	       (const_string "*")))
-   (set (attr "gpr32")
+   (set (attr "addr")
 	(if_then_else (eq_attr "alternative" "14")
-		      (const_string "0")
-		      (const_string "1")))
+		      (const_string "rex")
+		      (const_string "*")))
    (set (attr "type")
      (cond [(eq_attr "alternative" "4,5,6,7")
 	      (const_string "mskmov")
@@ -4470,10 +4470,10 @@  (define_insn "*mov<mode>_internal"
 		 (const_string "avx")
 	      ]
 	      (const_string "*")))
-   (set (attr "gpr32")
-	(if_then_else (eq_attr "alternative" "8")
-		      (const_string "0")
-		      (const_string "1")))
+   (set (attr "addr")
+	(if_then_else (eq_attr "alternative" "7")
+		      (const_string "rex")
+		      (const_string "*")))
    (set (attr "type")
 	(cond [(eq_attr "alternative" "4")
 		 (const_string "sselog1")
@@ -16913,7 +16913,7 @@  (define_insn "setcc_<mode>_sse"
    cmp%D3<ssemodesuffix>\t{%2, %0|%0, %2}
    vcmp%D3<ssemodesuffix>\t{%2, %1, %0|%0, %1, %2}"
   [(set_attr "isa" "noavx,avx")
-   (set_attr "gpr32" "1,0")
+   (set_attr "addr" "*,rex")
    (set_attr "type" "ssecmp")
    (set_attr "length_immediate" "1")
    (set_attr "prefix" "orig,vex")
@@ -20379,7 +20379,7 @@  (define_insn "*rcpsf2_sse"
    rcpss\t{%1, %d0|%d0, %1}
    vrcpss\t{%1, %d0|%d0, %1}"
   [(set_attr "isa" "*,*,noavx,avx")
-   (set_attr "gpr32" "1,1,1,0")
+   (set_attr "addr" "*,*,*,rex")
    (set_attr "type" "sse")
    (set_attr "atom_sse_attr" "rcp")
    (set_attr "btver2_sse_attr" "rcp")
@@ -20642,7 +20642,7 @@  (define_insn "*rsqrtsf2_sse"
    rsqrtss\t{%1, %d0|%d0, %1}
    vrsqrtss\t{%1, %d0|%d0, %1}"
   [(set_attr "isa" "*,*,noavx,avx")
-   (set_attr "gpr32" "1,1,1,0")
+   (set_attr "addr" "*,*,*,rex")
    (set_attr "type" "sse")
    (set_attr "atom_sse_attr" "rcp")
    (set_attr "btver2_sse_attr" "rcp")
@@ -21881,7 +21881,7 @@  (define_insn "sse4_1_round<mode>2"
   [(set_attr "type" "ssecvt")
    (set_attr "prefix_extra" "1,1,1,*,*")
    (set_attr "length_immediate" "1")
-   (set_attr "gpr32" "1,1,0,1,1")
+   (set_attr "addr" "*,*,rex,*,*")
    (set_attr "prefix" "maybe_vex,maybe_vex,maybe_vex,evex,evex")
    (set_attr "isa" "noavx512f,noavx512f,noavx512f,avx512f,avx512f")
    (set_attr "avx_partial_xmm_update" "false,false,true,false,true")
@@ -25924,7 +25924,7 @@  (define_insn "fxsave64"
   "TARGET_64BIT && TARGET_FXSR"
   "fxsave64\t%0"
   [(set_attr "type" "other")
-   (set_attr "gpr32" "0")
+   (set_attr "addr" "rex")
    (set_attr "memory" "store")
    (set (attr "length")
         (symbol_ref "ix86_attr_length_address_default (insn) + 4"))])
@@ -25945,7 +25945,7 @@  (define_insn "fxrstor64"
   "TARGET_64BIT && TARGET_FXSR"
   "fxrstor64\t%0"
   [(set_attr "type" "other")
-   (set_attr "gpr32" "0")
+   (set_attr "addr" "rex")
    (set_attr "memory" "load")
    (set (attr "length")
         (symbol_ref "ix86_attr_length_address_default (insn) + 4"))])
@@ -26008,7 +26008,7 @@  (define_insn "<xsave>_rex64"
   "<xsave>\t%0"
   [(set_attr "type" "other")
    (set_attr "memory" "store")
-   (set_attr "gpr32" "0")
+   (set_attr "addr" "rex")
    (set (attr "length")
         (symbol_ref "ix86_attr_length_address_default (insn) + 3"))])
 
@@ -26022,7 +26022,7 @@  (define_insn "<xsave>"
   "<xsave>\t%0"
   [(set_attr "type" "other")
    (set_attr "memory" "store")
-   (set_attr "gpr32" "0")
+   (set_attr "addr" "rex")
    (set (attr "length")
         (symbol_ref "ix86_attr_length_address_default (insn) + 4"))])
 
@@ -26048,7 +26048,7 @@  (define_insn "<xrstor>_rex64"
   "<xrstor>\t%0"
   [(set_attr "type" "other")
    (set_attr "memory" "load")
-   (set_attr "gpr32" "0")
+   (set_attr "addr" "rex")
    (set (attr "length")
         (symbol_ref "ix86_attr_length_address_default (insn) + 3"))])
 
@@ -26062,7 +26062,7 @@  (define_insn "<xrstor>64"
   "<xrstor>64\t%0"
   [(set_attr "type" "other")
    (set_attr "memory" "load")
-   (set_attr "gpr32" "0")
+   (set_attr "addr" "rex")
    (set (attr "length")
         (symbol_ref "ix86_attr_length_address_default (insn) + 4"))])
 
diff --git a/gcc/config/i386/mmx.md b/gcc/config/i386/mmx.md
index ba81ff72551..c3c24fab6ff 100644
--- a/gcc/config/i386/mmx.md
+++ b/gcc/config/i386/mmx.md
@@ -467,10 +467,10 @@  (define_insn "*movv2qi_internal"
 		  (const_string "avx")
 	       ]
 	       (const_string "*")))
-   (set (attr "gpr32")
+   (set (attr "addr")
 	(if_then_else (eq_attr "alternative" "7")
-		      (const_string "0")
-		      (const_string "1")))
+		      (const_string "rex")
+		      (const_string "*")))
    (set (attr "type")
      (cond [(eq_attr "alternative" "6,7,8")
 	      (if_then_else (match_test "TARGET_AVX512FP16")
@@ -1205,7 +1205,7 @@  (define_insn "@sse4_1_insertps_<mode>"
     }
 }
   [(set_attr "isa" "noavx,noavx,avx")
-   (set_attr "gpr32" "0,0,1")
+   (set_attr "addr" "*,*,rex")
    (set_attr "type" "sselog")
    (set_attr "prefix_data16" "1,1,*")
    (set_attr "prefix_extra" "1")
@@ -4874,7 +4874,7 @@  (define_insn "*mmx_pinsrd"
     }
 }
   [(set_attr "isa" "noavx,avx")
-   (set_attr "gpr32" "0,1")
+   (set_attr "addr" "rex,*")
    (set_attr "prefix_extra" "1")
    (set_attr "type" "sselog")
    (set_attr "length_immediate" "1")
@@ -4947,7 +4947,7 @@  (define_insn "*mmx_pinsrb"
 }
   [(set_attr "isa" "noavx,avx")
    (set_attr "type" "sselog")
-   (set_attr "gpr32" "0,1")
+   (set_attr "addr" "rex,*")
    (set_attr "prefix_extra" "1")
    (set_attr "length_immediate" "1")
    (set_attr "prefix" "orig,vex")
@@ -4966,7 +4966,7 @@  (define_insn "*mmx_pextrw"
    pextrw\t{%2, %1, %0|%0, %1, %2}
    vpextrw\t{%2, %1, %0|%0, %1, %2}"
   [(set_attr "isa" "*,sse2,sse4_noavx,avx")
-   (set_attr "gpr32" "1,1,0,1")
+   (set_attr "addr" "*,*,rex,*")
    (set_attr "mmx_isa" "native,*,*,*")
    (set_attr "type" "mmxcvt,sselog1,sselog1,sselog1")
    (set_attr "length_immediate" "1")
@@ -5003,7 +5003,7 @@  (define_insn "*mmx_pextrb"
    vpextrb\t{%2, %1, %k0|%k0, %1, %2}
    vpextrb\t{%2, %1, %0|%0, %1, %2}"
   [(set_attr "isa" "noavx,noavx,avx,avx")
-   (set_attr "gpr32" "1,0,1,1")
+   (set_attr "addr" "*,rex,*,*")
    (set_attr "type" "sselog1")
    (set_attr "prefix_extra" "1")
    (set_attr "length_immediate" "1")
@@ -5036,7 +5036,7 @@  (define_insn "mmx_pshufbv8qi3"
    pshufb\t{%2, %0|%0, %2}
    vpshufb\t{%2, %1, %0|%0, %1, %2}"
   [(set_attr "isa" "noavx,avx")
-   (set_attr "gpr32" "0,1")
+   (set_attr "addr" "rex,*")
    (set_attr "type" "sselog1")
    (set_attr "prefix_extra" "1")
    (set_attr "prefix" "orig,maybe_evex")
@@ -5054,7 +5054,7 @@  (define_insn "mmx_pshufbv4qi3"
    pshufb\t{%2, %0|%0, %2}
    vpshufb\t{%2, %1, %0|%0, %1, %2}"
   [(set_attr "isa" "noavx,avx")
-   (set_attr "gpr32" "0,1")
+   (set_attr "addr" "rex,*")
    (set_attr "type" "sselog1")
    (set_attr "prefix_extra" "1")
    (set_attr "prefix" "orig,maybe_evex")
@@ -5330,7 +5330,10 @@  (define_insn "*vec_extractv2si_1"
    #
    #"
   [(set_attr "isa" "*,sse4_noavx,avx,sse2,noavx,*,*,*")
-   (set_attr "gpr32" "1,0,1,1,1,1,1,1")
+   (set (attr "addr")
+	(if_then_else (eq_attr "alternative" "1")
+		      (const_string "rex")
+		      (const_string "*")))
    (set_attr "mmx_isa" "native,*,*,*,*,native,*,*")
    (set_attr "type" "mmxcvt,ssemov,ssemov,sseshuf1,sseshuf1,mmxmov,ssemov,imov")
    (set (attr "length_immediate")
@@ -5534,7 +5537,7 @@  (define_insn "*pinsrb"
     }
 }
   [(set_attr "isa" "noavx,avx")
-   (set_attr "gpr32" "0,1")
+   (set_attr "addr" "rex,*")
    (set_attr "type" "sselog")
    (set_attr "prefix_extra" "1")
    (set_attr "length_immediate" "1")
@@ -5552,7 +5555,7 @@  (define_insn "*pextrw"
    pextrw\t{%2, %1, %0|%0, %1, %2}
    vpextrw\t{%2, %1, %0|%0, %1, %2}"
   [(set_attr "isa" "*,sse4_noavx,avx")
-   (set_attr "gpr32" "1,0,1")
+   (set_attr "addr" "*,rex,*")
    (set_attr "type" "sselog1")
    (set_attr "length_immediate" "1")
    (set_attr "prefix" "maybe_vex")
@@ -5583,7 +5586,7 @@  (define_insn "*pextrb"
    vpextrb\t{%2, %1, %k0|%k0, %1, %2}
    vpextrb\t{%2, %1, %0|%0, %1, %2}"
   [(set_attr "isa" "noavx,noavx,avx,avx")
-   (set_attr "gpr32" "1,0,1,1")
+   (set_attr "addr" "*,rex,*,*")
    (set_attr "type" "sselog1")
    (set_attr "prefix_extra" "1")
    (set_attr "length_immediate" "1")
diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md
index 906212fb4c1..5cf3c50a584 100644
--- a/gcc/config/i386/sse.md
+++ b/gcc/config/i386/sse.md
@@ -1874,7 +1874,7 @@  (define_insn "<sse3>_lddqu<avxsizesuffix>"
   "%vlddqu\t{%1, %0|%0, %1}"
   [(set_attr "isa" "noavx,avx")
    (set_attr "type" "ssemov")
-   (set_attr "gpr32" "1,0")
+   (set_attr "addr" "*,rex")
    (set_attr "movu" "1")
    (set (attr "prefix_data16")
      (if_then_else
@@ -2578,7 +2578,7 @@  (define_insn "<sse>_rcp<mode>2"
   "%vrcpps\t{%1, %0|%0, %1}"
   [(set_attr "isa" "noavx,avx")
    (set_attr "type" "sse")
-   (set_attr "gpr32" "1,0")
+   (set_attr "addr" "*,rex")
    (set_attr "atom_sse_attr" "rcp")
    (set_attr "btver2_sse_attr" "rcp")
    (set_attr "prefix" "maybe_vex")
@@ -2597,7 +2597,7 @@  (define_insn "sse_vmrcpv4sf2"
    vrcpss\t{%1, %2, %0|%0, %2, %k1}"
   [(set_attr "isa" "noavx,avx")
    (set_attr "type" "sse")
-   (set_attr "gpr32" "1,0")
+   (set_attr "addr" "*,rex")
    (set_attr "atom_sse_attr" "rcp")
    (set_attr "btver2_sse_attr" "rcp")
    (set_attr "prefix" "orig,vex")
@@ -2617,7 +2617,7 @@  (define_insn "*sse_vmrcpv4sf2"
    vrcpss\t{%1, %2, %0|%0, %2, %1}"
   [(set_attr "isa" "noavx,avx")
    (set_attr "type" "sse")
-   (set_attr "gpr32" "1,0")
+   (set_attr "addr" "*,rex")
    (set_attr "atom_sse_attr" "rcp")
    (set_attr "btver2_sse_attr" "rcp")
    (set_attr "prefix" "orig,vex")
@@ -2801,7 +2801,7 @@  (define_insn "<sse>_rsqrt<mode>2"
   "%vrsqrtps\t{%1, %0|%0, %1}"
   [(set_attr "isa" "noavx,avx")
    (set_attr "type" "sse")
-   (set_attr "gpr32" "1,0")
+   (set_attr "addr" "*,rex")
    (set_attr "prefix" "maybe_vex")
    (set_attr "mode" "<MODE>")])
 
@@ -2870,7 +2870,7 @@  (define_insn "sse_vmrsqrtv4sf2"
    vrsqrtss\t{%1, %2, %0|%0, %2, %k1}"
   [(set_attr "isa" "noavx,avx")
    (set_attr "type" "sse")
-   (set_attr "gpr32" "1,0")
+   (set_attr "addr" "*,rex")
    (set_attr "prefix" "orig,vex")
    (set_attr "mode" "SF")])
 
@@ -2888,7 +2888,7 @@  (define_insn "*sse_vmrsqrtv4sf2"
    vrsqrtss\t{%1, %2, %0|%0, %2, %1}"
   [(set_attr "isa" "noavx,avx")
    (set_attr "type" "sse")
-   (set_attr "gpr32" "1,0")
+   (set_attr "addr" "*,rex")
    (set_attr "prefix" "orig,vex")
    (set_attr "mode" "SF")])
 
@@ -3073,7 +3073,7 @@  (define_insn "vec_addsub<mode>3"
    vaddsub<ssemodesuffix>\t{%2, %1, %0|%0, %1, %2}"
   [(set_attr "isa" "noavx,avx")
    (set_attr "type" "sseadd")
-   (set_attr "gpr32" "1,0")
+   (set_attr "addr" "*,rex")
    (set (attr "atom_unit")
      (if_then_else
        (match_test "<MODE>mode == V2DFmode")
@@ -3230,7 +3230,7 @@  (define_insn "avx_h<insn>v4df3"
   "TARGET_AVX"
   "vh<plusminus_mnemonic>pd\t{%2, %1, %0|%0, %1, %2}"
   [(set_attr "type" "sseadd")
-   (set_attr "gpr32" "0")
+   (set_attr "addr" "rex")
    (set_attr "prefix" "vex")
    (set_attr "mode" "V4DF")])
 
@@ -3273,7 +3273,7 @@  (define_insn "*sse3_haddv2df3"
    haddpd\t{%2, %0|%0, %2}
    vhaddpd\t{%2, %1, %0|%0, %1, %2}"
   [(set_attr "isa" "noavx,avx")
-   (set_attr "gpr32" "1,0")
+   (set_attr "addr" "*,rex")
    (set_attr "type" "sseadd")
    (set_attr "prefix" "orig,vex")
    (set_attr "mode" "V2DF")])
@@ -3297,7 +3297,7 @@  (define_insn "sse3_hsubv2df3"
    vhsubpd\t{%2, %1, %0|%0, %1, %2}"
   [(set_attr "isa" "noavx,avx")
    (set_attr "type" "sseadd")
-   (set_attr "gpr32" "1,0")
+   (set_attr "addr" "*,rex")
    (set_attr "prefix" "orig,vex")
    (set_attr "mode" "V2DF")])
 
@@ -3378,7 +3378,7 @@  (define_insn "avx_h<insn>v8sf3"
   "TARGET_AVX"
   "vh<plusminus_mnemonic>ps\t{%2, %1, %0|%0, %1, %2}"
   [(set_attr "type" "sseadd")
-   (set_attr "gpr32" "0")
+   (set_attr "addr" "rex")
    (set_attr "prefix" "vex")
    (set_attr "mode" "V8SF")])
 
@@ -3409,7 +3409,7 @@  (define_insn "sse3_h<insn>v4sf3"
    vh<plusminus_mnemonic>ps\t{%2, %1, %0|%0, %1, %2}"
   [(set_attr "isa" "noavx,avx")
    (set_attr "type" "sseadd")
-   (set_attr "gpr32" "1,0")
+   (set_attr "addr" "*,rex")
    (set_attr "atom_unit" "complex")
    (set_attr "prefix" "orig,vex")
    (set_attr "prefix_rep" "1,*")
@@ -3613,7 +3613,7 @@  (define_insn "avx_cmp<mode>3"
   "TARGET_AVX"
   "vcmp<ssemodesuffix>\t{%3, %2, %1, %0|%0, %1, %2, %3}"
   [(set_attr "type" "ssecmp")
-   (set_attr "gpr32" "0")
+   (set_attr "addr" "rex")
    (set_attr "length_immediate" "1")
    (set_attr "prefix" "vex")
    (set_attr "mode" "<MODE>")])
@@ -3827,7 +3827,7 @@  (define_insn "avx_vmcmp<mode>3"
   "TARGET_AVX"
   "vcmp<ssescalarmodesuffix>\t{%3, %2, %1, %0|%0, %1, %<iptr>2, %3}"
   [(set_attr "type" "ssecmp")
-   (set_attr "gpr32" "0")
+   (set_attr "addr" "rex")
    (set_attr "length_immediate" "1")
    (set_attr "prefix" "vex")
    (set_attr "mode" "<ssescalarmode>")])
@@ -3843,7 +3843,7 @@  (define_insn "*<sse>_maskcmp<mode>3_comm"
    cmp%D3<ssemodesuffix>\t{%2, %0|%0, %2}
    vcmp%D3<ssemodesuffix>\t{%2, %1, %0|%0, %1, %2}"
   [(set_attr "isa" "noavx,avx")
-   (set_attr "gpr32" "1,0")
+   (set_attr "addr" "*,rex")
    (set_attr "type" "ssecmp")
    (set_attr "length_immediate" "1")
    (set_attr "prefix" "orig,vex")
@@ -3859,7 +3859,7 @@  (define_insn "<sse>_maskcmp<mode>3"
    cmp%D3<ssemodesuffix>\t{%2, %0|%0, %2}
    vcmp%D3<ssemodesuffix>\t{%2, %1, %0|%0, %1, %2}"
   [(set_attr "isa" "noavx,avx")
-   (set_attr "gpr32" "1,0")
+   (set_attr "addr" "*,rex")
    (set_attr "type" "ssecmp")
    (set_attr "length_immediate" "1")
    (set_attr "prefix" "orig,vex")
@@ -3878,7 +3878,7 @@  (define_insn "<sse>_vmmaskcmp<mode>3"
    cmp%D3<ssescalarmodesuffix>\t{%2, %0|%0, %<iptr>2}
    vcmp%D3<ssescalarmodesuffix>\t{%2, %1, %0|%0, %1, %<iptr>2}"
   [(set_attr "isa" "noavx,avx")
-   (set_attr "gpr32" "1,0")
+   (set_attr "addr" "*,rex")
    (set_attr "type" "ssecmp")
    (set_attr "length_immediate" "1,*")
    (set_attr "prefix" "orig,vex")
@@ -4826,7 +4826,7 @@  (define_insn "<sse>_andnot<mode>3<mask_name>"
   return "";
 }
   [(set_attr "isa" "noavx,avx_noavx512f,avx512dq,avx512f")
-   (set_attr "gpr32" "1,0,1,1")
+   (set_attr "addr" "*,rex,*,*")
    (set_attr "type" "sselog")
    (set_attr "prefix" "orig,maybe_vex,evex,evex")
    (set (attr "mode")
@@ -5170,7 +5170,7 @@  (define_insn "*andnot<mode>3"
   return "";
 }
   [(set_attr "isa" "noavx,avx_noavx512f,avx512vl,avx512f_512")
-   (set_attr "gpr32" "1,0,1,1")
+   (set_attr "addr" "*,rex,*,*")
    (set_attr "type" "sselog")
    (set (attr "prefix_data16")
      (if_then_else
@@ -10958,10 +10958,10 @@  (define_insn "*vec_concatv2sf_sse4_1"
      (if_then_else (eq_attr "alternative" "7,8")
 		   (const_string "native")
 		   (const_string "*")))
-   (set (attr "gpr32")
+   (set (attr "addr")
      (if_then_else (eq_attr "alternative" "3,4")
-		   (const_string "0")
-		   (const_string "1")))
+		   (const_string "rex")
+		   (const_string "*")))
    (set (attr "prefix_data16")
      (if_then_else (eq_attr "alternative" "3,4")
 		   (const_string "1")
@@ -11093,10 +11093,10 @@  (define_insn "vec_set<mode>_0"
 	      (const_string "fmov")
 	   ]
 	   (const_string "ssemov")))
-   (set (attr "gpr32")
+   (set (attr "addr")
      (if_then_else (eq_attr "alternative" "8,9")
-		   (const_string "0")
-		   (const_string "1")))
+		   (const_string "rex")
+		   (const_string "*")))
    (set (attr "prefix_extra")
      (if_then_else (eq_attr "alternative" "8,9,10")
 		   (const_string "1")
@@ -11288,7 +11288,7 @@  (define_insn "*vec_setv4sf_sse4_1"
 }
   [(set_attr "isa" "noavx,noavx,avx")
    (set_attr "type" "sselog")
-   (set_attr "gpr32" "0,0,1")
+   (set_attr "addr" "rex,rex,*")
    (set_attr "prefix_data16" "1,1,*")
    (set_attr "prefix_extra" "1")
    (set_attr "length_immediate" "1")
@@ -11389,7 +11389,7 @@  (define_insn "@sse4_1_insertps_<mode>"
     }
 }
   [(set_attr "isa" "noavx,noavx,avx")
-   (set_attr "gpr32" "0,0,1")
+   (set_attr "addr" "rex,rex,*")
    (set_attr "type" "sselog")
    (set_attr "prefix_data16" "1,1,*")
    (set_attr "prefix_extra" "1")
@@ -11501,7 +11501,7 @@  (define_insn_and_split "*sse4_1_extractps"
   DONE;
 }
   [(set_attr "isa" "noavx,noavx,avx,noavx,avx")
-   (set_attr "gpr32" "0,0,1,1,1")
+   (set_attr "addr" "rex,rex,*,*,*")
    (set_attr "type" "sselog,sselog,sselog,*,*")
    (set_attr "prefix_data16" "1,1,1,*,*")
    (set_attr "prefix_extra" "1,1,1,*,*")
@@ -12354,7 +12354,7 @@  (define_insn "vec_extract_hi_v32qi"
    (set_attr "prefix_extra" "1")
    (set_attr "length_immediate" "1")
    (set_attr "isa" "noavx512vl,avx512vl")
-   (set_attr "gpr32" "0,1")
+   (set_attr "addr" "rex,*")
    (set_attr "prefix" "vex,evex")
    (set_attr "mode" "OI")])
 
@@ -12400,7 +12400,7 @@  (define_insn "*vec_extract<mode>"
    }
 }
   [(set_attr "isa" "*,sse4_noavx,avx,noavx,avx")
-   (set_attr "gpr32" "1,0,1,1,1")
+   (set_attr "addr" "*,rex,*,*,*")
    (set_attr "type" "sselog1,sselog1,sselog1,sseishft1,sseishft1")
    (set_attr "prefix" "maybe_evex")
    (set_attr "mode" "TI")])
@@ -15774,7 +15774,7 @@  (define_insn "*sse4_1_mulv2siv2di3<mask_name>"
    pmuldq\t{%2, %0|%0, %2}
    vpmuldq\t{%2, %1, %0<mask_operand3>|%0<mask_operand3>, %1, %2}"
   [(set_attr "isa" "noavx,noavx,avx")
-   (set_attr "gpr32" "0,0,1")
+   (set_attr "addr" "rex,rex,*")
    (set_attr "type" "sseimul")
    (set_attr "prefix_extra" "1")
    (set_attr "prefix" "orig,orig,vex")
@@ -16020,7 +16020,7 @@  (define_insn "*<sse4_1_avx2>_mul<mode>3<mask_name>"
    pmulld\t{%2, %0|%0, %2}
    vpmulld\t{%2, %1, %0<mask_operand3>|%0<mask_operand3>, %1, %2}"
   [(set_attr "isa" "noavx,noavx,avx")
-   (set_attr "gpr32" "0,0,1")
+   (set_attr "addr" "rex,rex,*")
    (set_attr "type" "sseimul")
    (set_attr "prefix_extra" "1")
    (set_attr "prefix" "<bcst_mask_prefix4>")
@@ -16836,7 +16836,7 @@  (define_insn "*sse4_1_<code><mode>3<mask_name>"
   [(set_attr "isa" "noavx,noavx,avx")
    (set_attr "type" "sseiadd")
    (set_attr "prefix_extra" "1")
-   (set_attr "gpr32" "0,0,1")
+   (set_attr "addr" "rex,rex,*")
    (set_attr "prefix" "orig,orig,vex")
    (set_attr "mode" "TI")])
 
@@ -16851,7 +16851,7 @@  (define_insn "*<code>v8hi3"
    vp<maxmin_int>w\t{%2, %1, %0|%0, %1, %2}"
   [(set_attr "isa" "noavx,avx")
    (set_attr "type" "sseiadd")
-   (set_attr "gpr32" "0,1")
+   (set_attr "addr" "rex,*")
    (set_attr "prefix" "orig,vex")
    (set_attr "mode" "TI")])
 
@@ -16919,7 +16919,7 @@  (define_insn "*sse4_1_<code><mode>3<mask_name>"
    vp<maxmin_int><ssemodesuffix>\t{%2, %1, %0<mask_operand3>|%0<mask_operand3>, %1, %2}"
   [(set_attr "isa" "noavx,noavx,avx")
    (set_attr "type" "sseiadd")
-   (set_attr "gpr32" "0,0,1")
+   (set_attr "addr" "rex,rex,*")
    (set_attr "prefix_extra" "1,1,*")
    (set_attr "prefix" "orig,orig,vex")
    (set_attr "mode" "TI")])
@@ -16934,7 +16934,7 @@  (define_insn "*<code>v16qi3"
    p<maxmin_int>b\t{%2, %0|%0, %2}
    vp<maxmin_int>b\t{%2, %1, %0|%0, %1, %2}"
   [(set_attr "isa" "noavx,avx")
-   (set_attr "gpr32" "0,1")
+   (set_attr "addr" "rex,*")
    (set_attr "type" "sseiadd")
    (set_attr "prefix" "orig,vex")
    (set_attr "mode" "TI")])
@@ -16957,7 +16957,7 @@  (define_insn "*avx2_eq<mode>3"
      (if_then_else (eq (const_string "<MODE>mode") (const_string "V4DImode"))
 		   (const_string "1")
 		   (const_string "*")))
-   (set_attr "gpr32" "0")
+   (set_attr "addr" "rex")
    (set_attr "prefix" "vex")
    (set_attr "mode" "OI")])
 
@@ -17148,7 +17148,7 @@  (define_insn "*sse4_1_eqv2di3"
    vpcmpeqq\t{%2, %1, %0|%0, %1, %2}"
   [(set_attr "isa" "noavx,noavx,avx")
    (set_attr "type" "ssecmp")
-   (set_attr "gpr32" "0")
+   (set_attr "addr" "rex")
    (set_attr "prefix_extra" "1")
    (set_attr "prefix" "orig,orig,vex")
    (set_attr "mode" "TI")])
@@ -17164,7 +17164,7 @@  (define_insn "*sse2_eq<mode>3"
    pcmpeq<ssemodesuffix>\t{%2, %0|%0, %2}
    vpcmpeq<ssemodesuffix>\t{%2, %1, %0|%0, %1, %2}"
   [(set_attr "isa" "noavx,avx")
-   (set_attr "gpr32" "1,0")
+   (set_attr "addr" "*,rex")
    (set_attr "type" "ssecmp")
    (set_attr "prefix" "orig,vex")
    (set_attr "mode" "TI")])
@@ -17181,7 +17181,7 @@  (define_insn "sse4_2_gtv2di3"
    vpcmpgtq\t{%2, %1, %0|%0, %1, %2}"
   [(set_attr "isa" "noavx,noavx,avx")
    (set_attr "type" "ssecmp")
-   (set_attr "gpr32" "0")
+   (set_attr "addr" "rex")
    (set_attr "prefix_extra" "1")
    (set_attr "prefix" "orig,orig,vex")
    (set_attr "mode" "TI")])
@@ -17198,7 +17198,7 @@  (define_insn "avx2_gt<mode>3"
      (if_then_else (eq (const_string "<MODE>mode") (const_string "V4DImode"))
 		   (const_string "1")
 		   (const_string "*")))
-   (set_attr "gpr32" "0")
+   (set_attr "addr" "rex")
    (set_attr "prefix" "vex")
    (set_attr "mode" "OI")])
 
@@ -17228,7 +17228,7 @@  (define_insn "*sse2_gt<mode>3"
    pcmpgt<ssemodesuffix>\t{%2, %0|%0, %2}
    vpcmpgt<ssemodesuffix>\t{%2, %1, %0|%0, %1, %2}"
   [(set_attr "isa" "noavx,avx")
-   (set_attr "gpr32" "1,0")
+   (set_attr "addr" "*,rex")
    (set_attr "type" "ssecmp")
    (set_attr "prefix" "orig,vex")
    (set_attr "mode" "TI")])
@@ -17637,7 +17637,7 @@  (define_insn "*andnot<mode>3"
   return "";
 }
   [(set_attr "isa" "noavx,avx_noavx512f,avx512f,*,*")
-   (set_attr "gpr32" "1,0,1,1,1")
+   (set_attr "addr" "*,rex,*,*,*")
    (set_attr "type" "sselog")
    (set (attr "prefix_data16")
      (if_then_else
@@ -17868,7 +17868,7 @@  (define_insn "*<code><mode>3<mask_name>"
   return "";
 }
   [(set_attr "isa" "noavx,avx_noavx512f,avx512f")
-   (set_attr "gpr32" "1,0,1")
+   (set_attr "addr" "*,rex,*")
    (set_attr "type" "sselog")
    (set (attr "prefix_data16")
      (if_then_else
@@ -17965,7 +17965,7 @@  (define_insn "*<code><mode>3"
   return "";
 }
   [(set_attr "isa" "noavx,avx_noavx512f,avx512f")
-   (set_attr "gpr32" "1,0,1")
+   (set_attr "addr" "*,rex,*")
    (set_attr "type" "sselog")
    (set (attr "prefix_data16")
      (if_then_else
@@ -17999,7 +17999,7 @@  (define_insn "<code>v1ti3"
    vp<logic>\t{%2, %1, %0|%0, %1, %2}
    vp<logic>d\t{%2, %1, %0|%0, %1, %2}"
   [(set_attr "isa" "noavx,avx_noavx512vl,avx512vl")
-   (set_attr "gpr32" "1,0,1")
+   (set_attr "addr" "*,rex,*")
    (set_attr "prefix" "orig,vex,evex")
    (set_attr "prefix_data16" "1,*,*")
    (set_attr "type" "sselog")
@@ -18980,7 +18980,10 @@  (define_insn "<sse2p4_1>_pinsr<ssemodesuffix>"
 }
   [(set_attr "isa" "noavx,noavx,avx,avx,<pinsr_evex_isa>,<pinsr_evex_isa>,avx2")
    (set_attr "type" "sselog")
-   (set_attr "gpr32" "0,0,1,1,1,1,1")
+   (set (attr "addr")
+	(if_then_else (eq_attr "alternative" "0,1")
+		      (const_string "rex")
+		      (const_string "*")))
    (set (attr "prefix_rex")
      (if_then_else
        (and (not (match_test "TARGET_AVX"))
@@ -20157,7 +20160,7 @@  (define_insn "*vec_extract<mode>"
    pextr<ssemodesuffix>\t{%2, %1, %0|%0, %1, %2}
    vpextr<ssemodesuffix>\t{%2, %1, %0|%0, %1, %2}"
   [(set_attr "isa" "sse2_noavx,avx,sse4_noavx,avx")
-   (set_attr "gpr32" "1,1,0,1")
+   (set_attr "addr" "*,*,rex,*")
    (set_attr "type" "sselog1")
    (set (attr "prefix_extra")
      (if_then_else
@@ -20334,7 +20337,10 @@  (define_insn "*vec_extractv4si"
 }
   [(set_attr "isa" "noavx,avx,avx512dq,noavx,noavx,avx")
    (set_attr "type" "sselog1,sselog1,sselog1,sseishft1,sseishft1,sseishft1")
-   (set_attr "gpr32" "0,1,1,1,1,1")
+   (set (attr "addr")
+	(if_then_else (eq_attr "alternative" "0")
+		      (const_string "rex")
+		      (const_string "*")))
    (set (attr "prefix_extra")
      (if_then_else (eq_attr "alternative" "0,1")
 		   (const_string "1")
@@ -20425,7 +20431,10 @@  (define_insn "*vec_extractv2di_1"
 	      (const_string "imov")
 	   ]
 	   (const_string "sselog1")))
-   (set_attr "gpr32" "0,1,1,1,1,1,1,1,1,1")
+   (set (attr "addr")
+	(if_then_else (eq_attr "alternative" "0")
+		      (const_string "rex")
+		      (const_string "*")))
    (set (attr "length_immediate")
      (if_then_else (eq_attr "alternative" "0,1,2,4,5,6")
 		   (const_string "1")
@@ -20585,10 +20594,10 @@  (define_insn "*vec_concatv2si_sse4_1"
 	      (const_string "mmxmov")
 	   ]
 	   (const_string "sselog")))
-   (set (attr "gpr32")
+   (set (attr "addr")
      (if_then_else (eq_attr "alternative" "0,1")
-		   (const_string "0")
-		   (const_string "1")))
+		   (const_string "rex")
+		   (const_string "*")))
    (set (attr "prefix_extra")
      (if_then_else (eq_attr "alternative" "0,1,2,3")
 		   (const_string "1")
@@ -20743,10 +20752,10 @@  (define_insn "vec_concatv2di"
        (eq_attr "alternative" "0,1,2,3,4,5")
        (const_string "sselog")
        (const_string "ssemov")))
-   (set (attr "gpr32")
+   (set (attr "addr")
      (if_then_else (eq_attr "alternative" "0,1")
-		   (const_string "0")
-		   (const_string "1")))
+		   (const_string "rex")
+		   (const_string "*")))
    (set (attr "prefix_rex")
      (if_then_else (eq_attr "alternative" "0,1,2,3")
 		   (const_string "1")
@@ -21339,7 +21348,7 @@  (define_insn "sse_ldmxcsr"
   "%vldmxcsr\t%0"
   [(set_attr "isa" "noavx,avx")
    (set_attr "type" "sse")
-   (set_attr "gpr32" "1,0")
+   (set_attr "addr" "*,rex")
    (set_attr "atom_sse_attr" "mxcsr")
    (set_attr "prefix" "maybe_vex")
    (set_attr "memory" "load")])
@@ -21351,7 +21360,7 @@  (define_insn "sse_stmxcsr"
   "%vstmxcsr\t%0"
   [(set_attr "isa" "noavx,avx")
    (set_attr "type" "sse")
-   (set_attr "gpr32" "0")
+   (set_attr "addr" "rex")
    (set_attr "atom_sse_attr" "mxcsr")
    (set_attr "prefix" "maybe_vex")
    (set_attr "memory" "store")])
@@ -21422,7 +21431,7 @@  (define_insn "avx2_ph<plusminus_mnemonic>wv16hi3"
   "TARGET_AVX2"
   "vph<plusminus_mnemonic>w\t{%2, %1, %0|%0, %1, %2}"
   [(set_attr "type" "sseiadd")
-   (set_attr "gpr32" "0")
+   (set_attr "addr" "rex")
    (set_attr "prefix_extra" "1")
    (set_attr "prefix" "vex")
    (set_attr "mode" "OI")])
@@ -21448,7 +21457,7 @@  (define_insn "ssse3_ph<plusminus_mnemonic>wv8hi3"
    vph<plusminus_mnemonic>w\t{%2, %1, %0|%0, %1, %2}"
   [(set_attr "isa" "noavx,avx")
    (set_attr "type" "sseiadd")
-   (set_attr "gpr32" "0")
+   (set_attr "addr" "rex")
    (set_attr "atom_unit" "complex")
    (set_attr "prefix_extra" "1")
    (set_attr "prefix" "orig,vex")
@@ -21512,7 +21521,7 @@  (define_insn "avx2_ph<plusminus_mnemonic>dv8si3"
   "TARGET_AVX2"
   "vph<plusminus_mnemonic>d\t{%2, %1, %0|%0, %1, %2}"
   [(set_attr "type" "sseiadd")
-   (set_attr "gpr32" "0")
+   (set_attr "addr" "rex")
    (set_attr "prefix_extra" "1")
    (set_attr "prefix" "vex")
    (set_attr "mode" "OI")])
@@ -21536,7 +21545,7 @@  (define_insn "ssse3_ph<plusminus_mnemonic>dv4si3"
    vph<plusminus_mnemonic>d\t{%2, %1, %0|%0, %1, %2}"
   [(set_attr "isa" "noavx,avx")
    (set_attr "type" "sseiadd")
-   (set_attr "gpr32" "0")
+   (set_attr "addr" "rex")
    (set_attr "atom_unit" "complex")
    (set_attr "prefix_data16" "1,*")
    (set_attr "prefix_extra" "1")
@@ -21576,7 +21585,7 @@  (define_insn_and_split "ssse3_ph<plusminus_mnemonic>dv2si3"
 }
   [(set_attr "mmx_isa" "native,sse_noavx,avx")
    (set_attr "type" "sseiadd")
-   (set_attr "gpr32" "0")
+   (set_attr "addr" "rex")
    (set_attr "atom_unit" "complex")
    (set_attr "prefix_extra" "1")
    (set (attr "prefix_rex") (symbol_ref "x86_extended_reg_mentioned_p (insn)"))
@@ -21721,7 +21730,7 @@  (define_insn "ssse3_pmaddubsw128"
    pmaddubsw\t{%2, %0|%0, %2}
    vpmaddubsw\t{%2, %1, %0|%0, %1, %2}"
   [(set_attr "isa" "noavx,avx")
-   (set_attr "gpr32" "0,1")
+   (set_attr "addr" "rex,*")
    (set_attr "type" "sseiadd")
    (set_attr "atom_unit" "simul")
    (set_attr "prefix_extra" "1")
@@ -21850,7 +21859,7 @@  (define_insn "*<ssse3_avx2>_pmulhrsw<mode>3<mask_name>"
    pmulhrsw\t{%2, %0|%0, %2}
    vpmulhrsw\t{%2, %1, %0<mask_operand4>|%0<mask_operand4>, %1, %2}"
   [(set_attr "isa" "noavx,avx")
-   (set_attr "gpr32" "0,1")
+   (set_attr "addr" "rex,*")
    (set_attr "type" "sseimul")
    (set_attr "prefix_extra" "1")
    (set_attr "prefix" "orig,maybe_evex")
@@ -21974,7 +21983,7 @@  (define_insn "<ssse3_avx2>_pshufb<mode>3<mask_name>"
    pshufb\t{%2, %0|%0, %2}
    vpshufb\t{%2, %1, %0<mask_operand3>|%0<mask_operand3>, %1, %2}"
   [(set_attr "isa" "noavx,avx")
-   (set_attr "gpr32" "0,1")
+   (set_attr "addr" "rex,*")
    (set_attr "type" "sselog1")
    (set_attr "prefix_extra" "1")
    (set_attr "prefix" "orig,maybe_evex")
@@ -22042,7 +22051,7 @@  (define_insn "<ssse3_avx2>_psign<mode>3"
    vpsign<ssemodesuffix>\t{%2, %1, %0|%0, %1, %2}"
   [(set_attr "isa" "noavx,avx")
    (set_attr "type" "sselog1")
-   (set_attr "gpr32" "0")
+   (set_attr "addr" "rex")
    (set_attr "prefix_extra" "1")
    (set_attr "prefix" "orig,vex")
    (set_attr "mode" "<sseinsnmode>")])
@@ -22108,7 +22117,7 @@  (define_insn "<ssse3_avx2>_palignr<mode>"
     }
 }
   [(set_attr "isa" "noavx,avx")
-   (set_attr "gpr32" "0,1")
+   (set_attr "addr" "rex,*")
    (set_attr "type" "sseishft")
    (set_attr "atom_unit" "sishuf")
    (set_attr "prefix_extra" "1")
@@ -22183,7 +22192,7 @@  (define_insn_and_split "ssse3_palignrdi"
 }
   [(set_attr "mmx_isa" "native,sse_noavx,avx")
    (set_attr "type" "sseishft")
-   (set_attr "gpr32" "0,0,1")
+   (set_attr "addr" "rex,rex,*")
    (set_attr "atom_unit" "sishuf")
    (set_attr "prefix_extra" "1")
    (set_attr "length_immediate" "1")
@@ -22206,7 +22215,7 @@  (define_insn "*abs<mode>2"
   "TARGET_SSSE3"
   "%vpabs<ssemodesuffix>\t{%1, %0|%0, %1}"
   [(set_attr "isa" "noavx,avx")
-   (set_attr "gpr32" "0,1")
+   (set_attr "addr" "rex,*")
    (set_attr "type" "sselog1")
    (set_attr "prefix_extra" "1")
    (set_attr "prefix" "maybe_vex")
@@ -22355,7 +22364,7 @@  (define_insn "<sse4_1>_blend<ssemodesuffix><avxsizesuffix>"
    vblend<ssemodesuffix>\t{%3, %2, %1, %0|%0, %1, %2, %3}"
   [(set_attr "isa" "noavx,noavx,avx")
    (set_attr "type" "ssemov")
-   (set_attr "gpr32" "0")
+   (set_attr "addr" "rex")
    (set_attr "length_immediate" "1")
    (set_attr "prefix_data16" "1,1,*")
    (set_attr "prefix_extra" "1")
@@ -22376,7 +22385,7 @@  (define_insn "<sse4_1>_blendv<ssemodesuffix><avxsizesuffix>"
    vblendv<ssemodesuffix>\t{%3, %2, %1, %0|%0, %1, %2, %3}"
   [(set_attr "isa" "noavx,noavx,avx")
    (set_attr "type" "ssemov")
-   (set_attr "gpr32" "0")
+   (set_attr "addr" "rex")
    (set_attr "length_immediate" "1")
    (set_attr "prefix_data16" "1,1,*")
    (set_attr "prefix_extra" "1")
@@ -22442,7 +22451,7 @@  (define_insn_and_split "*<sse4_1>_blendv<ssemodesuffix><avxsizesuffix>_lt"
   "operands[3] = gen_lowpart (<MODE>mode, operands[3]);"
   [(set_attr "isa" "noavx,noavx,avx")
    (set_attr "type" "ssemov")
-   (set_attr "gpr32" "0")
+   (set_attr "addr" "rex")
    (set_attr "length_immediate" "1")
    (set_attr "prefix_data16" "1,1,*")
    (set_attr "prefix_extra" "1")
@@ -22481,7 +22490,7 @@  (define_insn_and_split "*<sse4_1>_blendv<ssefltmodesuffix><avxsizesuffix>_ltint"
 }
   [(set_attr "isa" "noavx,noavx,avx")
    (set_attr "type" "ssemov")
-   (set_attr "gpr32" "0")
+   (set_attr "addr" "rex")
    (set_attr "length_immediate" "1")
    (set_attr "prefix_data16" "1,1,*")
    (set_attr "prefix_extra" "1")
@@ -22530,7 +22539,7 @@  (define_insn "<sse4_1>_dp<ssemodesuffix><avxsizesuffix>"
    vdp<ssemodesuffix>\t{%3, %2, %1, %0|%0, %1, %2, %3}"
   [(set_attr "isa" "noavx,noavx,avx")
    (set_attr "type" "ssemul")
-   (set_attr "gpr32" "0")
+   (set_attr "addr" "rex")
    (set_attr "length_immediate" "1")
    (set_attr "prefix_data16" "1,1,*")
    (set_attr "prefix_extra" "1")
@@ -22550,7 +22559,7 @@  (define_insn "<vi8_sse4_1_avx2_avx512>_movntdqa"
   "TARGET_SSE4_1"
   "%vmovntdqa\t{%1, %0|%0, %1}"
   [(set_attr "isa" "noavx,noavx,avx")
-   (set_attr "gpr32" "0,0,1")
+   (set_attr "addr" "rex,rex,*")
    (set_attr "type" "ssemov")
    (set_attr "prefix_extra" "1")
    (set_attr "prefix" "orig,orig,maybe_evex")
@@ -22569,9 +22578,8 @@  (define_insn "<sse4_1_avx2>_mpsadbw"
    mpsadbw\t{%3, %2, %0|%0, %2, %3}
    vmpsadbw\t{%3, %2, %1, %0|%0, %1, %2, %3}"
   [(set_attr "isa" "noavx,noavx,avx")
-   (set_attr "gpr32" "0,0,1")
+   (set_attr "addr" "rex")
    (set_attr "type" "sselog1")
-   (set_attr "gpr32" "0")
    (set_attr "length_immediate" "1")
    (set_attr "prefix_extra" "1")
    (set_attr "prefix" "orig,orig,vex")
@@ -22591,7 +22599,7 @@  (define_insn "<sse4_1_avx2>_packusdw<mask_name>"
    packusdw\t{%2, %0|%0, %2}
    vpackusdw\t{%2, %1, %0<mask_operand3>|%0<mask_operand3>, %1, %2}"
   [(set_attr "isa" "noavx,noavx,avx")
-   (set_attr "gpr32" "0,0,1")
+   (set_attr "addr" "rex,rex,*")
    (set_attr "type" "sselog")
    (set_attr "prefix_extra" "1")
    (set_attr "prefix" "orig,orig,<mask_prefix>")
@@ -22611,7 +22619,7 @@  (define_insn "<sse4_1_avx2>_pblendvb"
    vpblendvb\t{%3, %2, %1, %0|%0, %1, %2, %3}"
   [(set_attr "isa" "noavx,noavx,avx")
    (set_attr "type" "ssemov")
-   (set_attr "gpr32" "0")
+   (set_attr "addr" "rex")
    (set_attr "prefix_extra" "1")
    (set_attr "length_immediate" "*,*,1")
    (set_attr "prefix" "orig,orig,vex")
@@ -22664,7 +22672,7 @@  (define_insn_and_split "*<sse4_1_avx2>_pblendvb_lt"
   ""
   [(set_attr "isa" "noavx,noavx,avx")
    (set_attr "type" "ssemov")
-   (set_attr "gpr32" "0")
+   (set_attr "addr" "rex")
    (set_attr "prefix_extra" "1")
    (set_attr "length_immediate" "*,*,1")
    (set_attr "prefix" "orig,orig,vex")
@@ -22706,7 +22714,7 @@  (define_insn "sse4_1_pblend<ssemodesuffix>"
    vpblendw\t{%3, %2, %1, %0|%0, %1, %2, %3}"
   [(set_attr "isa" "noavx,noavx,avx")
    (set_attr "type" "ssemov")
-   (set_attr "gpr32" "0")
+   (set_attr "addr" "rex")
    (set_attr "prefix_extra" "1")
    (set_attr "length_immediate" "1")
    (set_attr "prefix" "orig,orig,vex")
@@ -22778,7 +22786,7 @@  (define_insn "*avx2_pblend<ssemodesuffix>"
   return "vpblendw\t{%3, %2, %1, %0|%0, %1, %2, %3}";
 }
   [(set_attr "type" "ssemov")
-   (set_attr "gpr32" "0")
+   (set_attr "addr" "rex")
    (set_attr "prefix_extra" "1")
    (set_attr "length_immediate" "1")
    (set_attr "prefix" "vex")
@@ -22805,7 +22813,7 @@  (define_insn "sse4_1_phminposuw"
   "TARGET_SSE4_1"
   "%vphminposuw\t{%1, %0|%0, %1}"
   [(set_attr "isa" "noavx,noavx,avx")
-   (set_attr "gpr32" "0")
+   (set_attr "addr" "rex")
    (set_attr "type" "sselog1")
    (set_attr "prefix_extra" "1")
    (set_attr "prefix" "orig,orig,vex")
@@ -22945,7 +22953,7 @@  (define_insn "*sse4_1_<code>v8qiv8hi2<mask_name>_1"
    pmov<extsuffix>bw\t{%1, %0|%0, %1}
    vpmov<extsuffix>bw\t{%1, %0<mask_operand2>|%0<mask_operand2>, %1}"
   [(set_attr "isa" "noavx,noavx,avx")
-   (set_attr "gpr32" "0,0,1")
+   (set_attr "addr" "rex,rex,*")
    (set_attr "type" "ssemov")
    (set_attr "prefix_extra" "1")
    (set_attr "prefix" "orig,orig,maybe_evex")
@@ -23001,7 +23009,7 @@  (define_insn_and_split "*sse4_1_zero_extendv8qiv8hi2_3"
     }
 }
   [(set_attr "isa" "noavx,noavx,avx")
-   (set_attr "gpr32" "0,0,1")])
+   (set_attr "addr" "rex,rex,*")])
 
 (define_insn_and_split "*sse4_1_zero_extendv8qiv8hi2_4"
   [(set (match_operand:V16QI 0 "register_operand" "=Yr,*x,Yw")
@@ -23037,7 +23045,7 @@  (define_insn_and_split "*sse4_1_zero_extendv8qiv8hi2_4"
   operands[1] = lowpart_subreg (V16QImode, operands[1], <ssehalfvecmode>mode);
 }
   [(set_attr "isa" "noavx,noavx,avx")
-   (set_attr "gpr32" "0,0,1")])
+   (set_attr "addr" "rex,rex,*")])
 
 (define_expand "<insn>v8qiv8hi2"
   [(set (match_operand:V8HI 0 "register_operand")
@@ -23160,7 +23168,7 @@  (define_insn "*sse4_1_<code>v4qiv4si2<mask_name>_1"
   "TARGET_SSE4_1 && <mask_avx512vl_condition>"
   "%vpmov<extsuffix>bd\t{%1, %0<mask_operand2>|%0<mask_operand2>, %1}"
   [(set_attr "isa" "noavx,noavx,avx")
-   (set_attr "gpr32" "0,0,1")
+   (set_attr "addr" "rex,rex,*")
    (set_attr "type" "ssemov")
    (set_attr "prefix_extra" "1")
    (set_attr "prefix" "orig,orig,maybe_evex")
@@ -23333,7 +23341,7 @@  (define_insn "*sse4_1_<code>v4hiv4si2<mask_name>_1"
   "TARGET_SSE4_1 && <mask_avx512vl_condition>"
   "%vpmov<extsuffix>wd\t{%1, %0<mask_operand2>|%0<mask_operand2>, %1}"
   [(set_attr "isa" "noavx,noavx,avx")
-   (set_attr "gpr32" "0,0,1")
+   (set_attr "addr" "rex,rex,*")
    (set_attr "type" "ssemov")
    (set_attr "prefix_extra" "1")
    (set_attr "prefix" "orig,orig,maybe_evex")
@@ -23406,7 +23414,7 @@  (define_insn_and_split "*sse4_1_zero_extendv4hiv4si2_3"
     }
 }
   [(set_attr "isa" "noavx,noavx,avx")
-   (set_attr "gpr32" "0,0,1")])
+   (set_attr "addr" "rex,rex,*")])
 
 (define_insn_and_split "*sse4_1_zero_extendv4hiv4si2_4"
   [(set (match_operand:V8HI 0 "register_operand" "=Yr,*x,v")
@@ -23440,7 +23448,7 @@  (define_insn_and_split "*sse4_1_zero_extendv4hiv4si2_4"
   operands[1] = lowpart_subreg (V8HImode, operands[1], <ssehalfvecmode>mode);
 }
   [(set_attr "isa" "noavx,noavx,avx")
-   (set_attr "gpr32" "0,0,1")])
+   (set_attr "addr" "rex,rex,*")])
 
 (define_insn "avx512f_<code>v8qiv8di2<mask_name>"
   [(set (match_operand:V8DI 0 "register_operand" "=v")
@@ -23584,7 +23592,7 @@  (define_insn "*sse4_1_<code>v2qiv2di2<mask_name>_1"
   "TARGET_SSE4_1 && <mask_avx512vl_condition>"
   "%vpmov<extsuffix>bq\t{%1, %0<mask_operand2>|%0<mask_operand2>, %1}"
   [(set_attr "isa" "noavx,avx")
-   (set_attr "gpr32" "0,1")
+   (set_attr "addr" "rex,*")
    (set_attr "type" "ssemov")
    (set_attr "prefix_extra" "1")
    (set_attr "prefix" "maybe_evex")
@@ -23723,7 +23731,7 @@  (define_insn "*sse4_1_<code>v2hiv2di2<mask_name>_1"
   "TARGET_SSE4_1 && <mask_avx512vl_condition>"
   "%vpmov<extsuffix>wq\t{%1, %0<mask_operand2>|%0<mask_operand2>, %1}"
   [(set_attr "isa" "noavx,noavx,avx")
-   (set_attr "gpr32" "0,0,1")
+   (set_attr "addr" "rex,rex,*")
    (set_attr "type" "ssemov")
    (set_attr "prefix_extra" "1")
    (set_attr "prefix" "orig,orig,maybe_evex")
@@ -23889,7 +23897,7 @@  (define_insn "*sse4_1_<code>v2siv2di2<mask_name>_1"
   "TARGET_SSE4_1 && <mask_avx512vl_condition>"
   "%vpmov<extsuffix>dq\t{%1, %0<mask_operand2>|%0<mask_operand2>, %1}"
   [(set_attr "isa" "noavx,noavx,avx")
-   (set_attr "gpr32" "0,0,1")
+   (set_attr "addr" "rex,rex,*")
    (set_attr "type" "ssemov")
    (set_attr "prefix_extra" "1")
    (set_attr "prefix" "orig,orig,maybe_evex")
@@ -23938,7 +23946,7 @@  (define_insn_and_split "*sse4_1_zero_extendv2siv2di2_3"
     }
 }
   [(set_attr "isa" "noavx,noavx,avx")
-   (set_attr "gpr32" "0,0,1")])
+   (set_attr "addr" "rex,rex,*")])
 
 (define_insn_and_split "*sse4_1_zero_extendv2siv2di2_4"
   [(set (match_operand:V4SI 0 "register_operand" "=Yr,*x,v")
@@ -23968,7 +23976,7 @@  (define_insn_and_split "*sse4_1_zero_extendv2siv2di2_4"
   operands[1] = lowpart_subreg (V4SImode, operands[1], V2SImode);
 }
   [(set_attr "isa" "noavx,noavx,avx")
-   (set_attr "gpr32" "0,0,1")])
+   (set_attr "addr" "rex,rex,*")])
 
 (define_expand "<insn>v2siv2di2"
   [(set (match_operand:V2DI 0 "register_operand")
@@ -24001,7 +24009,7 @@  (define_insn "avx_vtest<ssemodesuffix><avxsizesuffix>"
   "TARGET_AVX"
   "vtest<ssemodesuffix>\t{%1, %0|%0, %1}"
   [(set_attr "type" "ssecomi")
-   (set_attr "gpr32" "0")
+   (set_attr "addr" "rex")
    (set_attr "prefix_extra" "1")
    (set_attr "prefix" "vex")
    (set_attr "mode" "<MODE>")])
@@ -24017,7 +24025,7 @@  (define_insn "*<sse4_1>_ptest<mode>"
   "%vptest\t{%1, %0|%0, %1}"
   [(set_attr "isa" "noavx,noavx,avx")
    (set_attr "type" "ssecomi")
-   (set_attr "gpr32" "0")
+   (set_attr "addr" "rex")
    (set_attr "prefix_extra" "1")
    (set_attr "prefix" "orig,orig,vex")
    (set (attr "btver2_decode")
@@ -24060,7 +24068,7 @@  (define_insn "ptesttf2"
   "%vptest\t{%1, %0|%0, %1}"
   [(set_attr "isa" "noavx,noavx,avx")
    (set_attr "type" "ssecomi")
-   (set_attr "gpr32" "0")
+   (set_attr "addr" "rex")
    (set_attr "prefix_extra" "1")
    (set_attr "prefix" "orig,orig,vex")
    (set_attr "mode" "TI")])
@@ -24178,7 +24186,7 @@  (define_insn "<sse4_1>_round<ssemodesuffix><avxsizesuffix>"
   "%vround<ssemodesuffix>\t{%2, %1, %0|%0, %1, %2}"
   [(set_attr "isa" "noavx,noavx,avx")
    (set_attr "type" "ssecvt")
-   (set_attr "gpr32" "0")
+   (set_attr "addr" "rex")
    (set_attr "prefix_data16" "1,1,*")
    (set_attr "prefix_extra" "1")
    (set_attr "length_immediate" "1")
@@ -24290,7 +24298,7 @@  (define_insn "sse4_1_round<ssescalarmodesuffix>"
 }
   [(set_attr "isa" "noavx,noavx,noavx512f,avx512f")
    (set_attr "type" "ssecvt")
-   (set_attr "gpr32" "0,0,0,1")
+   (set_attr "addr" "rex,rex,rex,*")
    (set_attr "length_immediate" "1")
    (set_attr "prefix_data16" "1,1,*,*")
    (set_attr "prefix_extra" "1")
@@ -24327,7 +24335,7 @@  (define_insn "*sse4_1_round<ssescalarmodesuffix>"
 }
   [(set_attr "isa" "noavx,noavx,noavx512f,avx512f")
    (set_attr "type" "ssecvt")
-   (set_attr "gpr32" "0,0,0,1")
+   (set_attr "addr" "rex,rex,rex,*")
    (set_attr "length_immediate" "1")
    (set_attr "prefix_data16" "1,1,*,*")
    (set_attr "prefix_extra" "1")
@@ -24596,7 +24604,7 @@  (define_insn "sse4_2_pcmpestri"
   "TARGET_SSE4_2"
   "%vpcmpestri\t{%5, %3, %1|%1, %3, %5}"
   [(set_attr "type" "sselog")
-   (set_attr "gpr32" "0")
+   (set_attr "addr" "rex")
    (set_attr "prefix_extra" "1")
    (set_attr "prefix" "maybe_vex")
    (set_attr "length_immediate" "1")
@@ -24624,7 +24632,7 @@  (define_insn "sse4_2_pcmpestrm"
   "TARGET_SSE4_2"
   "%vpcmpestrm\t{%5, %3, %1|%1, %3, %5}"
   [(set_attr "type" "sselog")
-   (set_attr "gpr32" "0")
+   (set_attr "addr" "rex")
    (set_attr "prefix_extra" "1")
    (set_attr "length_immediate" "1")
    (set_attr "prefix" "maybe_vex")
@@ -24650,7 +24658,7 @@  (define_insn "sse4_2_pcmpestr_cconly"
    %vpcmpestri\t{%6, %4, %2|%2, %4, %6}
    %vpcmpestri\t{%6, %4, %2|%2, %4, %6}"
   [(set_attr "type" "sselog")
-   (set_attr "gpr32" "0")
+   (set_attr "addr" "rex")
    (set_attr "prefix_extra" "1")
    (set_attr "length_immediate" "1")
    (set_attr "memory" "none,load,none,load")
@@ -24705,7 +24713,7 @@  (define_insn_and_split "sse4_2_pcmpistr"
   DONE;
 }
   [(set_attr "type" "sselog")
-   (set_attr "gpr32" "0")
+   (set_attr "addr" "rex")
    (set_attr "prefix_extra" "1")
    (set_attr "length_immediate" "1")
    (set_attr "memory" "none,load")
@@ -24727,7 +24735,7 @@  (define_insn "sse4_2_pcmpistri"
   "TARGET_SSE4_2"
   "%vpcmpistri\t{%3, %2, %1|%1, %2, %3}"
   [(set_attr "type" "sselog")
-   (set_attr "gpr32" "0")
+   (set_attr "addr" "rex")
    (set_attr "prefix_extra" "1")
    (set_attr "length_immediate" "1")
    (set_attr "prefix" "maybe_vex")
@@ -24751,7 +24759,7 @@  (define_insn "sse4_2_pcmpistrm"
   "TARGET_SSE4_2"
   "%vpcmpistrm\t{%3, %2, %1|%1, %2, %3}"
   [(set_attr "type" "sselog")
-   (set_attr "gpr32" "0")
+   (set_attr "addr" "rex")
    (set_attr "prefix_extra" "1")
    (set_attr "length_immediate" "1")
    (set_attr "prefix" "maybe_vex")
@@ -24775,7 +24783,7 @@  (define_insn "sse4_2_pcmpistr_cconly"
    %vpcmpistri\t{%4, %3, %2|%2, %3, %4}
    %vpcmpistri\t{%4, %3, %2|%2, %3, %4}"
   [(set_attr "type" "sselog")
-   (set_attr "gpr32" "0")
+   (set_attr "addr" "rex")
    (set_attr "prefix_extra" "1")
    (set_attr "length_immediate" "1")
    (set_attr "memory" "none,load,none,load")
@@ -26202,7 +26210,7 @@  (define_insn "aesenc"
    vaesenc\t{%2, %1, %0|%0, %1, %2}"
   [(set_attr "isa" "noavx,aes,avx512vl")
    (set_attr "type" "sselog1")
-   (set_attr "gpr32" "0,1,1")
+   (set_attr "addr" "rex,*,*")
    (set_attr "prefix_extra" "1")
    (set_attr "prefix" "orig,vex,evex")
    (set_attr "btver2_decode" "double,double,double")
@@ -26220,7 +26228,7 @@  (define_insn "aesenclast"
    vaesenclast\t{%2, %1, %0|%0, %1, %2}"
   [(set_attr "isa" "noavx,aes,avx512vl")
    (set_attr "type" "sselog1")
-   (set_attr "gpr32" "0,1,1")
+   (set_attr "addr" "rex,*,*")
    (set_attr "prefix_extra" "1")
    (set_attr "prefix" "orig,vex,evex")
    (set_attr "btver2_decode" "double,double,double") 
@@ -26238,7 +26246,7 @@  (define_insn "aesdec"
    vaesdec\t{%2, %1, %0|%0, %1, %2}"
   [(set_attr "isa" "noavx,aes,avx512vl")
    (set_attr "type" "sselog1")
-   (set_attr "gpr32" "0,1,1")
+   (set_attr "addr" "rex,*,*")
    (set_attr "prefix_extra" "1")
    (set_attr "prefix" "orig,vex,evex")
    (set_attr "btver2_decode" "double,double,double") 
@@ -26255,7 +26263,7 @@  (define_insn "aesdeclast"
    vaesdeclast\t{%2, %1, %0|%0, %1, %2}
    vaesdeclast\t{%2, %1, %0|%0, %1, %2}"
   [(set_attr "isa" "noavx,aes,avx512vl")
-   (set_attr "gpr32" "0,1,1")
+   (set_attr "addr" "rex,*,*")
    (set_attr "type" "sselog1")
    (set_attr "prefix_extra" "1")
    (set_attr "prefix" "orig,vex,evex")
@@ -26269,7 +26277,7 @@  (define_insn "aesimc"
   "TARGET_AES"
   "%vaesimc\t{%1, %0|%0, %1}"
   [(set_attr "type" "sselog1")
-   (set_attr "gpr32" "0")
+   (set_attr "addr" "rex")
    (set_attr "prefix_extra" "1")
    (set_attr "prefix" "maybe_vex")
    (set_attr "mode" "TI")])
@@ -26282,7 +26290,7 @@  (define_insn "aeskeygenassist"
   "TARGET_AES"
   "%vaeskeygenassist\t{%2, %1, %0|%0, %1, %2}"
   [(set_attr "type" "sselog1")
-   (set_attr "gpr32" "0")
+   (set_attr "addr" "rex")
    (set_attr "prefix_extra" "1")
    (set_attr "length_immediate" "1")
    (set_attr "prefix" "maybe_vex")
@@ -26301,7 +26309,7 @@  (define_insn "pclmulqdq"
    vpclmulqdq\t{%3, %2, %1, %0|%0, %1, %2, %3}"
   [(set_attr "isa" "noavx,avx,vpclmulqdqvl")
    (set_attr "type" "sselog1")
-   (set_attr "gpr32" "0,1,1")
+   (set_attr "addr" "rex,*,*")
    (set_attr "prefix_extra" "1")
    (set_attr "length_immediate" "1")
    (set_attr "prefix" "orig,vex,evex")
@@ -26743,7 +26751,7 @@  (define_insn "avx512f_perm<mode>_1<mask_name>"
    (set_attr "mode" "<sseinsnmode>")])
 
 ;; TODO (APX): vmovaps supports EGPR but not others, could split
-;; pattern to enable gpr32 for this one.
+;; pattern to enable rex2 address for this one.
 (define_insn "avx2_permv2ti"
   [(set (match_operand:V4DI 0 "register_operand" "=x")
 	(unspec:V4DI
@@ -26775,7 +26783,7 @@  (define_insn "avx2_permv2ti"
     return "vperm2i128\t{%3, %2, %1, %0|%0, %1, %2, %3}";
   }
   [(set_attr "type" "sselog")
-   (set_attr "gpr32" "0")
+   (set_attr "addr" "rex")
    (set_attr "prefix" "vex")
    (set_attr "mode" "OI")])
 
@@ -27109,7 +27117,10 @@  (define_insn "avx_vbroadcastf128_<mode>"
    vinsert<shuffletype>32x4\t{$1, %1, %0, %0|%0, %0, %1, 1}"
   [(set_attr "isa" "noavx512vl,*,*,avx512dq,avx512dq,avx512vl,avx512vl")
    (set_attr "type" "ssemov,sselog1,sselog1,ssemov,sselog1,ssemov,sselog1")
-   (set_attr "gpr32" "0,1,1,1,1,1,1")
+   (set (attr "addr")
+	(if_then_else (eq_attr "alternative" "0")
+		      (const_string "rex")
+		      (const_string "*")))
    (set_attr "prefix_extra" "1")
    (set_attr "length_immediate" "0,1,1,0,1,0,1")
    (set_attr "prefix" "vex,vex,vex,evex,evex,evex,evex")
@@ -27404,7 +27415,7 @@  (define_insn "*avx_vperm2f128<mode>_full"
   "TARGET_AVX"
   "vperm2<i128>\t{%3, %2, %1, %0|%0, %1, %2, %3}"
   [(set_attr "type" "sselog")
-   (set_attr "gpr32" "0")
+   (set_attr "addr" "rex")
    (set_attr "prefix_extra" "1")
    (set_attr "length_immediate" "1")
    (set_attr "prefix" "vex")
@@ -27432,7 +27443,7 @@  (define_insn "*avx_vperm2f128<mode>_nozero"
   return "vperm2<i128>\t{%3, %2, %1, %0|%0, %1, %2, %3}";
 }
   [(set_attr "type" "sselog")
-   (set_attr "gpr32" "0")
+   (set_attr "addr" "rex")
    (set_attr "prefix_extra" "1")
    (set_attr "length_immediate" "1")
    (set_attr "prefix" "vex")
@@ -27537,7 +27548,7 @@  (define_insn "vec_set_lo_<mode><mask_name>"
     return "vinsert<i128>\t{$0x0, %2, %1, %0|%0, %1, %2, 0x0}";
 }
   [(set_attr "isa" "noavx512vl,avx512vl")
-   (set_attr "gpr32" "0,1")
+   (set_attr "addr" "rex,*")
    (set_attr "type" "sselog")
    (set_attr "prefix_extra" "1")
    (set_attr "length_immediate" "1")
@@ -27582,7 +27593,7 @@  (define_insn "vec_set_lo_<mode><mask_name>"
     return "vinsert<i128>\t{$0x0, %2, %1, %0|%0, %1, %2, 0x0}";
 }
   [(set_attr "isa" "noavx512vl,avx512vl")
-   (set_attr "gpr32" "0,1")
+   (set_attr "addr" "rex,*")
    (set_attr "type" "sselog")
    (set_attr "prefix_extra" "1")
    (set_attr "length_immediate" "1")
@@ -27605,7 +27616,7 @@  (define_insn "vec_set_hi_<mode><mask_name>"
     return "vinsert<i128>\t{$0x1, %2, %1, %0|%0, %1, %2, 0x1}";
 }
   [(set_attr "isa" "noavx512vl,avx512vl")
-   (set_attr "gpr32" "0,1")
+   (set_attr "addr" "rex,*")
    (set_attr "type" "sselog")
    (set_attr "prefix_extra" "1")
    (set_attr "length_immediate" "1")
@@ -27627,7 +27638,7 @@  (define_insn "vec_set_lo_<mode>"
    vinsert%~128\t{$0x0, %2, %1, %0|%0, %1, %2, 0x0}
    vinserti32x4\t{$0x0, %2, %1, %0|%0, %1, %2, 0x0}"
   [(set_attr "isa" "noavx512vl,avx512vl")
-   (set_attr "gpr32" "0,1")
+   (set_attr "addr" "rex,*")
    (set_attr "type" "sselog")
    (set_attr "prefix_extra" "1")
    (set_attr "length_immediate" "1")
@@ -27649,7 +27660,7 @@  (define_insn "vec_set_hi_<mode>"
    vinsert%~128\t{$0x1, %2, %1, %0|%0, %1, %2, 0x1}
    vinserti32x4\t{$0x1, %2, %1, %0|%0, %1, %2, 0x1}"
   [(set_attr "isa" "noavx512vl,avx512vl")
-   (set_attr "gpr32" "0,1")
+   (set_attr "addr" "rex,*")
    (set_attr "type" "sselog")
    (set_attr "prefix_extra" "1")
    (set_attr "length_immediate" "1")
@@ -27676,7 +27687,7 @@  (define_insn "vec_set_lo_v32qi"
    vinserti32x4\t{$0x0, %2, %1, %0|%0, %1, %2, 0x0}"
   [(set_attr "isa" "noavx512vl,avx512vl")
    (set_attr "type" "sselog")
-   (set_attr "gpr32" "0,1")
+   (set_attr "addr" "rex,*")
    (set_attr "prefix_extra" "1")
    (set_attr "length_immediate" "1")
    (set_attr "prefix" "vex,evex")
@@ -27701,7 +27712,7 @@  (define_insn "vec_set_hi_v32qi"
    vinsert%~128\t{$0x1, %2, %1, %0|%0, %1, %2, 0x1}
    vinserti32x4\t{$0x1, %2, %1, %0|%0, %1, %2, 0x1}"
   [(set_attr "isa" "noavx512vl,avx512vl")
-   (set_attr "gpr32" "0")
+   (set_attr "addr" "rex")
    (set_attr "type" "sselog")
    (set_attr "prefix_extra" "1")
    (set_attr "length_immediate" "1")
@@ -27722,7 +27733,7 @@  (define_insn "<avx_avx2>_maskload<ssemodesuffix><avxsizesuffix>"
     return "vmaskmov<ssefltmodesuffix>\t{%1, %2, %0|%0, %2, %1}";
 }
   [(set_attr "type" "sselog1")
-   (set_attr "gpr32" "0")
+   (set_attr "addr" "rex")
    (set_attr "prefix_extra" "1")
    (set_attr "prefix" "vex")
    (set_attr "btver2_decode" "vector")
@@ -27743,7 +27754,7 @@  (define_insn "<avx_avx2>_maskstore<ssemodesuffix><avxsizesuffix>"
     return "vmaskmov<ssefltmodesuffix>\t{%2, %1, %0|%0, %1, %2}";
 }
   [(set_attr "type" "sselog1")
-   (set_attr "gpr32" "0")
+   (set_attr "addr" "rex")
    (set_attr "prefix_extra" "1")
    (set_attr "prefix" "vex")
    (set_attr "btver2_decode" "vector") 
@@ -28102,7 +28113,7 @@  (define_insn "avx_vec_concat<mode>"
     }
 }
   [(set_attr "isa" "noavx512f,avx512f,*,*")
-   (set_attr "gpr32" "0,1,1,1")
+   (set_attr "addr" "rex,*,*,*")
    (set_attr "type" "sselog,sselog,ssemov,ssemov")
    (set_attr "prefix_extra" "1,1,*,*")
    (set_attr "length_immediate" "1,1,*,*")
@@ -28352,7 +28363,7 @@  (define_insn "*avx2_gathersi<VEC_GATHER_MODE:mode>"
   "TARGET_AVX2"
   "%M3v<sseintprefix>gatherd<ssemodesuffix>\t{%1, %7, %0|%0, %7, %1}"
   [(set_attr "type" "ssemov")
-   (set_attr "gpr32" "0")
+   (set_attr "addr" "rex")
    (set_attr "prefix" "vex")
    (set_attr "mode" "<sseinsnmode>")])
 
@@ -28373,7 +28384,7 @@  (define_insn "*avx2_gathersi<VEC_GATHER_MODE:mode>_2"
   "TARGET_AVX2"
   "%M2v<sseintprefix>gatherd<ssemodesuffix>\t{%1, %6, %0|%0, %6, %1}"
   [(set_attr "type" "ssemov")
-   (set_attr "gpr32" "0")
+   (set_attr "addr" "rex")
    (set_attr "prefix" "vex")
    (set_attr "mode" "<sseinsnmode>")])
 
@@ -28415,7 +28426,7 @@  (define_insn "*avx2_gatherdi<VEC_GATHER_MODE:mode>"
   "TARGET_AVX2"
   "%M3v<sseintprefix>gatherq<ssemodesuffix>\t{%5, %7, %2|%2, %7, %5}"
   [(set_attr "type" "ssemov")
-   (set_attr "gpr32" "0")
+   (set_attr "addr" "rex")
    (set_attr "prefix" "vex")
    (set_attr "mode" "<sseinsnmode>")])
 
@@ -28440,7 +28451,7 @@  (define_insn "*avx2_gatherdi<VEC_GATHER_MODE:mode>_2"
   return "%M2v<sseintprefix>gatherq<ssemodesuffix>\t{%4, %6, %0|%0, %6, %4}";
 }
   [(set_attr "type" "ssemov")
-   (set_attr "gpr32" "0")
+   (set_attr "addr" "rex")
    (set_attr "prefix" "vex")
    (set_attr "mode" "<sseinsnmode>")])
 
@@ -28464,7 +28475,7 @@  (define_insn "*avx2_gatherdi<VI4F_256:mode>_3"
   "TARGET_AVX2"
   "%M3v<sseintprefix>gatherq<ssemodesuffix>\t{%5, %7, %0|%0, %7, %5}"
   [(set_attr "type" "ssemov")
-   (set_attr "gpr32" "0")
+   (set_attr "addr" "rex")
    (set_attr "prefix" "vex")
    (set_attr "mode" "<sseinsnmode>")])
 
@@ -28488,7 +28499,7 @@  (define_insn "*avx2_gatherdi<VI4F_256:mode>_4"
   "TARGET_AVX2"
   "%M2v<sseintprefix>gatherq<ssemodesuffix>\t{%4, %6, %0|%0, %6, %4}"
   [(set_attr "type" "ssemov")
-   (set_attr "gpr32" "0")
+   (set_attr "addr" "rex")
    (set_attr "prefix" "vex")
    (set_attr "mode" "<sseinsnmode>")])
 
@@ -29688,7 +29699,7 @@  (define_insn "vgf2p8affineinvqb_<mode><mask_name>"
    gf2p8affineinvqb\t{%3, %2, %0| %0, %2, %3}
    vgf2p8affineinvqb\t{%3, %2, %1, %0<mask_operand4>| %0<mask_operand4>, %1, %2, %3}"
   [(set_attr "isa" "noavx,avx")
-   (set_attr "gpr32" "0,1")
+   (set_attr "addr" "rex,*")
    (set_attr "prefix_extra" "1")
    (set_attr "prefix" "orig,maybe_evex")
    (set_attr "mode" "<sseinsnmode>")])
@@ -29705,7 +29716,7 @@  (define_insn "vgf2p8affineqb_<mode><mask_name>"
    gf2p8affineqb\t{%3, %2, %0| %0, %2, %3}
    vgf2p8affineqb\t{%3, %2, %1, %0<mask_operand4>| %0<mask_operand4>, %1, %2, %3}"
   [(set_attr "isa" "noavx,avx")
-   (set_attr "gpr32" "0,1")
+   (set_attr "addr" "rex,*")
    (set_attr "prefix_extra" "1")
    (set_attr "prefix" "orig,maybe_evex")
    (set_attr "mode" "<sseinsnmode>")])
@@ -29721,7 +29732,7 @@  (define_insn "vgf2p8mulb_<mode><mask_name>"
    gf2p8mulb\t{%2, %0| %0, %2}
    vgf2p8mulb\t{%2, %1, %0<mask_operand3>| %0<mask_operand3>, %1, %2}"
   [(set_attr "isa" "noavx,avx")
-   (set_attr "gpr32" "0,1")
+   (set_attr "addr" "rex,*")
    (set_attr "prefix_extra" "1")
    (set_attr "prefix" "orig,maybe_evex")
    (set_attr "mode" "<sseinsnmode>")])