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[8.43.85.97]) by mx.google.com with ESMTPS id f2-20020a05640214c200b004acbf5579casi16892853edx.472.2023.02.20.14.22.33 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 20 Feb 2023 14:22:33 -0800 (PST) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) client-ip=8.43.85.97; Authentication-Results: mx.google.com; dkim=pass header.i=@gcc.gnu.org header.s=default header.b=F7lKCnDx; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=gnu.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 3C5DD3858C27 for ; Mon, 20 Feb 2023 22:22:29 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 3C5DD3858C27 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1676931749; bh=PANLRGfhkUX6znNnLAOfJP6tgNvAJJ4q8bM8259ZyAg=; h=Date:Subject:To:List-Id:List-Unsubscribe:List-Archive:List-Post: List-Help:List-Subscribe:From:Reply-To:From; b=F7lKCnDxoS+6zF64MbEHxcjePYiuZMo7O9LtYIHXr/KNrB5uy9qDEc2ELrSjYhn3N iYGbeFTMUGGmx87LhuxWsTR7sHI1JyD2/UKVnwEgLO/QdoN3w8pENAyn58+ed/Kx8a auRTgoC7Ou4kdTyseBhzM4ZQ4umieQRfIqtfw0w8= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mail-yb1-xb2a.google.com (mail-yb1-xb2a.google.com [IPv6:2607:f8b0:4864:20::b2a]) by sourceware.org (Postfix) with ESMTPS id 4C5B43858D1E for ; Mon, 20 Feb 2023 22:21:41 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 4C5B43858D1E Received: by mail-yb1-xb2a.google.com with SMTP id a20so1154895ybj.8 for ; Mon, 20 Feb 2023 14:21:41 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=to:subject:message-id:date:from:mime-version:x-gm-message-state :from:to:cc:subject:date:message-id:reply-to; bh=PANLRGfhkUX6znNnLAOfJP6tgNvAJJ4q8bM8259ZyAg=; b=bJHCRkc7TJtwx9TxX8NRZqKSBfRF6VTyLD5sByQU3FtTK9H4CYEGu9GBkN9GF4zgOG RvOMblRy6bGmLMDdrKwGwP59KX5IEmnBR1t6zAZt5bWpbsrZ+3BQjHjE+ofaFBd2X8hz VVoV4hkp2I9SkVuRHBVrBmz+voRVafmyRoz1VAiCUz+l9wl3midTvuP1NHQKoeXYEKQV neSz3M0GXrVqs4vUTo0iajPKqMnd7ZOqXaSP0EyVzQD6pQxLq2atEj0PM2tkgGNzEC+F 8v/V8VX66qr/2VS+hREdJCx4rv8kUYxWPYtoQf6i0imjUCtUrAppTfqzZ80jwbb5iq9n ROFA== X-Gm-Message-State: AO0yUKXNHmsamV4S+lkpd1nZGrbuxhxEEMfWEkSCv5qs0DEJ6IVSFeg2 ASf2/TDzafKflmm142nlCnb/MGD/pbqHf3W546dD2x6DWZr0xQ== X-Received: by 2002:a5b:58d:0:b0:80b:9566:d574 with SMTP id l13-20020a5b058d000000b0080b9566d574mr10117ybp.83.1676931700318; Mon, 20 Feb 2023 14:21:40 -0800 (PST) MIME-Version: 1.0 Date: Mon, 20 Feb 2023 23:21:29 +0100 Message-ID: Subject: [PATCH] i386: Introduce general_x64constmem_operand predicate To: "gcc-patches@gcc.gnu.org" X-Spam-Status: No, score=-7.4 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, FREEMAIL_FROM, GIT_PATCH_0, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Uros Bizjak via Gcc-patches From: Uros Bizjak Reply-To: Uros Bizjak Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1758390390768857931?= X-GMAIL-MSGID: =?utf-8?q?1758390390768857931?= Instructions that use high-part QImode registers can not be encoded with REX prefix. To avoid REX prefix, operand constraints allow only legacy QImode registers, immediates and constant memory operands. The patch introduces matching predicate, so invalid operands are not combined into instruction RTX only to be later fixed up by reload pass. 2023-02-20 Uroš Bizjak gcc/ChangeLog: * config/i386/predicates.md (general_x64constmem_operand): New predicate. * config/i386/i386.md (*cmpqi_ext_1): Use nonimm_x64constmem_operand. (*cmpqi_ext_3): Use general_x64constmem_operand. (*addqi_ext_1): Ditto. (*testqi_ext_1): Ditto. (*andqi_ext_1): Ditto. (*andqi_ext_1_cc): Ditto. (*qi_ext_1): Ditto. (*xorqi_ext_1_cc): Ditto. Bootstrapped and regression tested on x86_64-linux-gnu {,-m32}. Pushed to master. Uros. diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md index 6382cfbce21..8ebb12be2c9 100644 --- a/gcc/config/i386/i386.md +++ b/gcc/config/i386/i386.md @@ -1456,7 +1456,7 @@ (define_insn "*cmp_minus_1" (define_insn "*cmpqi_ext_1" [(set (reg FLAGS_REG) (compare - (match_operand:QI 0 "nonimmediate_operand" "QBc,m") + (match_operand:QI 0 "nonimm_x64constmem_operand" "QBc,m") (subreg:QI (zero_extract:SWI248 (match_operand 1 "int248_register_operand" "Q,Q") @@ -1501,7 +1501,7 @@ (define_insn "*cmpqi_ext_3" (match_operand 0 "int248_register_operand" "Q,Q") (const_int 8) (const_int 8)) 0) - (match_operand:QI 1 "general_operand" "QnBc,m")))] + (match_operand:QI 1 "general_x64constmem_operand" "QnBc,m")))] "ix86_match_ccmode (insn, CCmode)" "cmp{b}\t{%1, %h0|%h0, %1}" [(set_attr "isa" "*,nox64") @@ -6683,7 +6683,7 @@ (define_insn "*addqi_ext_1" (match_operand 1 "int248_register_operand" "0,0") (const_int 8) (const_int 8)) 0) - (match_operand:QI 2 "general_operand" "QnBc,m")) 0)) + (match_operand:QI 2 "general_x64constmem_operand" "QnBc,m")) 0)) (clobber (reg:CC FLAGS_REG))] "/* FIXME: without this LRA can't reload this pattern, see PR82524. */ rtx_equal_p (operands[0], operands[1])" @@ -9901,7 +9901,7 @@ (define_insn "*testqi_ext_1" (match_operand 0 "int248_register_operand" "Q,Q") (const_int 8) (const_int 8)) 0) - (match_operand:QI 1 "general_operand" "QnBc,m")) + (match_operand:QI 1 "general_x64constmem_operand" "QnBc,m")) (const_int 0)))] "ix86_match_ccmode (insn, CCNOmode)" "test{b}\t{%1, %h0|%h0, %1}" @@ -10602,7 +10602,7 @@ (define_insn "*andqi_ext_1" (match_operand 1 "int248_register_operand" "0,0") (const_int 8) (const_int 8)) 0) - (match_operand:QI 2 "general_operand" "QnBc,m")) 0)) + (match_operand:QI 2 "general_x64constmem_operand" "QnBc,m")) 0)) (clobber (reg:CC FLAGS_REG))] "/* FIXME: without this LRA can't reload this pattern, see PR82524. */ rtx_equal_p (operands[0], operands[1])" @@ -10622,7 +10622,7 @@ (define_insn "*andqi_ext_1_cc" (match_operand 1 "int248_register_operand" "0,0") (const_int 8) (const_int 8)) 0) - (match_operand:QI 2 "general_operand" "QnBc,m")) + (match_operand:QI 2 "general_x64constmem_operand" "QnBc,m")) (const_int 0))) (set (zero_extract:SWI248 (match_operand 0 "int248_register_operand" "+Q,Q") @@ -11345,7 +11345,7 @@ (define_insn "*qi_ext_1" (match_operand 1 "int248_register_operand" "0,0") (const_int 8) (const_int 8)) 0) - (match_operand:QI 2 "general_operand" "QnBc,m")) 0)) + (match_operand:QI 2 "general_x64constmem_operand" "QnBc,m")) 0)) (clobber (reg:CC FLAGS_REG))] "(!TARGET_PARTIAL_REG_STALL || optimize_function_for_size_p (cfun)) /* FIXME: without this LRA can't reload this pattern, see PR82524. */ @@ -11473,7 +11473,7 @@ (define_insn "*xorqi_ext_1_cc" (match_operand 1 "int248_register_operand" "0,0") (const_int 8) (const_int 8)) 0) - (match_operand:QI 2 "general_operand" "QnBc,m")) + (match_operand:QI 2 "general_x64constmem_operand" "QnBc,m")) (const_int 0))) (set (zero_extract:SWI248 (match_operand 0 "int248_register_operand" "+Q,Q") diff --git a/gcc/config/i386/predicates.md b/gcc/config/i386/predicates.md index 7b3db0cc851..b4d9ab40ab9 100644 --- a/gcc/config/i386/predicates.md +++ b/gcc/config/i386/predicates.md @@ -116,6 +116,13 @@ (define_predicate "nonimm_x64constmem_operand" (ior (not (match_test "TARGET_64BIT")) (match_test "constant_address_p (XEXP (op, 0))"))))) +;; Match general operand, but exclude non-constant addresses for x86_64. +(define_predicate "general_x64constmem_operand" + (ior (match_operand 0 "nonmemory_operand") + (and (match_operand 0 "memory_operand") + (ior (not (match_test "TARGET_64BIT")) + (match_test "constant_address_p (XEXP (op, 0))"))))) + ;; Match register operands, but include memory operands for TARGET_SSE_MATH. (define_predicate "register_ssemem_operand" (if_then_else