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[2620:52:3:1:0:246e:9693:128c]) by mx.google.com with ESMTPS id ja18-20020a170907989200b0096a687d6631si3041137ejc.485.2023.05.24.07.21.16 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 24 May 2023 07:21:16 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) client-ip=2620:52:3:1:0:246e:9693:128c; Authentication-Results: mx.google.com; dkim=pass header.i=@gcc.gnu.org header.s=default header.b=n2YxktDC; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=gnu.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 218013858004 for ; Wed, 24 May 2023 14:21:15 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 218013858004 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1684938075; bh=tq8yWhVoUEKq1+JN9db6Csfd5CZProaA6NbbMKoiezA=; h=Date:Subject:To:List-Id:List-Unsubscribe:List-Archive:List-Post: List-Help:List-Subscribe:From:Reply-To:From; b=n2YxktDCzeph3/rgCRI2T2fYiJVe0SDZn/7fquGixbD/is0Gtzvg9+vvIegAha/C4 USerJ/DsGPe/XTXQjgo17UEsAPyHayhTx2Tjdcux74OCMnKRWiXhgWbtrK+4YCEILc Gh7yBO5h7aaHmmQFZjdkyzml3ztTezncoWnD1joc= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mail-qt1-x82e.google.com (mail-qt1-x82e.google.com [IPv6:2607:f8b0:4864:20::82e]) by sourceware.org (Postfix) with ESMTPS id E97BE3858D28 for ; Wed, 24 May 2023 14:20:26 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org E97BE3858D28 Received: by mail-qt1-x82e.google.com with SMTP id d75a77b69052e-3f6b34d2fdcso6490221cf.1 for ; Wed, 24 May 2023 07:20:26 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1684938026; x=1687530026; h=to:subject:message-id:date:from:mime-version:x-gm-message-state :from:to:cc:subject:date:message-id:reply-to; bh=tq8yWhVoUEKq1+JN9db6Csfd5CZProaA6NbbMKoiezA=; b=fuu7s+Kswr81YKi17/f8J2xN6EDJS9t0eBGMA0Zszu2A7aC9EmBmGSoMGy6KUY+diJ irc+wd2nQyC59skWfu38RBfGg1rnwDd86swN4dVg2eH2SJazGwu39wM4igTMroADXmiO Bmgef3FS5yPODcMsl/+yqGZdJTSh2HOUjBx7YXVBnypdujwv7SI6AoPd9mzwzA3wxOSE XAWVOnG4Bfwx2jZSPvU+YMBQxPzknE38QVOhgXQr4ewR0tTSfr1AKo3f5FrW7TvkSzbC YXEX/Bq/oBlWiNF1ewOYYIZQcIxWTzbr1Yzuc4r0BO6a1I+r8NKwu/i3uQeAAMsSeLJX O9jg== X-Gm-Message-State: AC+VfDwR1w32ssZEXb+KywxW5lqdI4tRlD+SYknbPEgB9/Lz/dOUii9m CNx8Btv1z1cELx+qOfvhZ2yGcn/kP6ZxyohhFenWkuQxoaAL6A== X-Received: by 2002:ad4:5947:0:b0:625:1c04:6761 with SMTP id eo7-20020ad45947000000b006251c046761mr19041397qvb.27.1684938025833; Wed, 24 May 2023 07:20:25 -0700 (PDT) MIME-Version: 1.0 Date: Wed, 24 May 2023 16:20:14 +0200 Message-ID: Subject: [COMMITTED] i386: Add vv4qi3 expander To: "gcc-patches@gcc.gnu.org" X-Spam-Status: No, score=-8.3 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, FREEMAIL_FROM, GIT_PATCH_0, KAM_SHORT, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Uros Bizjak via Gcc-patches From: Uros Bizjak Reply-To: Uros Bizjak Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1766785628599568410?= X-GMAIL-MSGID: =?utf-8?q?1766785628599568410?= Also, move vv8qi3 expander to a better place and enable it with TARGET_MMX_WITH_SSE. Remove handling of V8QImode from ix86_expand_vecop_qihi2 since all partial QI->HI vector modes expand via ix86_expand_vecop_qihi_partial. gcc/ChangeLog: * config/i386/i386-expand.cc (ix86_expand_vecop_qihi2): Remove handling of V8QImode. * config/i386/mmx.md (vv8qi3): Move from sse.md. Call ix86_expand_vecop_qihi_partial. Enable for TARGET_MMX_WITH_SSE. (vv4qi3): Ditto. * config/i386/sse.md (vv8qi3): Remove. gcc/testsuite/ChangeLog: * gcc.target/i386/vect-shiftv4qi.c (dg-options): Remove -ftree-vectorize. * gcc.target/i386/vect-shiftv8qi.c (dg-options): Ditto. * gcc.target/i386/vect-vshiftv4qi.c: New test. * gcc.target/i386/vect-vshiftv8qi.c: New test. Bootstrapped and regression tested on x86_64-linux-gnu {,-m32}. Uros. diff --git a/gcc/config/i386/i386-expand.cc b/gcc/config/i386/i386-expand.cc index ff3d382f1b4..2e6e6585aeb 100644 --- a/gcc/config/i386/i386-expand.cc +++ b/gcc/config/i386/i386-expand.cc @@ -23132,9 +23132,10 @@ ix86_expand_vecop_qihi2 (enum rtx_code code, rtx dest, rtx op1, rtx op2) /* vpmovwb only available under AVX512BW. */ if (!TARGET_AVX512BW) return false; - if ((qimode == V8QImode || qimode == V16QImode) - && !TARGET_AVX512VL) + + if (qimode == V16QImode && !TARGET_AVX512VL) return false; + /* Do not generate ymm/zmm instructions when target prefers 128/256 bit vector width. */ if ((qimode == V16QImode && TARGET_PREFER_AVX128) @@ -23143,10 +23144,6 @@ ix86_expand_vecop_qihi2 (enum rtx_code code, rtx dest, rtx op1, rtx op2) switch (qimode) { - case E_V8QImode: - himode = V8HImode; - gen_truncate = gen_truncv8hiv8qi2; - break; case E_V16QImode: himode = V16HImode; gen_truncate = gen_truncv16hiv16qi2; diff --git a/gcc/config/i386/mmx.md b/gcc/config/i386/mmx.md index a37bbbb811f..dbcb850ffde 100644 --- a/gcc/config/i386/mmx.md +++ b/gcc/config/i386/mmx.md @@ -2734,6 +2734,30 @@ (define_insn_and_split "v2qi3" [(set_attr "type" "multi") (set_attr "mode" "QI")]) +(define_expand "vv8qi3" + [(set (match_operand:V8QI 0 "register_operand") + (any_shift:V8QI + (match_operand:V8QI 1 "register_operand") + (match_operand:V8QI 2 "register_operand")))] + "TARGET_AVX512BW && TARGET_AVX512VL && TARGET_MMX_WITH_SSE" +{ + ix86_expand_vecop_qihi_partial (, operands[0], + operands[1], operands[2]); + DONE; +}) + +(define_expand "vv4qi3" + [(set (match_operand:V4QI 0 "register_operand") + (any_shift:V4QI + (match_operand:V4QI 1 "register_operand") + (match_operand:V4QI 2 "register_operand")))] + "TARGET_AVX512BW && TARGET_AVX512VL" +{ + ix86_expand_vecop_qihi_partial (, operands[0], + operands[1], operands[2]); + DONE; +}) + ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;; ;; Parallel integral comparisons diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md index 26dd0b1aa10..0656a5ce717 100644 --- a/gcc/config/i386/sse.md +++ b/gcc/config/i386/sse.md @@ -24564,17 +24564,6 @@ (define_expand "v3" } }) -(define_expand "vv8qi3" - [(set (match_operand:V8QI 0 "register_operand") - (any_shift:V8QI - (match_operand:V8QI 1 "register_operand") - (match_operand:V8QI 2 "nonimmediate_operand")))] - "TARGET_AVX512BW && TARGET_AVX512VL && TARGET_64BIT" -{ - ix86_expand_vecop_qihi (, operands[0], operands[1], operands[2]); - DONE; -}) - (define_expand "vlshr3" [(set (match_operand:VI48_512 0 "register_operand") (lshiftrt:VI48_512 diff --git a/gcc/testsuite/gcc.target/i386/vect-shiftv4qi.c b/gcc/testsuite/gcc.target/i386/vect-shiftv4qi.c index c06dfb87bd1..c6a63903604 100644 --- a/gcc/testsuite/gcc.target/i386/vect-shiftv4qi.c +++ b/gcc/testsuite/gcc.target/i386/vect-shiftv4qi.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-O2 -ftree-vectorize -msse2" } */ +/* { dg-options "-O2 -msse2" } */ #define N 4 diff --git a/gcc/testsuite/gcc.target/i386/vect-shiftv8qi.c b/gcc/testsuite/gcc.target/i386/vect-shiftv8qi.c index f5e8925aa25..244b0dbd28a 100644 --- a/gcc/testsuite/gcc.target/i386/vect-shiftv8qi.c +++ b/gcc/testsuite/gcc.target/i386/vect-shiftv8qi.c @@ -1,5 +1,5 @@ /* { dg-do compile { target { ! ia32 } } } */ -/* { dg-options "-O2 -ftree-vectorize -msse2" } */ +/* { dg-options "-O2 -msse2" } */ #define N 8 diff --git a/gcc/testsuite/gcc.target/i386/vect-vshiftv4qi.c b/gcc/testsuite/gcc.target/i386/vect-vshiftv4qi.c new file mode 100644 index 00000000000..c74cc991f59 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/vect-vshiftv4qi.c @@ -0,0 +1,28 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -mavx512bw -mavx512vl" } */ + +#define N 4 + +typedef unsigned char __vu __attribute__ ((__vector_size__ (N))); +typedef signed char __vi __attribute__ ((__vector_size__ (N))); + +__vu sllv (__vu a, __vu b) +{ + return a << b; +} + +/* { dg-final { scan-assembler-times "vpsllvw" 1 } } */ + +__vu srlv (__vu a, __vu b) +{ + return a >> b; +} + +/* { dg-final { scan-assembler-times "vpsrlvw" 1 } } */ + +__vi srav (__vi a, __vi b) +{ + return a >> b; +} + +/* { dg-final { scan-assembler-times "vpsravw" 1 } } */ diff --git a/gcc/testsuite/gcc.target/i386/vect-vshiftv8qi.c b/gcc/testsuite/gcc.target/i386/vect-vshiftv8qi.c new file mode 100644 index 00000000000..1d838af07f7 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/vect-vshiftv8qi.c @@ -0,0 +1,28 @@ +/* { dg-do compile { target { ! ia32 } } } */ +/* { dg-options "-O2 -mavx512bw -mavx512vl" } */ + +#define N 8 + +typedef unsigned char __vu __attribute__ ((__vector_size__ (N))); +typedef signed char __vi __attribute__ ((__vector_size__ (N))); + +__vu vsll (__vu a, __vu b) +{ + return a << b; +} + +/* { dg-final { scan-assembler-times "vpsllvw" 1 } } */ + +__vu vsrl (__vu a, __vu b) +{ + return a >> b; +} + +/* { dg-final { scan-assembler-times "vpsrlvw" 1 } } */ + +__vi vsra (__vi a, __vi b) +{ + return a >> b; +} + +/* { dg-final { scan-assembler-times "vpsravw" 1 } } */