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[2620:52:3:1:0:246e:9693:128c]) by mx.google.com with ESMTPS id o15-20020a170906974f00b00710e9e0a239si3976751ejy.919.2022.08.05.04.33.44 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 05 Aug 2022 04:33:45 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) client-ip=2620:52:3:1:0:246e:9693:128c; Authentication-Results: mx.google.com; dkim=pass header.i=@gcc.gnu.org header.s=default header.b="AVA/POjd"; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=gnu.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id CBC1C3857355 for ; Fri, 5 Aug 2022 11:33:43 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org CBC1C3857355 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1659699223; bh=E9lA5lN2kPUsl9wVH47l+YvpUhxiFdKyCAjuQSOMhk0=; h=Date:Subject:To:List-Id:List-Unsubscribe:List-Archive:List-Post: List-Help:List-Subscribe:From:Reply-To:From; b=AVA/POjdW9Qak4SbuOThvK0B2L5YCBZh3gGA2erb8tw0ayE6dcP6ejZbaLoOqlGqR RHGh/rkzKtEF8KqX2JzSK0Qhzv7lzPIR1tYoWPsX3hEqajeKfRbz036+KXW1knbfN5 +9xRHRwPjxoNLd3Q/MY4DrLxhXSYhum2mamiXQxo= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mail-ed1-x532.google.com (mail-ed1-x532.google.com [IPv6:2a00:1450:4864:20::532]) by sourceware.org (Postfix) with ESMTPS id C495B3858C53 for ; Fri, 5 Aug 2022 11:32:59 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org C495B3858C53 Received: by mail-ed1-x532.google.com with SMTP id e13so2962906edj.12 for ; Fri, 05 Aug 2022 04:32:59 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:mime-version:from:date:message-id:subject:to; bh=E9lA5lN2kPUsl9wVH47l+YvpUhxiFdKyCAjuQSOMhk0=; b=OZZVhB4cQGE4Sjw++2iB3hswTO2ZvO6JMmUc+sbEjzVYJPUr0CvO3qpmmfw8kkQTh7 tODvLZqyYsI/H1sS9EgDm3K+cEjk9bR8K4ggpyKKnWuSOnSFLWVDcoW5DZxxA7uiZJ4Y GW3oiFZFeVlDVeEsl8PghZkgRM3E7rMX5rrR3tdvxGmcHkg/UB/PpXZjwpdlsxJ2oRTr aF6+x5gmM1tR4j7cdJtZDeOESBpzG/MeGq8+M/p3QknKFBNxmb/uzOGkSEUlOQ8ocfjM kgIZPcfMhy8ovQfxiABKt/w04V6pOkaCusCXrgor89BILo0e8D2FtO1RIVLIUf/M7AtT K4JQ== X-Gm-Message-State: ACgBeo1W/GMv4VMjhgwsWBrpS4wK5F4pcfIm6fJrR2GhB4cEu8Pcinc6 AqfLYu+iD5uPiqqYPlqEW/SdZsPI1Xf8YPAXOeWVkg== X-Received: by 2002:a05:6402:40ce:b0:43d:f8a0:9c4f with SMTP id z14-20020a05640240ce00b0043df8a09c4fmr6301580edb.95.1659699178524; Fri, 05 Aug 2022 04:32:58 -0700 (PDT) MIME-Version: 1.0 Date: Fri, 5 Aug 2022 17:02:22 +0530 Message-ID: Subject: Missed lowering to ld1rq from svld1rq for memory operand To: Richard Sandiford , gcc Patches X-Spam-Status: No, score=-9.3 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, KAM_SHORT, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Prathamesh Kulkarni via Gcc-patches From: Prathamesh Kulkarni Reply-To: Prathamesh Kulkarni Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1740320774992827505?= X-GMAIL-MSGID: =?utf-8?q?1740320774992827505?= Hi Richard, Following from off-list discussion, in the attached patch, I wrote pattern similar to vec_duplicate_reg, which seems to work for the svld1rq tests. Does it look OK ? Sorry, I didn't fully understand your suggestion on integrating with vec_duplicate_reg pattern. For vec_duplicate_reg, the operand to vec_duplicate expects mode to be , while the pattern in patch expects operand of vec_duplicate to have mode . How do we write a pattern so an operand can accept either of the 2 modes ? Also it seems cannot be used with SVE_ALL ? Thanks, Prathamesh diff --git a/gcc/config/aarch64/aarch64-sve.md b/gcc/config/aarch64/aarch64-sve.md index bd60e65b0c3..b0dc33870b8 100644 --- a/gcc/config/aarch64/aarch64-sve.md +++ b/gcc/config/aarch64/aarch64-sve.md @@ -2504,6 +2504,27 @@ } ) +;; Fold ldr+dup -> ld1rq + +(define_insn_and_split "*vec_duplicate_ld1rq" + [(set (match_operand:SVE_FULL 0 "register_operand" "=w") + (vec_duplicate:SVE_FULL + (match_operand: 1 "aarch64_sve_ld1rq_operand" "UtQ"))) + (clobber (match_scratch:VNx16BI 2 "=Upl"))] + "TARGET_SVE" + "#" + "&& 1" + [(const_int 0)] + { + if (GET_CODE (operands[2]) == SCRATCH) + operands[2] = gen_reg_rtx (VNx16BImode); + emit_move_insn (operands[2], CONSTM1_RTX (VNx16BImode)); + rtx gp = gen_lowpart (mode, operands[2]); + emit_insn (gen_aarch64_sve_ld1rq (operands[0], operands[1], gp)); + DONE; + } +) + ;; Accept memory operands for the benefit of combine, and also in case ;; the scalar input gets spilled to memory during RA. We want to split ;; the load at the first opportunity in order to allow the PTRUE to be diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/general/pr96463-2.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/pr96463-2.c index 196de3f5e0a..0dfe125507f 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/general/pr96463-2.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/pr96463-2.c @@ -26,4 +26,8 @@ TEST(svfloat64_t, float64_t, f64) TEST(svbfloat16_t, bfloat16_t, bf16) -/* { dg-final { scan-assembler-times {\tdup\tz[0-9]+\.q, z[0-9]+\.q\[0\]} 12 { target aarch64_little_endian } } } */ +/* { dg-final { scan-assembler-not "dup" { target aarch64_little_endian } } } */ +/* { dg-final { scan-assembler-times {\tld1rqb\tz0\.b, p0/z, \[x0\]} 2 { target aarch64_little_endian } } } */ +/* { dg-final { scan-assembler-times {\tld1rqh\tz0\.h, p0/z, \[x0\]} 4 { target aarch64_little_endian } } } */ +/* { dg-final { scan-assembler-times {\tld1rqw\tz0\.s, p0/z, \[x0\]} 3 { target aarch64_little_endian } } } */ +/* { dg-final { scan-assembler-times {\tld1rqd\tz0\.d, p0/z, \[x0\]} 3 { target aarch64_little_endian } } } */