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Mon, 8 Aug 2022 06:04:10 GMT Received: from d06av26.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id B0BF5AE045; Mon, 8 Aug 2022 06:04:10 +0000 (GMT) Received: from d06av26.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 17829AE051; Mon, 8 Aug 2022 06:04:09 +0000 (GMT) Received: from [9.200.38.112] (unknown [9.200.38.112]) by d06av26.portsmouth.uk.ibm.com (Postfix) with ESMTP; Mon, 8 Aug 2022 06:04:08 +0000 (GMT) Message-ID: <9c7df6aa-c768-114e-4b1e-df6ce65a63b9@linux.ibm.com> Date: Mon, 8 Aug 2022 14:04:07 +0800 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:91.0) Gecko/20100101 Thunderbird/91.12.0 Content-Language: en-US To: gcc-patches Subject: [PATCH v2, rs6000] Add multiply-add expand pattern [PR103109] X-TM-AS-GCONF: 00 X-Proofpoint-ORIG-GUID: do4w5UkK6hgsM8NPX-jPXE_FCgfna2FU X-Proofpoint-GUID: BSQNs7VmOfjKjV-naWLif9X1eJDkjE0S X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.883,Hydra:6.0.517,FMLib:17.11.122.1 definitions=2022-08-08_03,2022-08-05_01,2022-06-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 phishscore=0 suspectscore=0 malwarescore=0 lowpriorityscore=0 mlxscore=0 bulkscore=0 impostorscore=0 adultscore=0 priorityscore=1501 mlxlogscore=999 spamscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2206140000 definitions=main-2208080031 X-Spam-Status: No, score=-12.7 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_EF, GIT_PATCH_0, KAM_SHORT, RCVD_IN_MSPIKE_H2, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: HAO CHEN GUI via Gcc-patches From: HAO CHEN GUI Reply-To: HAO CHEN GUI Cc: Peter Bergner , David , Segher Boessenkool Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1740571886227534725?= X-GMAIL-MSGID: =?utf-8?q?1740571886227534725?= Hi, This patch adds an expand and several insns for multiply-add with three 64bit operands. Compared with last version, the main changes are: 1 The "maddld" pattern is reused for the low-part generation. 2 A runnable testcase replaces the original compiling case. 3 Fixes indention problems. Bootstrapped and tested on powerpc64-linux BE and LE with no regressions. Is this okay for trunk? Any recommendations? Thanks a lot. ChangeLog 2022-08-08 Haochen Gui gcc/ PR target/103109 * config/rs6000/rs6000.md (maddditi4): New pattern for multiply-add. (madddi4_highpart): New. (madddi4_highpart_le): New. gcc/testsuite/ PR target/103109 * gcc.target/powerpc/pr103109.c: New. patch.diff diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md index c55ee7e171a..4c58023490a 100644 --- a/gcc/config/rs6000/rs6000.md +++ b/gcc/config/rs6000/rs6000.md @@ -3217,7 +3217,7 @@ (define_expand "mul3" DONE; }) -(define_insn "*maddld4" +(define_insn "maddld4" [(set (match_operand:GPR 0 "gpc_reg_operand" "=r") (plus:GPR (mult:GPR (match_operand:GPR 1 "gpc_reg_operand" "r") (match_operand:GPR 2 "gpc_reg_operand" "r")) @@ -3226,6 +3226,52 @@ (define_insn "*maddld4" "maddld %0,%1,%2,%3" [(set_attr "type" "mul")]) +(define_expand "maddditi4" + [(set (match_operand:TI 0 "gpc_reg_operand") + (plus:TI + (mult:TI (any_extend:TI (match_operand:DI 1 "gpc_reg_operand")) + (any_extend:TI (match_operand:DI 2 "gpc_reg_operand"))) + (any_extend:TI (match_operand:DI 3 "gpc_reg_operand"))))] + "TARGET_MADDLD && TARGET_POWERPC64" +{ + rtx op0_lo = gen_rtx_SUBREG (DImode, operands[0], BYTES_BIG_ENDIAN ? 8 : 0); + rtx op0_hi = gen_rtx_SUBREG (DImode, operands[0], BYTES_BIG_ENDIAN ? 0 : 8); + + emit_insn (gen_maddlddi4 (op0_lo, operands[1], operands[2], operands[3])); + + if (BYTES_BIG_ENDIAN) + emit_insn (gen_madddi4_highpart (op0_hi, operands[1], operands[2], + operands[3])); + else + emit_insn (gen_madddi4_highpart_le (op0_hi, operands[1], operands[2], + operands[3])); + DONE; +}) + +(define_insn "madddi4_highpart" + [(set (match_operand:DI 0 "gpc_reg_operand" "=r") + (subreg:DI + (plus:TI + (mult:TI (any_extend:TI (match_operand:DI 1 "gpc_reg_operand" "r")) + (any_extend:TI (match_operand:DI 2 "gpc_reg_operand" "r"))) + (any_extend:TI (match_operand:DI 3 "gpc_reg_operand" "r"))) + 0))] + "TARGET_MADDLD && BYTES_BIG_ENDIAN && TARGET_POWERPC64" + "maddhd %0,%1,%2,%3" + [(set_attr "type" "mul")]) + +(define_insn "madddi4_highpart_le" + [(set (match_operand:DI 0 "gpc_reg_operand" "=r") + (subreg:DI + (plus:TI + (mult:TI (any_extend:TI (match_operand:DI 1 "gpc_reg_operand" "r")) + (any_extend:TI (match_operand:DI 2 "gpc_reg_operand" "r"))) + (any_extend:TI (match_operand:DI 3 "gpc_reg_operand" "r"))) + 8))] + "TARGET_MADDLD && !BYTES_BIG_ENDIAN && TARGET_POWERPC64" + "maddhd %0,%1,%2,%3" + [(set_attr "type" "mul")]) + (define_insn "udiv3" [(set (match_operand:GPR 0 "gpc_reg_operand" "=r") (udiv:GPR (match_operand:GPR 1 "gpc_reg_operand" "r") diff --git a/gcc/testsuite/gcc.target/powerpc/pr103109.c b/gcc/testsuite/gcc.target/powerpc/pr103109.c new file mode 100644 index 00000000000..969b9751b21 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/pr103109.c @@ -0,0 +1,110 @@ +/* { dg-do run { target { has_arch_ppc64 } } } */ +/* { dg-options "-O2 -mdejagnu-cpu=power9 -save-temps" } */ +/* { dg-require-effective-target int128 } */ +/* { dg-require-effective-target p9modulo_hw } */ +/* { dg-final { scan-assembler-times {\mmaddld\M} 2 } } */ +/* { dg-final { scan-assembler-times {\mmaddhd\M} 1 } } */ +/* { dg-final { scan-assembler-times {\mmaddhdu\M} 1 } } */ + +union U { + __int128 i128; + struct { + long l1; + long l2; + } s; +}; + +__int128 +create_i128 (long most_sig, long least_sig) +{ + union U u; + +#if __LITTLE_ENDIAN__ + u.s.l1 = least_sig; + u.s.l2 = most_sig; +#else + u.s.l1 = most_sig; + u.s.l2 = least_sig; +#endif + return u.i128; +} + + +#define DEBUG 0 + +#if DEBUG +#include +#include + +void print_i128(__int128 val, int unsignedp) +{ + if (unsignedp) + printf(" %llu ", (unsigned long long)(val >> 64)); + else + printf(" %lld ", (signed long long)(val >> 64)); + + printf("%llu (0x%llx %llx)", + (unsigned long long)(val & 0xFFFFFFFFFFFFFFFF), + (unsigned long long)(val >> 64), + (unsigned long long)(val & 0xFFFFFFFFFFFFFFFF)); +} +#endif + +void abort (void); + +__attribute__((noinline)) +__int128 multiply_add (long a, long b, long c) +{ + return (__int128) a * b + c; +} + +__attribute__((noinline)) +unsigned __int128 multiply_addu (unsigned long a, unsigned long b, + unsigned long c) +{ + return (unsigned __int128) a * b + c; +} + +int main () +{ + long a = 0xFEDCBA9876543210L; + long b = 0x1000000L; + long c = 0x123456L; + __int128 expected_result = create_i128 (0xFFFFFFFFFFFEDCBAL, + 0x9876543210123456L); + + __int128 result = multiply_add (a, b, c); + + if (result != expected_result) + { +#if DEBUG + printf ("ERROR: multiply_add (%lld, %lld, %lld) = ", a, b, c); + print_i128 (result, 0); + printf ("\n does not match expected_result = "); + print_i128 (expected_result, 0); + printf ("\n\n"); +#else + abort(); +#endif + } + + unsigned long au = 0xFEDCBA9876543210UL; + unsigned long bu = 0x1000000UL; + unsigned long cu = 0x123456UL; + unsigned __int128 expected_resultu = create_i128 (0x0000000000FEDCBAL, + 0x9876543210123456L); + + unsigned __int128 resultu = multiply_addu (au, bu, cu); + if (resultu != expected_resultu) + { +#if DEBUG + printf ("ERROR: multiply_addu (%llu, %llu, %llu) = ", au, bu, cu); + print_i128 (resultu, 1); + printf ("\n does not match expected_result = "); + print_i128 (expected_resultu, 1); + printf ("\n\n"); +#else + abort(); +#endif + } +}