diff --git a/gcc/config/s390/s390.md b/gcc/config/s390/s390.md
index 55c0064bba84..f37d8fd33a15 100644
--- a/gcc/config/s390/s390.md
+++ b/gcc/config/s390/s390.md
@@ -153,7 +153,6 @@ (define_c_enum "unspec" [
    UNSPEC_VEC_VMALO

    UNSPEC_VEC_GATHER
-   UNSPEC_VEC_EXTRACT
    UNSPEC_VEC_INSERT_AND_ZERO
    UNSPEC_VEC_LOAD_BNDRY
    UNSPEC_VEC_LOAD_LEN
@@ -1744,8 +1743,8 @@ (define_split
    && GENERAL_REG_P (operands[0])
    && VECTOR_REG_P (operands[1])"
   [(set (match_dup 2) (match_dup 4))
-   (set (match_dup 3) (unspec:DI [(match_dup 5) (const_int 1)]
-				 UNSPEC_VEC_EXTRACT))]
+   (set (match_dup 3) (vec_select:DI (match_dup 5)
+		       (parallel [(const_int 1)])))]
 {
   operands[2] = operand_subword (operands[0], 0, 0, TImode);
   operands[3] = operand_subword (operands[0], 1, 0, TImode);
diff --git a/gcc/config/s390/vector.md b/gcc/config/s390/vector.md
index 6f46bed03e00..6a7ee7870f37 100644
--- a/gcc/config/s390/vector.md
+++ b/gcc/config/s390/vector.md
@@ -264,11 +264,13 @@ (define_split
 	(match_operand:V_128 1 "register_operand" ""))]
   "TARGET_VX && GENERAL_REG_P (operands[0]) && VECTOR_REG_P (operands[1])"
   [(set (match_dup 2)
-	(unspec:DI [(subreg:V2DI (match_dup 1) 0)
-		    (const_int 0)] UNSPEC_VEC_EXTRACT))
+       (vec_select:DI
+         (subreg:V2DI (match_dup 1) 0)
+           (parallel [(const_int 0)])))
    (set (match_dup 3)
-	(unspec:DI [(subreg:V2DI (match_dup 1) 0)
-		    (const_int 1)] UNSPEC_VEC_EXTRACT))]
+       (vec_select:DI
+         (subreg:V2DI (match_dup 1) 0)
+           (parallel [(const_int 1)])))]
 {
   operands[2] = operand_subword (operands[0], 0, 0, <MODE>mode);
   operands[3] = operand_subword (operands[0], 1, 0, <MODE>mode);
@@ -505,22 +507,24 @@ (define_insn "*vec_set<mode>_plus"
   [(set_attr "op_type" "VRS")])


-; FIXME: Support also vector mode operands for 0
-; FIXME: This should be (vec_select ..) or something but it does only
allow constant selectors :(
-; This is used via RTL standard name as well as for expanding the builtin
+;; FIXME: Support also vector mode operands for 0
+;; This is used via RTL standard name as well as for expanding the builtin
 (define_expand "vec_extract<mode><non_vec_l>"
-  [(set (match_operand:<non_vec> 0 "nonimmediate_operand" "")
-	(unspec:<non_vec> [(match_operand:V  1 "register_operand" "")
-			   (match_operand:SI 2 "nonmemory_operand" "")]
-			  UNSPEC_VEC_EXTRACT))]
-  "TARGET_VX")
+  [(set (match_operand:<non_vec>    0 "nonimmediate_operand" "")
+       (vec_select:<non_vec>
+         (match_operand:V	    1 "register_operand" "")
+         (parallel
+          [(match_operand:SI	    2 "nonmemory_operand" "")])))]
+  "TARGET_VX"
+)

 ; vlgvb, vlgvh, vlgvf, vlgvg, vsteb, vsteh, vstef, vsteg
 (define_insn "*vec_extract<mode>"
-  [(set (match_operand:<non_vec> 0 "nonimmediate_operand"          "=d,R")
-	(unspec:<non_vec> [(match_operand:V  1 "register_operand"   "v,v")
-			   (match_operand:SI 2 "nonmemory_operand" "an,I")]
-			  UNSPEC_VEC_EXTRACT))]
+  [(set (match_operand:<non_vec> 0 "nonimmediate_operand" "=d,R")
+       (vec_select:<non_vec>
+         (match_operand:V	 1 "nonmemory_operand"  "v,v")
+         (parallel
+          [(match_operand:SI	 2 "nonmemory_operand" "an,I")])))]
   "TARGET_VX
    && (!CONST_INT_P (operands[2])
        || UINTVAL (operands[2]) < GET_MODE_NUNITS (<V:MODE>mode))"
@@ -531,11 +535,11 @@ (define_insn "*vec_extract<mode>"

 ; vlgvb, vlgvh, vlgvf, vlgvg
 (define_insn "*vec_extract<mode>_plus"
-  [(set (match_operand:<non_vec>                      0
"nonimmediate_operand" "=d")
-	(unspec:<non_vec> [(match_operand:V           1 "register_operand"
 "v")
-			   (plus:SI (match_operand:SI 2 "nonmemory_operand"     "a")
-				    (match_operand:SI 3 "const_int_operand"     "n"))]
-			   UNSPEC_VEC_EXTRACT))]
+  [(set (match_operand:<non_vec>       0 "nonimmediate_operand" "=d")
+	(vec_select:<non_vec>
+	 (match_operand:V	       1 "register_operand"      "v")
+	 (plus:SI (match_operand:SI    2 "nonmemory_operand"     "a")
+	  (parallel [(match_operand:SI 3 "const_int_operand"     "n")]))))]
   "TARGET_VX"
   "vlgv<bhfgq>\t%0,%v1,%Y3(%2)"
   [(set_attr "op_type" "VRS")])
diff --git a/gcc/config/s390/vx-builtins.md b/gcc/config/s390/vx-builtins.md
index 22d0355ec219..fc13f0a3393e 100644
--- a/gcc/config/s390/vx-builtins.md
+++ b/gcc/config/s390/vx-builtins.md
@@ -440,12 +440,13 @@ (define_expand "vec_splat<mode>"
 (define_insn "vec_scatter_element<V_HW_4:mode>_DI"
   [(set (mem:<non_vec>
 	 (plus:DI (zero_extend:DI
-		   (unspec:SI [(match_operand:V4SI 1 "register_operand"   "v")
-			       (match_operand:QI   3 "const_mask_operand" "C")]
-			      UNSPEC_VEC_EXTRACT))
-		  (match_operand:SI                2 "address_operand"   "ZQ")))
-	(unspec:<non_vec> [(match_operand:V_HW_4          0 "register_operand"
  "v")
-			   (match_dup 3)] UNSPEC_VEC_EXTRACT))]
+		   (vec_select:SI
+		    (match_operand:V4SI		  1 "register_operand"   "v")
+		    (parallel [(match_operand:QI  3 "const_mask_operand" "C")])))
+	  (match_operand:SI			  2 "address_operand" "ZQ")))
+	(vec_select:<non_vec>
+	 (match_operand:V_HW_4			  0 "register_operand"   "v")
+	 (parallel [(match_dup 3)])))]
   "TARGET_VX && TARGET_64BIT && UINTVAL (operands[3]) < 4"
   "vscef\t%v0,%O2(%v1,%R2),%3"
