[committed,PR,target/109508] Adjust conditional move expansion for SFB
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Commit Message
Recently the conditional move expander's predicates were loosened for
the benefit of the THEAD processors. In particular one operand that was
previously "register_operand" is now "reg_or_0_operand". That's fine
for THEAD, but breaks for SFB which requires a register for that operand.
This results in an ICE when compiling the testcase an SFB target such as
the sifive s76.
This change adjusts the expansion code slightly to copy the value into a
register for SFB.
Bootstrapped and regression tested (c,c++,fortran only) with a toolchain
configured to enable SFB by default.
Installing on the trunk momentarily.
Jeff
commit a647198fcf7463a42c8e035a429200e7998735dc
Author: Jeff Law <jlaw@ventanamicro>
Date: Sun Apr 16 09:55:32 2023 -0600
[committed] [PR target/109508] Adjust conditional move expansion for SFB
Recently the conditional move expander's predicates were loosened for the
benefit of the THEAD processors. In particular one operand that was
previously "register_operand" is now "reg_or_0_operand". That's fine for
THEAD, but breaks for SFB which requires a register for that operand.
This results in an ICE when compiling the testcase an SFB target such as
the sifive s76.
This change adjusts the expansion code slightly to copy the value into
a register for SFB.
Bootstrapped and regression tested (c,c++,fortran only) with a toolchain
configured to enable SFB by default.
PR target/109508
gcc/
* config/riscv/riscv.cc (riscv_expand_conditional_move): For
TARGET_SFB_ALU, force the true arm into a register.
gcc/testsuite
* gcc.target/riscv/pr109508.c: New test.
@@ -3419,6 +3419,12 @@ riscv_expand_conditional_move (rtx dest, rtx op, rtx cons, rtx alt)
{
riscv_emit_int_compare (&code, &op0, &op1);
rtx cond = gen_rtx_fmt_ee (code, GET_MODE (op0), op0, op1);
+
+ /* The expander allows (const_int 0) for CONS for the benefit of
+ TARGET_XTHEADCONDMOV, but that case isn't supported for
+ TARGET_SFB_ALU. So force that operand into a register if
+ necessary. */
+ cons = force_reg (GET_MODE (dest), cons);
emit_insn (gen_rtx_SET (dest, gen_rtx_IF_THEN_ELSE (GET_MODE (dest),
cond, cons, alt)));
return true;
new file mode 100644
@@ -0,0 +1,12 @@
+/* { dg-do compile } */
+/* { dg-options "-mcpu=sifive-s76" } */
+
+typedef char __attribute__((__vector_size__ (1))) V;
+
+V v;
+
+void
+foo (void)
+{
+ (char) __builtin_shuffle (0 % v, (V){6}, v);
+}