diff mbox series

RISC-V: Prohibit combination of 'E' and 'H'

Message ID 92fad87801003eaa4cf9f47a1ab8d6e6f015ed12.1697866371.git.research_trasio@irq.a4lg.com
State Accepted
Headers
Series RISC-V: Prohibit combination of 'E' and 'H' |

Checks

Context Check Description
snail/gcc-patch-check success Github commit url

Commit Message

Tsukasa OI Oct. 21, 2023, 5:32 a.m. UTC 
  From: Tsukasa OI <research_trasio@irq.a4lg.com>

According to the ratified privileged specification (version 20211203),
it says:

> The hypervisor extension depends on an "I" base integer ISA with 32 x
> registers (RV32I or RV64I), not RV32E, which has only 16 x registers.

Also in the latest draft, it also prohibits RV64E with the 'H' extension.
This commit prohibits the combination of 'E' and 'H' extensions.

gcc/ChangeLog:

	* common/config/riscv/riscv-common.cc (riscv_subset_list::parse):
	Prohibit 'E' and 'H' combinations.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/arch-26.c: New test.
---
 gcc/common/config/riscv/riscv-common.cc  | 4 ++++
 gcc/testsuite/gcc.target/riscv/arch-26.c | 4 ++++
 2 files changed, 8 insertions(+)
 create mode 100644 gcc/testsuite/gcc.target/riscv/arch-26.c


base-commit: 66c26e5cfdf65ae024fcb658629dc5a9a10f3f85

Comments

Jeff Law Oct. 21, 2023, 6:04 p.m. UTC | #1 
On 10/20/23 23:32, Tsukasa OI wrote:
> From: Tsukasa OI <research_trasio@irq.a4lg.com>
> 
> According to the ratified privileged specification (version 20211203),
> it says:
> 
>> The hypervisor extension depends on an "I" base integer ISA with 32 x
>> registers (RV32I or RV64I), not RV32E, which has only 16 x registers.
> 
> Also in the latest draft, it also prohibits RV64E with the 'H' extension.
> This commit prohibits the combination of 'E' and 'H' extensions.
> 
> gcc/ChangeLog:
> 
> 	* common/config/riscv/riscv-common.cc (riscv_subset_list::parse):
> 	Prohibit 'E' and 'H' combinations.
> 
> gcc/testsuite/ChangeLog:
> 
> 	* gcc.target/riscv/arch-26.c: New test.
In a similar vein, GCC doesn't really care about the privileged 
extensions.  So this won't really affect code generation.  So I'll ACK, 
but going forward let's start doing the regression test.  If you need 
help setting that up, I'm sure someone here can make suggestions. 
Personally I prefer a qemu+binfmt setup as it doesn't require setting up 
a board file and explicitly calling the simulator, ie, it looks a lot 
like native testing.

jeff
Tsukasa OI Oct. 22, 2023, 1:33 a.m. UTC | #2 
On 2023/10/22 3:04, Jeff Law wrote:
> 
> 
> On 10/20/23 23:32, Tsukasa OI wrote:
>> From: Tsukasa OI <research_trasio@irq.a4lg.com>
>>
>> According to the ratified privileged specification (version 20211203),
>> it says:
>>
>>> The hypervisor extension depends on an "I" base integer ISA with 32 x
>>> registers (RV32I or RV64I), not RV32E, which has only 16 x registers.
>>
>> Also in the latest draft, it also prohibits RV64E with the 'H' extension.
>> This commit prohibits the combination of 'E' and 'H' extensions.
>>
>> gcc/ChangeLog:
>>
>>     * common/config/riscv/riscv-common.cc (riscv_subset_list::parse):
>>     Prohibit 'E' and 'H' combinations.
>>
>> gcc/testsuite/ChangeLog:
>>
>>     * gcc.target/riscv/arch-26.c: New test.
> In a similar vein, GCC doesn't really care about the privileged
> extensions.  So this won't really affect code generation.  So I'll ACK,
> but going forward let's start doing the regression test.  If you need
> help setting that up, I'm sure someone here can make suggestions.
> Personally I prefer a qemu+binfmt setup as it doesn't require setting up
> a board file and explicitly calling the simulator, ie, it looks a lot
> like native testing.
> 
> jeff
> 

Thanks for reviewing.  I'll commit two patches soon.

Yes, for GCC, privileged extensions (and version numbers) are not
important in general (unless toolchain conventions create privileged
built-in functions).

Intents of my two small patch sets are:

1. Allow inline assembly to use new/privileged extensions.
2. Allow/disallow same -march for both CC and AS (as possible).
3. (As long as no major compatibility breakage happens),
   make both GCC and Binutils faithful to the specification
   and the current status (that would also improve interoperability).

Hmm, I generally agree with your opinion and I made a board file for
DejaGnu (running qemu-riscv64) to run "make check-gcc
RUNTESTFLAGS='--target_board=riscv-sim riscv.exp'" because it already
contains many execute tests (and annoys me if I don't do that).

What I'm not sure is, what kind of regression tests we need?

(In my mind)
Level 1: Make nearly empty program with specific -march (and optionally
         -mabi?) and make sure that it works.
Level 2: Make a program with inline assembly and execute tests with
         specific configurations (with specific -march and -mabi)
         [I'm not sure how to write **and optionally execute tests**]

I would like to hear your thoughts.

Thanks,
Tsukasa
Jeff Law Oct. 23, 2023, 1:54 a.m. UTC | #3 
On 10/21/23 19:33, Tsukasa OI wrote:

> 
> Hmm, I generally agree with your opinion and I made a board file for
> DejaGnu (running qemu-riscv64) to run "make check-gcc
> RUNTESTFLAGS='--target_board=riscv-sim riscv.exp'" because it already
> contains many execute tests (and annoys me if I don't do that).
> 
> What I'm not sure is, what kind of regression tests we need?
> 
> (In my mind)
> Level 1: Make nearly empty program with specific -march (and optionally
>           -mabi?) and make sure that it works.
> Level 2: Make a program with inline assembly and execute tests with
>           specific configurations (with specific -march and -mabi)
>           [I'm not sure how to write **and optionally execute tests**]
> 
> I would like to hear your thoughts.
So I don't think we need to do a large matrix of extensions or anything 
like that.  Whatever config you usually build should be sufficient.

What most folks do is a make -k check before/after their patch and 
compare the results.  That's the standard.

If you change a target independent file, then the standard would be to 
bootstrap and regression test on x86 or similar primary architecture.

Jeff
diff mbox series

Patch

diff --git a/gcc/common/config/riscv/riscv-common.cc b/gcc/common/config/riscv/riscv-common.cc
index d7216285c648..36201559deff 100644
--- a/gcc/common/config/riscv/riscv-common.cc
+++ b/gcc/common/config/riscv/riscv-common.cc
@@ -1495,6 +1495,10 @@  riscv_subset_list::parse (const char *arch, location_t loc)
     error_at (loc, "%<-march=%s%>: z*inx conflicts with floating-point "
 		   "extensions", arch);
 
+  /* 'H' hypervisor extension requires base ISA with 32 registers.  */
+  if (subset_list->lookup ("e") && subset_list->lookup ("h"))
+    error_at (loc, "%<-march=%s%>: h extension requires i extension", arch);
+
   return subset_list;
 
 fail:
diff --git a/gcc/testsuite/gcc.target/riscv/arch-26.c b/gcc/testsuite/gcc.target/riscv/arch-26.c
new file mode 100644
index 000000000000..0b48bc945b58
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/arch-26.c
@@ -0,0 +1,4 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv32eh -mabi=ilp32e" } */
+int foo() {}
+/* { dg-error "'-march=rv32eh': h extension requires i extension" "" { target *-*-* } 0 } */