diff mbox series

[2/2] xtensa: Merge '*addx' and '*subx' insn patterns into one

Message ID 8f4e2726-0844-3dd0-8a27-7fb669db8f76@yahoo.co.jp
State Accepted
Headers
Series [1/2] xtensa: Optimize '(x & CST1_POW2) != 0 ? CST2_POW2 : 0' |

Checks

Context Check Description
snail/gcc-patch-check success Github commit url

Commit Message

Takayuki 'January June' Suwa May 22, 2023, 7:04 a.m. UTC 
  By making use of the 'addsub_operator' added in the last patch.

gcc/ChangeLog:

	* config/xtensa/xtensa.md (*addsubx): Rename from '*addx',
	and change to also accept '*subx' pattern.
	(*subx): Remove.
---
 gcc/config/xtensa/xtensa.md | 31 +++++++++++++------------------
 1 file changed, 13 insertions(+), 18 deletions(-)

Comments

Max Filippov May 23, 2023, 8:05 p.m. UTC | #1 
On Mon, May 22, 2023 at 12:06 AM Takayuki 'January June' Suwa
<jjsuwa_sys3175@yahoo.co.jp> wrote:
>
> By making use of the 'addsub_operator' added in the last patch.
>
> gcc/ChangeLog:
>
>         * config/xtensa/xtensa.md (*addsubx): Rename from '*addx',
>         and change to also accept '*subx' pattern.
>         (*subx): Remove.
> ---
>  gcc/config/xtensa/xtensa.md | 31 +++++++++++++------------------
>  1 file changed, 13 insertions(+), 18 deletions(-)

Regtested for target=xtensa-linux-uclibc, no new regressions.
Committed to master.
diff mbox series

Patch

diff --git a/gcc/config/xtensa/xtensa.md b/gcc/config/xtensa/xtensa.md
index bd4614e4be0..f3313266645 100644
--- a/gcc/config/xtensa/xtensa.md
+++ b/gcc/config/xtensa/xtensa.md
@@ -170,15 +170,24 @@ 
    (set_attr "mode"	"SI")
    (set_attr "length"	"2,2,3,3,3")])
 
-(define_insn "*addx"
+(define_insn "*addsubx"
   [(set (match_operand:SI 0 "register_operand" "=a")
-	(plus:SI (ashift:SI (match_operand:SI 1 "register_operand" "r")
+	(match_operator:SI 4 "addsub_operator"
+		[(ashift:SI (match_operand:SI 1 "register_operand" "r")
 			    (match_operand:SI 3 "addsubx_operand" "i"))
-		 (match_operand:SI 2 "register_operand" "r")))]
+		 (match_operand:SI 2 "register_operand" "r")]))]
   "TARGET_ADDX"
 {
   operands[3] = GEN_INT (1 << INTVAL (operands[3]));
-  return "addx%3\t%0, %1, %2";
+  switch (GET_CODE (operands[4]))
+    {
+    case PLUS:
+      return "addx%3\t%0, %1, %2";
+    case MINUS:
+      return "subx%3\t%0, %1, %2";
+    default:
+      gcc_unreachable ();
+    }
 }
   [(set_attr "type"	"arith")
    (set_attr "mode"	"SI")
@@ -207,20 +216,6 @@ 
    (set_attr "mode"	"SI")
    (set_attr "length"	"3")])
 
-(define_insn "*subx"
-  [(set (match_operand:SI 0 "register_operand" "=a")
-	(minus:SI (ashift:SI (match_operand:SI 1 "register_operand" "r")
-			     (match_operand:SI 3 "addsubx_operand" "i"))
-		  (match_operand:SI 2 "register_operand" "r")))]
-  "TARGET_ADDX"
-{
-  operands[3] = GEN_INT (1 << INTVAL (operands[3]));
-  return "subx%3\t%0, %1, %2";
-}
-  [(set_attr "type"	"arith")
-   (set_attr "mode"	"SI")
-   (set_attr "length"	"3")])
-
 (define_insn "subsf3"
   [(set (match_operand:SF 0 "register_operand" "=f")
 	(minus:SF (match_operand:SF 1 "register_operand" "f")