From patchwork Wed May 24 09:41:13 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?5qKF5p2w?= X-Patchwork-Id: 98415 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp2717821vqo; Wed, 24 May 2023 02:44:44 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ5lmo7t1wisAFpI2646ye+H67+KvwMYLNwQPVgo12b69ASPTDSuBCf1dITF5vkFRofNIYSp X-Received: by 2002:aa7:dd10:0:b0:510:a5a1:b36d with SMTP id i16-20020aa7dd10000000b00510a5a1b36dmr1718833edv.33.1684921484778; Wed, 24 May 2023 02:44:44 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1684921484; cv=none; d=google.com; s=arc-20160816; b=xfZBJmoVMNRq6lQ0EQHEtB48Wi60CmDpmH9D76sPVSajFbGrEq6NDp76XskR8KUMr1 bqr5Pd392BdfOEMbFs+LFVQz5Y0iLxj3JS6ExRsvqiksIF2EA8g5SAp16Hndk1AAXxrp 7XwKZ8tYQl0AqS/L25R66eJFW4yxetTHIUef5gXsxqDEBoCcjTrz9zB2sKd4DCgiLgzE zsFuq8dVWcaYGiR0j6u9Pzc1Yxi4lowh1QqP63a6u2o/iCeCcrbAL0kuX7BIswagnH4N A0vqcD9lsV9wvE9X9rv8AcfD/4rJlr5z3Ortl78MfS5q4f2zAG7UrdtxYu57EuT5L4/G kIAg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:message-id:to:in-reply-to:references:date:from:cc :subject:dkim-signature:dmarc-filter:delivered-to; bh=gmjsc0RtbvflVAqYrCgDc6NSlLUvCzvvJNvnktKHQEc=; b=lHdjOQ55Nry8iMAdRXZVqqu03Qaz+zYQxDJI7kFod5MteSvuHbUxMKRFjr63wnmISh UqkEgAAG4Mz/Vy0LL+Df45jg/CZWzeq4FW5CLIAWtMK/T1tz1t2AE4QvCIf4rfvKDhyF bJXbqH75ZBjcqA89ws3csQSeO4qDXmn2JYg1CrbytwDSN88lcD5dYNoVwBHaTDaqzWjx eGne4URhu6ZK9GHRTSScpwh8hIZK5FIKb+gvy4hQNJWlV8d3RrBNHrb91t/2Zepru0+r mOFHfhl3p0sVjkdiRzLhckfvmQ3kMrhIA5OCsIjiB+PpN+ivyufL9vALc7PQHiG9o3mM ZOEQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@oss.cipunited.com header.s=feishu2303200042 header.b=uMHMODFq; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org" Received: from sourceware.org (server2.sourceware.org. [2620:52:3:1:0:246e:9693:128c]) by mx.google.com with ESMTPS id s6-20020a1709064d8600b0096f6bbfea57si1720736eju.988.2023.05.24.02.44.44 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 24 May 2023 02:44:44 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) client-ip=2620:52:3:1:0:246e:9693:128c; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@oss.cipunited.com header.s=feishu2303200042 header.b=uMHMODFq; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org" Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 79462383907D for ; Wed, 24 May 2023 09:42:19 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from s01.bc.larksuite.com (s01.bc.larksuite.com [209.127.230.13]) by sourceware.org (Postfix) with UTF8SMTPS id 60A2C3857704 for ; Wed, 24 May 2023 09:41:18 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 60A2C3857704 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=oss.cipunited.com Authentication-Results: sourceware.org; spf=none smtp.mailfrom=oss.cipunited.com DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; s=feishu2303200042; d=oss.cipunited.com; t=1684921274; h=from:subject:mime-version:from:date:message-id:subject:to:cc: reply-to:content-type:mime-version:in-reply-to:message-id; bh=xb67mRnXDzfxN+5ds8mKCL6S/H9malu5JnoOcAE5Hcs=; b=uMHMODFqoWbqSaZKprFIzujTvixycZnOue6Ot/rKExSYE+qB/HHooxfbYD94jvv+gxcGOa 7sz3GUF1Q7stZkGZUB+qphfUS9sbuGf4EP3GF2ZmojD2av7EHPOFuUSmFul9mU46MTylAq GHzhH1ibQc3Tmab7RJ3RUwU+f4s1fx8DCEFZFkSqkrmHB3BmK9Ji+SYoEZeHq2QNFbLCVB jvQTGGjs8PlzzLAENPzpOZgXfNEzZ01bLWl4IsQvw4fs1tWkwcUtLcgRPRENLMop95TXAp 6ZzXT9pVk2nGTC45lHObp5Erfd8CHTN9gduQ2Bm/iis2CJQ4rP241jnYtriIRw== Subject: [PATCH v3 2/9] MIPS: Add MOVx instructions support for mips16e2 X-Mailer: git-send-email 2.40.1 Cc: "YunQiang Su" , "Maciej W . Rozycki" From: "Jie Mei" Date: Wed, 24 May 2023 17:41:13 +0800 References: In-Reply-To: To: Message-Id: <8e0c8971407e0ad350476051e8061172ed706f33.1684918168.git.jie.mei@oss.cipunited.com> Mime-Version: 1.0 X-Lms-Return-Path: X-Spam-Status: No, score=-10.5 required=5.0 tests=BAYES_00, DKIM_ADSP_NXDOMAIN, DKIM_INVALID, DKIM_SIGNED, GIT_PATCH_0, HTML_MESSAGE, KAM_DMARC_STATUS, KAM_NUMSUBJECT, KAM_SHORT, NO_DNS_FOR_FROM, SPF_HELO_NONE, SPF_NONE, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-Content-Filtered-By: Mailman/MimeDel 2.1.29 X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1766768230838884890?= X-GMAIL-MSGID: =?utf-8?q?1766768230838884890?= This patch adds MOVx instructions from mips16e2 (movn,movz,movtn,movtz) with corresponding tests. gcc/ChangeLog: * config/mips/mips.h(ISA_HAS_CONDMOVE): Add condition for ISA_HAS_MIPS16E2. * config/mips/mips.md(*mov_on_): Add logics for MOVx insts. (*mov_on__mips16e2): Generate MOVx instruction. (*mov_on__ne): Add logics for MOVx insts. (*mov_on__ne_mips16e2): Generate MOVx instruction. * config/mips/predicates.md(reg_or_0_operand_mips16e2): New predicate for MOVx insts. gcc/testsuite/ChangeLog: * gcc.target/mips/mips16e2-cmov.c: Added tests for MOVx instructions. --- gcc/config/mips/mips.h | 1 + gcc/config/mips/mips.md | 38 ++++++++++- gcc/config/mips/predicates.md | 6 ++ gcc/testsuite/gcc.target/mips/mips16e2-cmov.c | 68 +++++++++++++++++++ 4 files changed, 111 insertions(+), 2 deletions(-) create mode 100644 gcc/testsuite/gcc.target/mips/mips16e2-cmov.c diff --git a/gcc/config/mips/mips.h b/gcc/config/mips/mips.h index c6781670a54..a94b253e898 100644 --- a/gcc/config/mips/mips.h +++ b/gcc/config/mips/mips.h @@ -1081,6 +1081,7 @@ struct mips_cpu_info { ST Loongson 2E/2F. */ #define ISA_HAS_CONDMOVE (ISA_HAS_FP_CONDMOVE \ || TARGET_MIPS5900 \ + || ISA_HAS_MIPS16E2 \ || TARGET_LOONGSON_2EF) /* ISA has LDC1 and SDC1. */ diff --git a/gcc/config/mips/mips.md b/gcc/config/mips/mips.md index ac1d77afc7d..48d5f419ce0 100644 --- a/gcc/config/mips/mips.md +++ b/gcc/config/mips/mips.md @@ -7341,26 +7341,60 @@ (const_int 0)]) (match_operand:GPR 2 "reg_or_0_operand" "dJ,0") (match_operand:GPR 3 "reg_or_0_operand" "0,dJ")))] - "ISA_HAS_CONDMOVE" + "!TARGET_MIPS16 && ISA_HAS_CONDMOVE" "@ mov%T4\t%0,%z2,%1 mov%t4\t%0,%z3,%1" [(set_attr "type" "condmove") (set_attr "mode" "")]) +(define_insn "*mov_on__mips16e2" + [(set (match_operand:GPR 0 "register_operand" "=d,d,d,d") + (if_then_else:GPR + (match_operator 4 "equality_operator" + [(match_operand:MOVECC 1 "register_operand" ",,t,t") + (const_int 0)]) + (match_operand:GPR 2 "reg_or_0_operand_mips16e2" "dJ,0,dJ,0") + (match_operand:GPR 3 "reg_or_0_operand_mips16e2" "0,dJ,0,dJ")))] + "ISA_HAS_MIPS16E2 && ISA_HAS_CONDMOVE" + "@ + mov%T4\t%0,%z2,%1 + mov%t4\t%0,%z3,%1 + movt%T4\t%0,%z2 + movt%t4\t%0,%z3" + [(set_attr "type" "condmove") + (set_attr "mode" "") + (set_attr "extended_mips16" "yes")]) + (define_insn "*mov_on__ne" [(set (match_operand:GPR 0 "register_operand" "=d,d") (if_then_else:GPR (match_operand:GPR2 1 "register_operand" ",") (match_operand:GPR 2 "reg_or_0_operand" "dJ,0") (match_operand:GPR 3 "reg_or_0_operand" "0,dJ")))] - "ISA_HAS_CONDMOVE" + "!TARGET_MIPS16 && ISA_HAS_CONDMOVE" "@ movn\t%0,%z2,%1 movz\t%0,%z3,%1" [(set_attr "type" "condmove") (set_attr "mode" "")]) +(define_insn "*mov_on__ne_mips16e2" + [(set (match_operand:GPR 0 "register_operand" "=d,d,d,d") + (if_then_else:GPR + (match_operand:GPR2 1 "register_operand" ",,t,t") + (match_operand:GPR 2 "reg_or_0_operand_mips16e2" "dJ,0,dJ,0") + (match_operand:GPR 3 "reg_or_0_operand_mips16e2" "0,dJ,0,dJ")))] + "ISA_HAS_MIPS16E2 && ISA_HAS_CONDMOVE" + "@ + movn\t%0,%z2,%1 + movz\t%0,%z3,%1 + movtn\t%0,%z2 + movtz\t%0,%z3" + [(set_attr "type" "condmove") + (set_attr "mode" "") + (set_attr "extended_mips16" "yes")]) + (define_insn "*mov_on_" [(set (match_operand:SCALARF 0 "register_operand" "=f,f") (if_then_else:SCALARF diff --git a/gcc/config/mips/predicates.md b/gcc/config/mips/predicates.md index 87460a64652..e2cd5a8c65f 100644 --- a/gcc/config/mips/predicates.md +++ b/gcc/config/mips/predicates.md @@ -114,6 +114,12 @@ (not (match_test "TARGET_MIPS16"))) (match_operand 0 "register_operand"))) +(define_predicate "reg_or_0_operand_mips16e2" + (ior (and (match_operand 0 "const_0_operand") + (ior (not (match_test "TARGET_MIPS16")) + (match_test "ISA_HAS_MIPS16E2"))) + (match_operand 0 "register_operand"))) + (define_predicate "const_1_operand" (and (match_code "const_int,const_double,const_vector") (match_test "op == CONST1_RTX (GET_MODE (op))"))) diff --git a/gcc/testsuite/gcc.target/mips/mips16e2-cmov.c b/gcc/testsuite/gcc.target/mips/mips16e2-cmov.c new file mode 100644 index 00000000000..6e9dd82ebf3 --- /dev/null +++ b/gcc/testsuite/gcc.target/mips/mips16e2-cmov.c @@ -0,0 +1,68 @@ +/* { dg-options "-mno-abicalls -mgpopt -G8 -mabi=32 -mips16 -mmips16e2" } */ +/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */ + +/* Test MOVN. */ + +/* { dg-final { scan-assembler-times "test01:.*\tmovn\t.*test01\n" 1 } } */ +int +test01 (int a, int b, int c) +{ + return (a==0) ? b : c; +} + +/* { dg-final { scan-assembler-times "test02:.*\tmovn\t\\\$.,\\\$0.*test02\n" 1 } } */ +int +test02 (int a, int b, int c) +{ + return (a==0) ? b : 0; +} + +/* Test MOVZ. */ + +/* { dg-final { scan-assembler-times "test03:.*\tmovz\t.*test03\n" 1 } } */ +int +test03 (int a, int b, int c) +{ + return a ? b : c; +} + +/* { dg-final { scan-assembler-times "test04:.*\tmovz\t\\\$.,\\\$0.*test04\n" 1 } } */ +int +test04 (int a, int b, int c) +{ + return a ? b : 0; +} + +/* Test MOVTN. */ + +/* { dg-final { scan-assembler-times "test05:.*\tmovtn\t.*test05\n" 1 } } */ +int +test05 (int a, int b, int c, int d) +{ + return a >= b ? c : d; +} + +/* { dg-final { scan-assembler-times "test06:.*\tmovtn\t\\\$2,\\\$0.*test06\n" 1 } } */ +int +test06 (int a, int b, int c, int d) +{ + return a >= b ? c : 0; +} + +/* Test MOVTZ. */ + +/* { dg-final { scan-assembler-times "test07:.*\tmovtz\t.*test07\n" 1 } } */ +int +test07 (int a, int b, int c, int d) +{ + return a < b ? c : d; +} + +/* { dg-final { scan-assembler-times "test08:.*\tmovtz\t\\\$.,\\\$0.*test08\n" 1 } } */ +int +test08 (int a, int b, int c, int d) +{ + return a < b ? c : 0; +} + +