diff mbox series

[SPARC] Fix PR target/109140

Message ID 8198261.T7Z3S40VBb@fomalhaut
State Repeat Merge
Headers
Series [SPARC] Fix PR target/109140 |

Checks

Context Check Description
snail/gcc-patch-check warning Git am fail log

Commit Message

Eric Botcazou March 28, 2023, 8:48 a.m. UTC 
  This is a regression present on the mainline and 12 branch at -O2, but the 
issue is related to vectorization so was present at -O3 in earlier versions.

The vcondu expander that was added for VIS 3 more than a decade ago does not 
fully work, because it does not filter out the unsigned condition codes (the 
instruction is an UNSPEC that accepts only signed condition codes).

While I was at it, I also added the missing vcond and vcondu expanders for the 
new comparison instructions that were added in VIS 4.

Tested on SPARC/Solaris, applied on the mainline, 12 and 11 branches.


2023-03-28  Eric Botcazou  <ebotcazou@adacore.com>

	PR target/109140
	* config/sparc/sparc.cc (sparc_expand_vcond): Call signed_condition
	on operand #3 to get the final condition code.  Use std::swap.
	* config/sparc/sparc.md (vcondv8qiv8qi): New VIS 4 expander.
	(fucmp<gcond:code>8<P:mode>_vis): Move around.
	(fpcmpu<gcond:code><GCM:gcm_name><P:mode>_vis): Likewise.
	(vcondu<GCM:mode><GCM:mode>): New VIS 4 expander.


2023-03-28  Eric Botcazou  <ebotcazou@adacore.com>

	* gcc.target/sparc/20230328-1.c: New test.
	* gcc.target/sparc/20230328-2.c: Likewise.
	* gcc.target/sparc/20230328-3.c: Likewise.
	* gcc.target/sparc/20230328-4.c: Likewise.
diff mbox series

Patch

diff --git a/gcc/config/sparc/sparc.cc b/gcc/config/sparc/sparc.cc
index 644ff9cf594..8c0c9dce971 100644
--- a/gcc/config/sparc/sparc.cc
+++ b/gcc/config/sparc/sparc.cc
@@ -13662,18 +13662,16 @@  sparc_expand_conditional_move (machine_mode mode, rtx *operands)
 void
 sparc_expand_vcond (machine_mode mode, rtx *operands, int ccode, int fcode)
 {
+  enum rtx_code code = signed_condition (GET_CODE (operands[3]));
   rtx mask, cop0, cop1, fcmp, cmask, bshuf, gsr;
-  enum rtx_code code = GET_CODE (operands[3]);
 
   mask = gen_reg_rtx (Pmode);
   cop0 = operands[4];
   cop1 = operands[5];
   if (code == LT || code == GE)
     {
-      rtx t;
-
       code = swap_condition (code);
-      t = cop0; cop0 = cop1; cop1 = t;
+      std::swap (cop0, cop1);
     }
 
   gsr = gen_rtx_REG (DImode, SPARC_GSR_REG);
diff --git a/gcc/config/sparc/sparc.md b/gcc/config/sparc/sparc.md
index 417b588e610..94779c16c63 100644
--- a/gcc/config/sparc/sparc.md
+++ b/gcc/config/sparc/sparc.md
@@ -9033,6 +9033,50 @@  visl")
   DONE;
 })
 
+(define_expand "vcondv8qiv8qi"
+  [(match_operand:V8QI 0 "register_operand" "")
+   (match_operand:V8QI 1 "register_operand" "")
+   (match_operand:V8QI 2 "register_operand" "")
+   (match_operator 3 ""
+     [(match_operand:V8QI 4 "register_operand" "")
+      (match_operand:V8QI 5 "register_operand" "")])]
+  "TARGET_VIS4"
+{
+  sparc_expand_vcond (V8QImode, operands, UNSPEC_CMASK8, UNSPEC_FCMP);
+  DONE;
+})
+
+(define_insn "fucmp<gcond:code>8<P:mode>_vis"
+  [(set (match_operand:P 0 "register_operand" "=r")
+	(unspec:P [(gcond:V8QI (match_operand:V8QI 1 "register_operand" "e")
+		               (match_operand:V8QI 2 "register_operand" "e"))]
+	 UNSPEC_FUCMP))]
+  "TARGET_VIS3"
+  "fucmp<gcond:code>8\t%1, %2, %0"
+  [(set_attr "type" "viscmp")])
+
+(define_insn "fpcmpu<gcond:code><GCM:gcm_name><P:mode>_vis"
+  [(set (match_operand:P 0 "register_operand" "=r")
+	(unspec:P [(gcond:GCM (match_operand:GCM 1 "register_operand" "e")
+		              (match_operand:GCM 2 "register_operand" "e"))]
+	 UNSPEC_FUCMP))]
+  "TARGET_VIS4"
+  "fpcmpu<gcond:code><GCM:gcm_name>\t%1, %2, %0"
+  [(set_attr "type" "viscmp")])
+
+(define_expand "vcondu<GCM:mode><GCM:mode>"
+  [(match_operand:GCM 0 "register_operand" "")
+   (match_operand:GCM 1 "register_operand" "")
+   (match_operand:GCM 2 "register_operand" "")
+   (match_operator 3 ""
+     [(match_operand:GCM 4 "register_operand" "")
+      (match_operand:GCM 5 "register_operand" "")])]
+  "TARGET_VIS4"
+{
+  sparc_expand_vcond (<MODE>mode, operands, UNSPEC_CMASK<gcm_name>, UNSPEC_FUCMP);
+  DONE;
+})
+
 (define_expand "vconduv8qiv8qi"
   [(match_operand:V8QI 0 "register_operand" "")
    (match_operand:V8QI 1 "register_operand" "")
@@ -9351,24 +9395,6 @@  visl")
  [(set_attr "type" "fga")
   (set_attr "subtype" "other")])
 
-(define_insn "fucmp<gcond:code>8<P:mode>_vis"
-  [(set (match_operand:P 0 "register_operand" "=r")
-	(unspec:P [(gcond:V8QI (match_operand:V8QI 1 "register_operand" "e")
-		               (match_operand:V8QI 2 "register_operand" "e"))]
-	 UNSPEC_FUCMP))]
-  "TARGET_VIS3"
-  "fucmp<gcond:code>8\t%1, %2, %0"
-  [(set_attr "type" "viscmp")])
-
-(define_insn "fpcmpu<gcond:code><GCM:gcm_name><P:mode>_vis"
-  [(set (match_operand:P 0 "register_operand" "=r")
-	(unspec:P [(gcond:GCM (match_operand:GCM 1 "register_operand" "e")
-		              (match_operand:GCM 2 "register_operand" "e"))]
-	 UNSPEC_FUCMP))]
-  "TARGET_VIS4"
-  "fpcmpu<gcond:code><GCM:gcm_name>\t%1, %2, %0"
-  [(set_attr "type" "viscmp")])
-
 (define_insn "*naddsf3"
   [(set (match_operand:SF 0 "register_operand" "=f")
         (neg:SF (plus:SF (match_operand:SF 1 "register_operand" "f")