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[2620:52:3:1:0:246e:9693:128c]) by mx.google.com with ESMTPS id gw19-20020a170906f15300b00982b37dd005si4700660ejb.865.2023.06.19.01.35.57 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Jun 2023 01:35:58 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) client-ip=2620:52:3:1:0:246e:9693:128c; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@oss.cipunited.com header.s=feishu2303200042 header.b=n3VSYmDF; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org" Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 4BBAC388301C for ; Mon, 19 Jun 2023 08:33:23 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from s01.bc.larksuite.com (s01.bc.larksuite.com [209.127.230.19]) by sourceware.org (Postfix) with UTF8SMTPS id 5A01B385772B for ; Mon, 19 Jun 2023 08:31:59 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 5A01B385772B Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=oss.cipunited.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=oss.cipunited.com DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; s=feishu2303200042; d=oss.cipunited.com; t=1687163513; h=from:subject:mime-version:from:date:message-id:subject:to:cc: reply-to:content-type:mime-version:in-reply-to:message-id; bh=jzsD59mCggVoJVRc2Pa5Txieu1gPH+4oCt/l0oc6xvA=; b=n3VSYmDF7r4Fy9ws0qSj2EhjO7O+eGxlGOGFLplbw4077xBiFvfVyYFSSknf47mgiBG5cP JwdUmWfLrPqUQ22qwE7P1iDRQ+Sv6zimwVQWNgmFIZGLRCIt7KdtXG+UcQydhlg8Zixpst 1SCYL3x6Yzqs6OJCJZbEKB0lw2vs+2Xa5A3sdk2YWb2TooCH0hT2fz64NCHQ9tXQ53UVMJ 1Djf0mmW3SCmJtz43GW5tI4LOgQlMfoyp1eLZcO+geqB6JuVlTVHHn3g1dBxFsxrOGkzdM lBwxX8o4ghB38nZ+dlhFxJvTOKIrzf3ly5o40tuaV0J0qzpmsoyAFOR/X6V3zA== To: Mime-Version: 1.0 Date: Mon, 19 Jun 2023 16:29:55 +0800 References: Subject: [PATCH v4 6/9] MIPS: Add load/store word left/right instructions for mips16e2 X-Mailer: git-send-email 2.40.1 Message-Id: <7d133575663a34329b415d1790389b537b9ad2e1.1687162620.git.jie.mei@oss.cipunited.com> X-Lms-Return-Path: In-Reply-To: Cc: "YunQiang Su" , "Maciej W . Rozycki" From: "Jie Mei" X-Spam-Status: No, score=-12.5 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, GIT_PATCH_0, HTML_MESSAGE, KAM_NUMSUBJECT, KAM_SHORT, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-Content-Filtered-By: Mailman/MimeDel 2.1.29 X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1769119424583443312?= X-GMAIL-MSGID: =?utf-8?q?1769119424583443312?= This patch adds LWL/LWR, SWL/SWR instructions with their corresponding tests. gcc/ChangeLog: * config/mips/mips.cc(mips_expand_ins_as_unaligned_store): Add logics for generating instruction. * config/mips/mips.h(ISA_HAS_LWL_LWR): Add clause for ISA_HAS_MIPS16E2. * config/mips/mips.md(mov_l): Generates instructions. (mov_r): Same as above. (mov_l): Adjusted for the conditions above. (mov_r): Same as above. (mov_l_mips16e2): Add machine description for `define_insn mov_l_mips16e2`. (mov_r_mips16e2): Add machine description for `define_insn mov_r_mips16e2`. gcc/testsuite/ChangeLog: * gcc.target/mips/mips16e2.c: New tests for mips16e2. --- gcc/config/mips/mips.cc | 15 ++- gcc/config/mips/mips.h | 3 +- gcc/config/mips/mips.md | 43 +++++++-- gcc/testsuite/gcc.target/mips/mips16e2.c | 116 +++++++++++++++++++++++ 4 files changed, 169 insertions(+), 8 deletions(-) diff --git a/gcc/config/mips/mips.cc b/gcc/config/mips/mips.cc index cdc04bec217..124a82b6a46 100644 --- a/gcc/config/mips/mips.cc +++ b/gcc/config/mips/mips.cc @@ -8603,12 +8603,25 @@ mips_expand_ins_as_unaligned_store (rtx dest, rtx src, HOST_WIDE_INT width, return false; mode = int_mode_for_size (width, 0).require (); - src = gen_lowpart (mode, src); + if (TARGET_MIPS16 + && src == const0_rtx) + src = force_reg (mode, src); + else + src = gen_lowpart (mode, src); + if (mode == DImode) { + if (TARGET_MIPS16) + gcc_unreachable (); emit_insn (gen_mov_sdl (dest, src, left)); emit_insn (gen_mov_sdr (copy_rtx (dest), copy_rtx (src), right)); } + else if (TARGET_MIPS16) + { + emit_insn (gen_mov_swl_mips16e2 (dest, src, left)); + emit_insn (gen_mov_swr_mips16e2 (copy_rtx (dest), copy_rtx (src), + right)); + } else { emit_insn (gen_mov_swl (dest, src, left)); diff --git a/gcc/config/mips/mips.h b/gcc/config/mips/mips.h index eefe2aa0910..e09a6c60157 100644 --- a/gcc/config/mips/mips.h +++ b/gcc/config/mips/mips.h @@ -1180,7 +1180,8 @@ struct mips_cpu_info { && (MODE) == V2SFmode)) \ && !TARGET_MIPS16) -#define ISA_HAS_LWL_LWR (mips_isa_rev <= 5 && !TARGET_MIPS16) +#define ISA_HAS_LWL_LWR (mips_isa_rev <= 5 \ + && (!TARGET_MIPS16 || ISA_HAS_MIPS16E2)) #define ISA_HAS_IEEE_754_LEGACY (mips_isa_rev <= 5) diff --git a/gcc/config/mips/mips.md b/gcc/config/mips/mips.md index b2ab23dc931..a0c1ea8e762 100644 --- a/gcc/config/mips/mips.md +++ b/gcc/config/mips/mips.md @@ -4488,10 +4488,12 @@ (unspec:GPR [(match_operand:BLK 1 "memory_operand" "m") (match_operand:QI 2 "memory_operand" "ZC")] UNSPEC_LOAD_LEFT))] - "!TARGET_MIPS16 && mips_mem_fits_mode_p (mode, operands[1])" + "(!TARGET_MIPS16 || ISA_HAS_MIPS16E2) + && mips_mem_fits_mode_p (mode, operands[1])" "l\t%0,%2" [(set_attr "move_type" "load") - (set_attr "mode" "")]) + (set_attr "mode" "") + (set_attr "extended_mips16" "yes")]) (define_insn "mov_r" [(set (match_operand:GPR 0 "register_operand" "=d") @@ -4499,17 +4501,20 @@ (match_operand:QI 2 "memory_operand" "ZC") (match_operand:GPR 3 "register_operand" "0")] UNSPEC_LOAD_RIGHT))] - "!TARGET_MIPS16 && mips_mem_fits_mode_p (mode, operands[1])" + "(!TARGET_MIPS16 || ISA_HAS_MIPS16E2) + && mips_mem_fits_mode_p (mode, operands[1])" "r\t%0,%2" [(set_attr "move_type" "load") - (set_attr "mode" "")]) + (set_attr "mode" "") + (set_attr "extended_mips16" "yes")]) (define_insn "mov_l" [(set (match_operand:BLK 0 "memory_operand" "=m") (unspec:BLK [(match_operand:GPR 1 "reg_or_0_operand" "dJ") (match_operand:QI 2 "memory_operand" "ZC")] UNSPEC_STORE_LEFT))] - "!TARGET_MIPS16 && mips_mem_fits_mode_p (mode, operands[0])" + "!TARGET_MIPS16 + && mips_mem_fits_mode_p (mode, operands[0])" "l\t%z1,%2" [(set_attr "move_type" "store") (set_attr "mode" "")]) @@ -4520,11 +4525,37 @@ (match_operand:QI 2 "memory_operand" "ZC") (match_dup 0)] UNSPEC_STORE_RIGHT))] - "!TARGET_MIPS16 && mips_mem_fits_mode_p (mode, operands[0])" + "!TARGET_MIPS16 + && mips_mem_fits_mode_p (mode, operands[0])" "r\t%z1,%2" [(set_attr "move_type" "store") (set_attr "mode" "")]) +(define_insn "mov_l_mips16e2" + [(set (match_operand:BLK 0 "memory_operand" "=m") + (unspec:BLK [(match_operand:GPR 1 "register_operand" "d") + (match_operand:QI 2 "memory_operand" "ZC")] + UNSPEC_STORE_LEFT))] + "TARGET_MIPS16 && ISA_HAS_MIPS16E2 + && mips_mem_fits_mode_p (mode, operands[0])" + "l\t%1,%2" + [(set_attr "move_type" "store") + (set_attr "mode" "") + (set_attr "extended_mips16" "yes")]) + +(define_insn "mov_r_mips16e2" + [(set (match_operand:BLK 0 "memory_operand" "+m") + (unspec:BLK [(match_operand:GPR 1 "register_operand" "d") + (match_operand:QI 2 "memory_operand" "ZC") + (match_dup 0)] + UNSPEC_STORE_RIGHT))] + "TARGET_MIPS16 && ISA_HAS_MIPS16E2 + && mips_mem_fits_mode_p (mode, operands[0])" + "r\t%1,%2" + [(set_attr "move_type" "store") + (set_attr "mode" "") + (set_attr "extended_mips16" "yes")]) + ;; Unaligned direct access (define_expand "movmisalign" [(set (match_operand:JOIN_MODE 0) diff --git a/gcc/testsuite/gcc.target/mips/mips16e2.c b/gcc/testsuite/gcc.target/mips/mips16e2.c index 780891b4056..166aa742268 100644 --- a/gcc/testsuite/gcc.target/mips/mips16e2.c +++ b/gcc/testsuite/gcc.target/mips/mips16e2.c @@ -122,3 +122,119 @@ test10 (int i) return i; } +/* Test 32bit unaligned load. */ + +/* { dg-final { scan-assembler "test11:.*\tlwl\t.*test11\n" } } */ +/* { dg-final { scan-assembler "test11:.*\tlwr\t.*test11\n" } } */ +struct node11 +{ + char c; + int i; +} __attribute__ ((packed)) obj11 __attribute__((aligned(1))); + +int +test11 (void) +{ + return obj11.i; +} + +/* Test 32bit unaligned load. */ + +/* { dg-final { scan-assembler "test12:.*\tlwl\t.*test12\n" } } */ +/* { dg-final { scan-assembler "test12:.*\tlwr\t.*test12\n" } } */ +struct node12 +{ + unsigned int i : 8; + unsigned int j : 32; +} __attribute__ ((packed)) obj12 __attribute__((aligned(16))); + +int +test12 (void) +{ + return obj12.j; +} + +/* Test 32bit unaligned store with non-zero constant */ + +/* { dg-final { scan-assembler "test13:.*\tswl\t.*test13\n" } } */ +/* { dg-final { scan-assembler "test13:.*\tswr\t.*test13\n" } } */ +struct node13 +{ + char c; + int i; +} __attribute__ ((packed)) obj13 __attribute__((aligned(1))); + +void +test13 (void) +{ + obj13.i = 1234; +} + +/* Test 32bit unaligned store with zero constant. */ + +/* { dg-final { scan-assembler "test14:.*\tswl\t.*test14\n" } } */ +/* { dg-final { scan-assembler "test14:.*\tswr\t.*test14\n" } } */ +/* { dg-final { scan-assembler-not "test14:.*\tswl\t\\\$0,.*test14\n" } } */ +/* { dg-final { scan-assembler-not "test14:.*\tswr\t\\\$0,.*test14\n" } } */ +struct node14 +{ + char c; + int i; +} __attribute__ ((packed)) obj14 __attribute__((aligned(1))); + +void +test14 (void) +{ + obj14.i = 0; +} + +/* Test 32bit unaligned store with non-constant. */ + +/* { dg-final { scan-assembler "test15:.*\tswl\t.*test15\n" } } */ +/* { dg-final { scan-assembler "test15:.*\tswr\t.*test15\n" } } */ +struct node15 +{ + char c; + int i; +} __attribute__ ((packed)) obj15 __attribute__((aligned(1))); + +int i15 = 1234; + +void +test15 (void) +{ + obj15.i = i15; +} + +/* Test 32bit unaligned store with non-constant */ + +/* { dg-final { scan-assembler "test16:.*\tswl\t.*test16\n" } } */ +/* { dg-final { scan-assembler "test16:.*\tswr\t.*test16\n" } } */ +struct node16 +{ + char c; + int i; +} __attribute__ ((packed)) obj16 __attribute__((aligned(1))); + +void +test16 (int i) +{ + obj16.i = i; +} + +/* Test 32bit unaligned store with non-constant. */ + +/* { dg-final { scan-assembler "test17:.*\tswl\t.*test17\n" } } */ +/* { dg-final { scan-assembler "test17:.*\tswr\t.*test17\n" } } */ +struct node17 +{ + unsigned int i : 8; + unsigned int j : 32; +} __attribute__ ((packed)) obj17 __attribute__((aligned(16))); + +void +test17 (int i) +{ + obj17.j = i; +} +