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[2620:52:3:1:0:246e:9693:128c]) by mx.google.com with ESMTPS id md5-20020a170906ae8500b009885c5f1d7asi4551951ejb.319.2023.08.11.19.59.23 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 11 Aug 2023 19:59:23 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) client-ip=2620:52:3:1:0:246e:9693:128c; Authentication-Results: mx.google.com; dkim=pass header.i=@gcc.gnu.org header.s=default header.b=RMKcOH2L; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=gnu.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id CEBF1385624C for ; Sat, 12 Aug 2023 02:58:51 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org CEBF1385624C DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1691809131; bh=6CJE5F2LwLHhtJh+S4mj8HYBf+xqnkRLH+yMpRK9yno=; h=To:Cc:Subject:Date:In-Reply-To:References:List-Id: List-Unsubscribe:List-Archive:List-Post:List-Help:List-Subscribe: From:Reply-To:From; b=RMKcOH2LW7BuTWIcy90lmH/muSlGRmeqtpRJil9mif9m7DlkKqs83C/VJExtqW2Fq 5JjYUBEjgUxvoZBxaiW2jALKPfcuy/31HR9mFRD5IDYZHPvuwZqGNuGF5IfNdSQtsn ZoHhwO0pfXDWc9kNurYDGpSTur9T8cCt6TXzAF2g= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mail-sender-0.a4lg.com (mail-sender-0.a4lg.com [IPv6:2401:2500:203:30b:4000:6bfe:4757:0]) by sourceware.org (Postfix) with ESMTPS id CF5143857721 for ; Sat, 12 Aug 2023 02:58:06 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org CF5143857721 Received: from [127.0.0.1] (localhost [127.0.0.1]) by mail-sender-0.a4lg.com (Postfix) with ESMTPSA id 10286300089; Sat, 12 Aug 2023 02:58:05 +0000 (UTC) To: Tsukasa OI , Kito Cheng , Palmer Dabbelt , Andrew Waterman , Jim Wilson , Jeff Law Cc: gcc-patches@gcc.gnu.org Subject: [PATCH 3/3] RISC-V: Add stub support for existing extensions (unprivileged) Date: Sat, 12 Aug 2023 02:57:20 +0000 Message-ID: <6d0c9d647ac7d1e0df6d419e849f631373344802.1691809036.git.research_trasio@irq.a4lg.com> In-Reply-To: References: Mime-Version: 1.0 X-Spam-Status: No, score=-12.0 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, GIT_PATCH_0, KAM_MANYTO, KAM_SHORT, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Tsukasa OI via Gcc-patches From: Tsukasa OI Reply-To: Tsukasa OI Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1773990485352556806 X-GMAIL-MSGID: 1773990485352556806 From: Tsukasa OI After commit c283c4774d1c ("RISC-V: Throw compilation error for unknown extensions") changed how do we handle unknown extensions, we have no guarantee that we can share the same architectural string with Binutils (specifically, the assembler). To avoid compilation errors on shared Assembler-C/C++ projects, GCC should support almost all extensions that Binutils support, even if the GCC does not touch a thing. This commit adds stub supported standard unprivileged extensions to riscv_ext_version_table and its implications to riscv_implied_info (all information is copied from Binutils' bfd/elfxx-riscv.c except not yet merged 'Zce', 'Zcmp' and 'Zcmt' support). gcc/ChangeLog: * common/config/riscv/riscv-common.cc (riscv_implied_info): Add implications from unprivileged extensions. (riscv_ext_version_table): Add stub support for all unprivileged extensions supported by Binutils as well as 'Zce', 'Zcmp', 'Zcmt'. gcc/testsuite/ChangeLog: * gcc.target/riscv/predef-31.c: New test for a stub unprivileged extension 'Zcb' with some implications. --- gcc/common/config/riscv/riscv-common.cc | 25 +++++++++++++++++ gcc/testsuite/gcc.target/riscv/predef-31.c | 31 ++++++++++++++++++++++ 2 files changed, 56 insertions(+) create mode 100644 gcc/testsuite/gcc.target/riscv/predef-31.c diff --git a/gcc/common/config/riscv/riscv-common.cc b/gcc/common/config/riscv/riscv-common.cc index 0c351105e015..112bb86bd675 100644 --- a/gcc/common/config/riscv/riscv-common.cc +++ b/gcc/common/config/riscv/riscv-common.cc @@ -105,6 +105,7 @@ static const riscv_implied_info_t riscv_implied_info[] = {"zvl65536b", "zvl32768b"}, {"zvkn", "zvkned"}, + {"zvkn", "zvknha"}, {"zvkn", "zvknhb"}, {"zvkn", "zvbb"}, {"zvkn", "zvkt"}, @@ -121,6 +122,19 @@ static const riscv_implied_info_t riscv_implied_info[] = {"zvksg", "zvks"}, {"zvksg", "zvkg"}, + {"zcb", "zca"}, + {"zcd", "zca"}, + {"zcd", "d"}, + {"zcf", "zca"}, + {"zcf", "f"}, + {"zce", "zca"}, + {"zce", "zcb"}, + {"zce", "zcmp"}, + {"zce", "zcmt"}, + {"zcmp", "zca"}, + {"zcmt", "zca"}, + {"zcmt", "zcicsr"}, + {"zfh", "zfhmin"}, {"zfhmin", "f"}, {"zvfhmin", "zve32f"}, @@ -197,6 +211,14 @@ static const struct riscv_ext_version riscv_ext_version_table[] = {"zawrs", ISA_SPEC_CLASS_NONE, 1, 0}, + {"zca", ISA_SPEC_CLASS_NONE, 1, 0}, + {"zcb", ISA_SPEC_CLASS_NONE, 1, 0}, + {"zce", ISA_SPEC_CLASS_NONE, 1, 0}, + {"zcmp", ISA_SPEC_CLASS_NONE, 1, 0}, + {"zcmt", ISA_SPEC_CLASS_NONE, 1, 0}, + {"zcd", ISA_SPEC_CLASS_NONE, 1, 0}, + {"zcf", ISA_SPEC_CLASS_NONE, 1, 0}, + {"zba", ISA_SPEC_CLASS_NONE, 1, 0}, {"zbb", ISA_SPEC_CLASS_NONE, 1, 0}, {"zbc", ISA_SPEC_CLASS_NONE, 1, 0}, @@ -219,6 +241,7 @@ static const struct riscv_ext_version riscv_ext_version_table[] = {"zkt", ISA_SPEC_CLASS_NONE, 1, 0}, {"zihintntl", ISA_SPEC_CLASS_NONE, 1, 0}, + {"zihintpause", ISA_SPEC_CLASS_NONE, 2, 0}, {"zicboz",ISA_SPEC_CLASS_NONE, 1, 0}, {"zicbom",ISA_SPEC_CLASS_NONE, 1, 0}, @@ -265,6 +288,8 @@ static const struct riscv_ext_version riscv_ext_version_table[] = {"zvl32768b", ISA_SPEC_CLASS_NONE, 1, 0}, {"zvl65536b", ISA_SPEC_CLASS_NONE, 1, 0}, + {"zfa", ISA_SPEC_CLASS_NONE, 0, 1}, + {"zfh", ISA_SPEC_CLASS_NONE, 1, 0}, {"zfhmin", ISA_SPEC_CLASS_NONE, 1, 0}, {"zvfhmin", ISA_SPEC_CLASS_NONE, 1, 0}, diff --git a/gcc/testsuite/gcc.target/riscv/predef-31.c b/gcc/testsuite/gcc.target/riscv/predef-31.c new file mode 100644 index 000000000000..4ea11442f995 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/predef-31.c @@ -0,0 +1,31 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64i_zcb -mabi=lp64 -mcmodel=medlow -misa-spec=20191213" } */ + +int main () { + +#ifndef __riscv_arch_test +#error "__riscv_arch_test" +#endif + +#if __riscv_xlen != 64 +#error "__riscv_xlen" +#endif + +#if !defined(__riscv_i) || (__riscv_i != (2 * 1000 * 1000 + 1 * 1000)) +#error "__riscv_i" +#endif + +#if defined(__riscv_e) +#error "__riscv_e" +#endif + +#if !defined(__riscv_zca) +#error "__riscv_zca" +#endif + +#if !defined(__riscv_zcb) +#error "__riscv_zcb" +#endif + + return 0; +}