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[8.43.85.97]) by mx.google.com with ESMTPS id om29-20020a0562143d9d00b0065b31ba68acsi5407785qvb.339.2023.10.23.00.25.04 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 23 Oct 2023 00:25:04 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) client-ip=8.43.85.97; Authentication-Results: mx.google.com; dkim=pass header.i=@irq.a4lg.com header.s=2017s01 header.b=FjhUB2rE; arc=pass (i=1); spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=irq.a4lg.com Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id ABE983875457 for ; Mon, 23 Oct 2023 07:24:47 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mail-sender-0.a4lg.com (mail-sender.a4lg.com [153.120.152.154]) by sourceware.org (Postfix) with ESMTPS id C228B385E020 for ; Mon, 23 Oct 2023 07:24:23 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org C228B385E020 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=irq.a4lg.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=irq.a4lg.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org C228B385E020 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=153.120.152.154 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1698045865; cv=none; b=o47AGsNqv24M7GAddub1gQeBlgTrPbSuKrXv+2HNIOWul+RvrqZPsquAEj3FWNkgDBYZXGk2i3zK/OBtBUgpbdkrAR5Wqj5t/8BqrBJ8/YCfJy1NLictJLth2whQgrAwfbFQoXb1FUPUKy8j7/puSa34id8pmTYBomk7r7o9rIA= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1698045865; c=relaxed/simple; bh=FoFthWH66TuicDgVWRSVQzgwSIoneQLcV8pL1ymhZl4=; h=DKIM-Signature:From:To:Subject:Date:Message-ID:Mime-Version; b=cpGeVLMdVpxPnzN+2XTWUo9TFxinZ1pkIlA5ytARaO+BxkmdwHzKeQzZjyYKtgDrVZDNDo9PefIC5RIMuRxkLdli+3ncffu43bD7QIIzC/kpO7z3WbXXr0fVHpFxxGPa4gtNG1XX9JLTFszJjWY/6Gs8G2KUQHvX8uW0Gqs9PM4= ARC-Authentication-Results: i=1; server2.sourceware.org Received: from [127.0.0.1] (localhost [127.0.0.1]) by mail-sender-0.a4lg.com (Postfix) with ESMTPSA id C79DF300089; Mon, 23 Oct 2023 07:24:21 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=irq.a4lg.com; s=2017s01; t=1698045862; bh=baZMWkKRMJpeNY03YCW/twmY2XfmpZXdY8XXe8UKWZE=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: Mime-Version:Content-Transfer-Encoding; b=FjhUB2rE7OE5pgyI61ngIlJSwxOzcjppYBT/rA4AmS29O2RcWcnOjwy2RlCmunp7K 90EFpahyPsxhYlCP6Sn0Y/sSEnikOWSaTfdBtiR/AWER+lT5+TYK2vee6pFe/oJyMo BXlaJ2dUMsbQT85rXUMzjYQCoqV+L6qOu3S+19d0= From: Tsukasa OI To: Tsukasa OI , Kito Cheng , Palmer Dabbelt , Andrew Waterman , Jim Wilson , Jeff Law Cc: gcc-patches@gcc.gnu.org Subject: [PATCH 3/4] RISC-V: Add not broken RW prefetch RTL instructions without offsets Date: Mon, 23 Oct 2023 07:22:54 +0000 Message-ID: <671a5e3bc2ca33b9050c54d2f53dd0580339b858.1698045769.git.research_trasio@irq.a4lg.com> In-Reply-To: References: Mime-Version: 1.0 X-Spam-Status: No, score=-11.9 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, GIT_PATCH_0, KAM_MANYTO, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1780530181813618974 X-GMAIL-MSGID: 1780530181813618974 From: Tsukasa OI To prepare adding new not broken prefetch built-in functions and fixing an ICE in __builtin_prefetch, this commit adds two new instructions, each corresponding a 'Zicbop' prefetch hint instruction, but with no specifiable offset field for simplicity. This commit also excludes new instruction corresponding "prefetch.i" because it is not needed to fix an ICE (so new instruction corresponding "prefetch.i" is going to be a separate commit). gcc/ChangeLog: * config/riscv/riscv.md (unspecv) Add UNSPECV_PREFETCH_[RW]. (riscv_prefetch_w_, riscv_prefetch_w_): New. --- gcc/config/riscv/riscv.md | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md index 4b445cb8be9c..e67a6d1f1b81 100644 --- a/gcc/config/riscv/riscv.md +++ b/gcc/config/riscv/riscv.md @@ -118,6 +118,8 @@ UNSPECV_FLUSH UNSPECV_INVAL UNSPECV_ZERO + UNSPECV_PREFETCH_R + UNSPECV_PREFETCH_W ;; Zihintpause unspec UNSPECV_PAUSE @@ -3492,6 +3494,20 @@ } [(set_attr "type" "cbo")]) +(define_insn "riscv_prefetch_r_" + [(unspec_volatile:X [(match_operand:X 0 "register_operand" "r")] + UNSPECV_PREFETCH_R)] + "TARGET_ZICBOP" + "prefetch.r\t0(%0)" + [(set_attr "type" "cbo")]) + +(define_insn "riscv_prefetch_w_" + [(unspec_volatile:X [(match_operand:X 0 "register_operand" "r")] + UNSPECV_PREFETCH_W)] + "TARGET_ZICBOP" + "prefetch.w\t0(%0)" + [(set_attr "type" "cbo")]) + (define_expand "extv" [(set (match_operand:GPR 0 "register_operand" "=r") (sign_extract:GPR (match_operand:GPR 1 "register_operand" "r")