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[2620:52:3:1:0:246e:9693:128c]) by mx.google.com with ESMTPS id c5-20020aa7c745000000b0051a59360fdbsi1011758eds.514.2023.06.19.01.35.40 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Jun 2023 01:35:42 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) client-ip=2620:52:3:1:0:246e:9693:128c; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@oss.cipunited.com header.s=feishu2303200042 header.b="uBMdf/Xe"; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org" Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id CDCDB3854E59 for ; Mon, 19 Jun 2023 08:33:17 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from t03.bc.larksuite.com (t03.bc.larksuite.com [209.127.231.31]) by sourceware.org (Postfix) with UTF8SMTPS id 37C6A3858D32 for ; Mon, 19 Jun 2023 08:32:13 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 37C6A3858D32 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=oss.cipunited.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=oss.cipunited.com DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; s=feishu2303200042; d=oss.cipunited.com; t=1687163529; h=from:subject:mime-version:from:date:message-id:subject:to:cc: reply-to:content-type:mime-version:in-reply-to:message-id; bh=dpxVu+PaiiVlZWpzchxfqeSIvCPynHEUqHtQeH3JaKs=; b=uBMdf/XeLG2tiZcJ5av1jTnn7GHZTbmFmMisWmOt16XGj7TWfeYUizPS8sDvPIxa/9x5yj yTkAIzDaVFp0RPzpdnze0wxoqB9Vyu+djolHqpNxkMeusx2nMhWCBbzgMMmnJ6jmilGH1K fJ/buvmG1WEFYXqxfR4UOK8SkDf5jVvZZRi20NO7LjYgJL2zxx26KHrITd2hYijf2FB2RN zx+1ovwLXLfFBlkFkIzOBVBZIY3jmU0Kthike+Rx5QeqJ2dDq1vXvIVkGXONytTHSeLKc+ tG7BunLglUamnNdVv0OwhKimUUipKwmbG2Ncukp5ALivyZS2c0mVRuKsuduyfA== Subject: [PATCH v4 9/9] MIPS: Make mips16e2 generating ZEB/ZEH instead of ANDI under certain conditions X-Mailer: git-send-email 2.40.1 In-Reply-To: Cc: "YunQiang Su" , "Maciej W . Rozycki" X-Lms-Return-Path: Mime-Version: 1.0 Date: Mon, 19 Jun 2023 16:29:58 +0800 From: "Jie Mei" Message-Id: <647bd72134fcf571ec40ddcb0f42997d88d0979b.1687162620.git.jie.mei@oss.cipunited.com> References: To: X-Spam-Status: No, score=-12.6 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, GIT_PATCH_0, HTML_MESSAGE, HTML_NONELEMENT_30_40, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-Content-Filtered-By: Mailman/MimeDel 2.1.29 X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1769119408633004430?= X-GMAIL-MSGID: =?utf-8?q?1769119408633004430?= This patch allows mips16e2 acts the same with -O1~3 when generating ZEB/ZEH instead of ANDI under the -O0 option, which shrinks the code size. gcc/ChangeLog: * config/mips/mips.md(*and3_mips16): Generates ZEB/ZEH instructions. --- gcc/config/mips/mips.md | 30 +++++++++++++++++------------- 1 file changed, 17 insertions(+), 13 deletions(-) diff --git a/gcc/config/mips/mips.md b/gcc/config/mips/mips.md index 8a8663a171f..e1beb84a287 100644 --- a/gcc/config/mips/mips.md +++ b/gcc/config/mips/mips.md @@ -3357,9 +3357,9 @@ (set_attr "mode" "")]) (define_insn "*and3_mips16" - [(set (match_operand:GPR 0 "register_operand" "=d,d,d,d,d,d,d,d") - (and:GPR (match_operand:GPR 1 "nonimmediate_operand" "%W,W,W,d,0,d,0,0?") - (match_operand:GPR 2 "and_operand" "Yb,Yh,Yw,Yw,d,Yx,Yz,K")))] + [(set (match_operand:GPR 0 "register_operand" "=d,d,d,d,d,d,d,d,d,d") + (and:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,0,W,W,W,d,0,d,0,0?") + (match_operand:GPR 2 "and_operand" "Yb,Yh,Yb,Yh,Yw,Yw,d,Yx,Yz,K")))] "TARGET_MIPS16 && and_operands_ok (mode, operands[1], operands[2])" { int len; @@ -3368,38 +3368,42 @@ switch (which_alternative) { case 0: + return "zeb\t%0"; + case 1: + return "zeh\t%0"; + case 2: operands[1] = gen_lowpart (QImode, operands[1]); return "lbu\t%0,%1"; - case 1: + case 3: operands[1] = gen_lowpart (HImode, operands[1]); return "lhu\t%0,%1"; - case 2: + case 4: operands[1] = gen_lowpart (SImode, operands[1]); return "lwu\t%0,%1"; - case 3: + case 5: return "#"; - case 4: + case 6: return "and\t%0,%2"; - case 5: + case 7: len = low_bitmask_len (mode, INTVAL (operands[2])); operands[2] = GEN_INT (len); return "ext\t%0,%1,0,%2"; - case 6: + case 8: mips_bit_clear_info (mode, INTVAL (operands[2]), &pos, &len); operands[1] = GEN_INT (pos); operands[2] = GEN_INT (len); return "ins\t%0,$0,%1,%2"; - case 7: + case 9: return "andi\t%0,%x2"; default: gcc_unreachable (); } } - [(set_attr "move_type" "load,load,load,shift_shift,logical,ext_ins,ext_ins,andi") + [(set_attr "move_type" "andi,andi,load,load,load,shift_shift,logical,ext_ins,ext_ins,andi") (set_attr "mode" "") - (set_attr "extended_mips16" "no,no,no,no,no,yes,yes,yes") + (set_attr "extended_mips16" "no,no,no,no,no,no,no,yes,yes,yes") (set (attr "enabled") - (cond [(and (eq_attr "alternative" "7") + (cond [(and (eq_attr "alternative" "9") (not (match_test "ISA_HAS_MIPS16E2"))) (const_string "no") (and (eq_attr "alternative" "0,1")