@@ -121,6 +121,7 @@ static const riscv_implied_info_t riscv_implied_info[] =
{"zvksg", "zvks"},
{"zvksg", "zvkg"},
+ {"zfa", "f"},
{"zfh", "zfhmin"},
{"zfhmin", "f"},
{"zvfhmin", "zve32f"},
@@ -257,6 +258,7 @@ static const struct riscv_ext_version riscv_ext_version_table[] =
{"zvl32768b", ISA_SPEC_CLASS_NONE, 1, 0},
{"zvl65536b", ISA_SPEC_CLASS_NONE, 1, 0},
+ {"zfa", ISA_SPEC_CLASS_NONE, 0, 1},
{"zfh", ISA_SPEC_CLASS_NONE, 1, 0},
{"zfhmin", ISA_SPEC_CLASS_NONE, 1, 0},
{"zvfhmin", ISA_SPEC_CLASS_NONE, 1, 0},
@@ -1400,6 +1402,7 @@ static const riscv_ext_flag_table_t riscv_ext_flag_table[] =
{"zvl32768b", &gcc_options::x_riscv_zvl_flags, MASK_ZVL32768B},
{"zvl65536b", &gcc_options::x_riscv_zvl_flags, MASK_ZVL65536B},
+ {"zfa", &gcc_options::x_riscv_zf_subext, MASK_ZFA},
{"zfhmin", &gcc_options::x_riscv_zf_subext, MASK_ZFHMIN},
{"zfh", &gcc_options::x_riscv_zf_subext, MASK_ZFH},
{"zvfhmin", &gcc_options::x_riscv_zf_subext, MASK_ZVFHMIN},
@@ -249,11 +249,13 @@ enum riscv_entity
#define MASK_ZFH (1 << 1)
#define MASK_ZVFHMIN (1 << 2)
#define MASK_ZVFH (1 << 3)
+#define MASK_ZFA (1 << 4)
#define TARGET_ZFHMIN ((riscv_zf_subext & MASK_ZFHMIN) != 0)
#define TARGET_ZFH ((riscv_zf_subext & MASK_ZFH) != 0)
#define TARGET_ZVFHMIN ((riscv_zf_subext & MASK_ZVFHMIN) != 0)
#define TARGET_ZVFH ((riscv_zf_subext & MASK_ZVFH) != 0)
+#define TARGET_ZFA ((riscv_zf_subext & MASK_ZFA) != 0)
#define MASK_ZMMUL (1 << 0)
#define TARGET_ZMMUL ((riscv_zm_subext & MASK_ZMMUL) != 0)