diff mbox series

RISC-V: Fix vmul test expectation.

Message ID 5c993a6a-d869-6d6f-2c7a-177f6d6af5c2@gmail.com
State Unresolved
Headers
Series RISC-V: Fix vmul test expectation. |

Checks

Context Check Description
snail/gcc-patch-check warning Git am fail log

Commit Message

Robin Dapp June 20, 2023, 7:58 a.m. UTC 
  Hi,

I forgot to check for vfmul in the multiplication tests.  Fix this.

Regards
 Robin

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/rvv/autovec/binop/vmul-rv32gcv.c: Check for
	vfmul.
	* gcc.target/riscv/rvv/autovec/binop/vmul-rv64gcv.c: Dito.
---
 gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmul-rv32gcv.c | 1 +
 gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmul-rv64gcv.c | 1 +
 2 files changed, 2 insertions(+)

Comments

juzhe.zhong@rivai.ai June 20, 2023, 8:12 a.m. UTC | #1 
Ok. No need to wait just commit.
Thanks.



juzhe.zhong@rivai.ai
 
From: Robin Dapp
Date: 2023-06-20 15:58
To: gcc-patches; palmer; Kito Cheng; juzhe.zhong@rivai.ai; jeffreyalaw
CC: rdapp.gcc
Subject: [PATCH] RISC-V: Fix vmul test expectation.
Hi,
 
I forgot to check for vfmul in the multiplication tests.  Fix this.
 
Regards
Robin
 
gcc/testsuite/ChangeLog:
 
* gcc.target/riscv/rvv/autovec/binop/vmul-rv32gcv.c: Check for
vfmul.
* gcc.target/riscv/rvv/autovec/binop/vmul-rv64gcv.c: Dito.
---
gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmul-rv32gcv.c | 1 +
gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmul-rv64gcv.c | 1 +
2 files changed, 2 insertions(+)
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmul-rv32gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmul-rv32gcv.c
index 1900c21121b..7d3dfade0ee 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmul-rv32gcv.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmul-rv32gcv.c
@@ -4,3 +4,4 @@
#include "vmul-template.h"
/* { dg-final { scan-assembler-times {\tvmul\.vv} 16 } } */
+/* { dg-final { scan-assembler-times {\tvfmul\.vv} 6 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmul-rv64gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmul-rv64gcv.c
index c8508bcc1f7..a549d6f7be4 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmul-rv64gcv.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmul-rv64gcv.c
@@ -4,3 +4,4 @@
#include "vmul-template.h"
/* { dg-final { scan-assembler-times {\tvmul\.vv} 16 } } */
+/* { dg-final { scan-assembler-times {\tvfmul\.vv} 6 } } */
-- 
2.40.1
Robin Dapp June 20, 2023, 12:35 p.m. UTC | #2 
I just noticed there is also a -ffast-math missing in vadd-run.c
as well as one redundant in vrem-rv32gcv.c and added it to the
patch.

Going to commit the attached as obvious.

Regards
 Robin

Subject: [PATCH] RISC-V: testsuite: Fix vmul test expectation and fix -ffast-math.

I forgot to check for vfmul in the multiplication tests as well as
some -ffast-math arguments.  Fix this.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/rvv/autovec/binop/vadd-run.c: Add
	-ffast-math.
	* gcc.target/riscv/rvv/autovec/binop/vadd-zvfh-run.c: Dito.
	* gcc.target/riscv/rvv/autovec/binop/vrem-rv32gcv.c: Remove
	-ffast-math
	* gcc.target/riscv/rvv/autovec/binop/vmul-rv32gcv.c: Check for
	vfmul.
	* gcc.target/riscv/rvv/autovec/binop/vmul-rv64gcv.c: Dito.
---
 gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-run.c     | 2 +-
 .../gcc.target/riscv/rvv/autovec/binop/vadd-zvfh-run.c          | 2 +-
 gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmul-rv32gcv.c | 1 +
 gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmul-rv64gcv.c | 1 +
 gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vrem-rv32gcv.c | 2 +-
 5 files changed, 5 insertions(+), 3 deletions(-)

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-run.c
index 5db0a3c79be..12fb952118e 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-run.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-run.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_vector } } } */
-/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax" } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */
 
 #include "vadd-template.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-zvfh-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-zvfh-run.c
index 1a11fe0fb30..30b467f50c7 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-zvfh-run.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-zvfh-run.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_vector && riscv_zvfh_hw } } } */
-/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax" } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */
 
 #include "vadd-template.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmul-rv32gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmul-rv32gcv.c
index 1900c21121b..7d3dfade0ee 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmul-rv32gcv.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmul-rv32gcv.c
@@ -4,3 +4,4 @@
 #include "vmul-template.h"
 
 /* { dg-final { scan-assembler-times {\tvmul\.vv} 16 } } */
+/* { dg-final { scan-assembler-times {\tvfmul\.vv} 6 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmul-rv64gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmul-rv64gcv.c
index c8508bcc1f7..a549d6f7be4 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmul-rv64gcv.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmul-rv64gcv.c
@@ -4,3 +4,4 @@
 #include "vmul-template.h"
 
 /* { dg-final { scan-assembler-times {\tvmul\.vv} 16 } } */
+/* { dg-final { scan-assembler-times {\tvfmul\.vv} 6 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vrem-rv32gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vrem-rv32gcv.c
index c6fe79e37b8..86607d03777 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vrem-rv32gcv.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vrem-rv32gcv.c
@@ -1,4 +1,4 @@
-/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax" } */
 
 #include "vrem-template.h"
diff mbox series

Patch

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmul-rv32gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmul-rv32gcv.c
index 1900c21121b..7d3dfade0ee 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmul-rv32gcv.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmul-rv32gcv.c
@@ -4,3 +4,4 @@ 
 #include "vmul-template.h"
 
 /* { dg-final { scan-assembler-times {\tvmul\.vv} 16 } } */
+/* { dg-final { scan-assembler-times {\tvfmul\.vv} 6 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmul-rv64gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmul-rv64gcv.c
index c8508bcc1f7..a549d6f7be4 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmul-rv64gcv.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmul-rv64gcv.c
@@ -4,3 +4,4 @@ 
 #include "vmul-template.h"
 
 /* { dg-final { scan-assembler-times {\tvmul\.vv} 16 } } */
+/* { dg-final { scan-assembler-times {\tvfmul\.vv} 6 } } */