[GCC] aarch64: Add support for Cortex-A715 CPU.
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Commit Message
Hi,
This patch adds support for Cortex-A715 CPU.
Bootstrapped on aarch64-none-linux-gnu and found no regressions.
Ok for GCC master?
Regards,
Srinath.
gcc/ChangeLog:
2022-11-09 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
* config/aarch64/aarch64-cores.def (AARCH64_CORE): Add Cortex-A715 CPU.
* config/aarch64/aarch64-tune.md: Regenerate.
* doc/gcc/gcc-command-options/machine-dependent-options/aarch64-options.rst:
Document Cortex-A715 CPU.
############### Attachment also inlined for ease of reply ###############
diff --git a/gcc/config/aarch64/aarch64-cores.def b/gcc/config/aarch64/aarch64-cores.def
index e9a4b622be018d92a790db10f4d5cf926bba512c..380bd8d90fdc7bddea2c8465522a30f938c2ffc5 100644
--- a/gcc/config/aarch64/aarch64-cores.def
+++ b/gcc/config/aarch64/aarch64-cores.def
@@ -167,6 +167,8 @@ AARCH64_CORE("cortex-a510", cortexa510, cortexa55, V9A, (SVE2_BITPERM, MEMTAG,
AARCH64_CORE("cortex-a710", cortexa710, cortexa57, V9A, (SVE2_BITPERM, MEMTAG, I8MM, BF16), neoversen2, 0x41, 0xd47, -1)
+AARCH64_CORE("cortex-a715", cortexa715, cortexa57, V9A, (SVE2_BITPERM, MEMTAG, I8MM, BF16), neoversen2, 0x41, 0xd4d, -1)
+
AARCH64_CORE("cortex-x2", cortexx2, cortexa57, V9A, (SVE2_BITPERM, MEMTAG, I8MM, BF16), neoversen2, 0x41, 0xd48, -1)
AARCH64_CORE("neoverse-n2", neoversen2, cortexa57, V9A, (I8MM, BF16, SVE2_BITPERM, RNG, MEMTAG, PROFILE), neoversen2, 0x41, 0xd49, -1)
diff --git a/gcc/config/aarch64/aarch64-tune.md b/gcc/config/aarch64/aarch64-tune.md
index 84e9bbf44f6222b3e5bcf4cbf8fab7ebf17015e1..f5b1482ba357d14f36e13ca3c4358865d4238e9a 100644
--- a/gcc/config/aarch64/aarch64-tune.md
+++ b/gcc/config/aarch64/aarch64-tune.md
@@ -1,5 +1,5 @@
;; -*- buffer-read-only: t -*-
;; Generated automatically by gentune.sh from aarch64-cores.def
(define_attr "tune"
- "cortexa34,cortexa35,cortexa53,cortexa57,cortexa72,cortexa73,thunderx,thunderxt88p1,thunderxt88,octeontx,octeontxt81,octeontxt83,thunderxt81,thunderxt83,ampere1,emag,xgene1,falkor,qdf24xx,exynosm1,phecda,thunderx2t99p1,vulcan,thunderx2t99,cortexa55,cortexa75,cortexa76,cortexa76ae,cortexa77,cortexa78,cortexa78ae,cortexa78c,cortexa65,cortexa65ae,cortexx1,ares,neoversen1,neoversee1,octeontx2,octeontx2t98,octeontx2t96,octeontx2t93,octeontx2f95,octeontx2f95n,octeontx2f95mm,a64fx,tsv110,thunderx3t110,zeus,neoversev1,neoverse512tvb,saphira,cortexa57cortexa53,cortexa72cortexa53,cortexa73cortexa35,cortexa73cortexa53,cortexa75cortexa55,cortexa76cortexa55,cortexr82,cortexa510,cortexa710,cortexx2,neoversen2,demeter,neoversev2"
+ "cortexa34,cortexa35,cortexa53,cortexa57,cortexa72,cortexa73,thunderx,thunderxt88p1,thunderxt88,octeontx,octeontxt81,octeontxt83,thunderxt81,thunderxt83,ampere1,emag,xgene1,falkor,qdf24xx,exynosm1,phecda,thunderx2t99p1,vulcan,thunderx2t99,cortexa55,cortexa75,cortexa76,cortexa76ae,cortexa77,cortexa78,cortexa78ae,cortexa78c,cortexa65,cortexa65ae,cortexx1,ares,neoversen1,neoversee1,octeontx2,octeontx2t98,octeontx2t96,octeontx2t93,octeontx2f95,octeontx2f95n,octeontx2f95mm,a64fx,tsv110,thunderx3t110,zeus,neoversev1,neoverse512tvb,saphira,cortexa57cortexa53,cortexa72cortexa53,cortexa73cortexa35,cortexa73cortexa53,cortexa75cortexa55,cortexa76cortexa55,cortexr82,cortexa510,cortexa710,cortexa715,cortexx2,neoversen2,demeter,neoversev2"
(const (symbol_ref "((enum attr_tune) aarch64_tune)")))
diff --git a/gcc/doc/gcc/gcc-command-options/machine-dependent-options/aarch64-options.rst b/gcc/doc/gcc/gcc-command-options/machine-dependent-options/aarch64-options.rst
index c2b23a6ee97ef2b7c74119f22c1d3e3d85385f4d..2e1bd6dbfb1fcff53dd562ec5e8923d0a21cf715 100644
--- a/gcc/doc/gcc/gcc-command-options/machine-dependent-options/aarch64-options.rst
+++ b/gcc/doc/gcc/gcc-command-options/machine-dependent-options/aarch64-options.rst
@@ -258,7 +258,8 @@ These options are defined for AArch64 implementations:
:samp:`cortex-a73.cortex-a35`, :samp:`cortex-a73.cortex-a53`,
:samp:`cortex-a75.cortex-a55`, :samp:`cortex-a76.cortex-a55`,
:samp:`cortex-r82`, :samp:`cortex-x1`, :samp:`cortex-x2`,
- :samp:`cortex-a510`, :samp:`cortex-a710`, :samp:`ampere1`, :samp:`native`.
+ :samp:`cortex-a510`, :samp:`cortex-a710`, :samp:`cortex-a715`, :samp:`ampere1`,
+ :samp:`native`.
The values :samp:`cortex-a57.cortex-a53`, :samp:`cortex-a72.cortex-a53`,
:samp:`cortex-a73.cortex-a35`, :samp:`cortex-a73.cortex-a53`,
Comments
Hi Srinath,
> -----Original Message-----
> From: Srinath Parvathaneni <srinath.parvathaneni@arm.com>
> Sent: Friday, November 11, 2022 11:58 AM
> To: gcc-patches@gcc.gnu.org
> Cc: Richard Sandiford <Richard.Sandiford@arm.com>; Kyrylo Tkachov
> <Kyrylo.Tkachov@arm.com>
> Subject: [PATCH][GCC] aarch64: Add support for Cortex-A715 CPU.
>
> Hi,
>
> This patch adds support for Cortex-A715 CPU.
>
> Bootstrapped on aarch64-none-linux-gnu and found no regressions.
>
> Ok for GCC master?
>
Ok. Please make sure aarch64-tune.md is appropriately regenerated in combination with the other -mcpu options you're adding.
Thanks,
Kyrill
> Regards,
> Srinath.
>
> gcc/ChangeLog:
>
> 2022-11-09 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
>
> * config/aarch64/aarch64-cores.def (AARCH64_CORE): Add Cortex-A715
> CPU.
> * config/aarch64/aarch64-tune.md: Regenerate.
> * doc/gcc/gcc-command-options/machine-dependent-options/aarch64-
> options.rst:
> Document Cortex-A715 CPU.
>
>
> ############### Attachment also inlined for ease of reply
> ###############
>
>
> diff --git a/gcc/config/aarch64/aarch64-cores.def
> b/gcc/config/aarch64/aarch64-cores.def
> index
> e9a4b622be018d92a790db10f4d5cf926bba512c..380bd8d90fdc7bddea2c846
> 5522a30f938c2ffc5 100644
> --- a/gcc/config/aarch64/aarch64-cores.def
> +++ b/gcc/config/aarch64/aarch64-cores.def
> @@ -167,6 +167,8 @@ AARCH64_CORE("cortex-a510", cortexa510,
> cortexa55, V9A, (SVE2_BITPERM, MEMTAG,
>
> AARCH64_CORE("cortex-a710", cortexa710, cortexa57, V9A,
> (SVE2_BITPERM, MEMTAG, I8MM, BF16), neoversen2, 0x41, 0xd47, -1)
>
> +AARCH64_CORE("cortex-a715", cortexa715, cortexa57, V9A,
> (SVE2_BITPERM, MEMTAG, I8MM, BF16), neoversen2, 0x41, 0xd4d, -1)
> +
> AARCH64_CORE("cortex-x2", cortexx2, cortexa57, V9A, (SVE2_BITPERM,
> MEMTAG, I8MM, BF16), neoversen2, 0x41, 0xd48, -1)
>
> AARCH64_CORE("neoverse-n2", neoversen2, cortexa57, V9A, (I8MM, BF16,
> SVE2_BITPERM, RNG, MEMTAG, PROFILE), neoversen2, 0x41, 0xd49, -1)
> diff --git a/gcc/config/aarch64/aarch64-tune.md
> b/gcc/config/aarch64/aarch64-tune.md
> index
> 84e9bbf44f6222b3e5bcf4cbf8fab7ebf17015e1..f5b1482ba357d14f36e13ca3c
> 4358865d4238e9a 100644
> --- a/gcc/config/aarch64/aarch64-tune.md
> +++ b/gcc/config/aarch64/aarch64-tune.md
> @@ -1,5 +1,5 @@
> ;; -*- buffer-read-only: t -*-
> ;; Generated automatically by gentune.sh from aarch64-cores.def
> (define_attr "tune"
> -
> "cortexa34,cortexa35,cortexa53,cortexa57,cortexa72,cortexa73,thun
> derx,thunderxt88p1,thunderxt88,octeontx,octeontxt81,octeontxt83,thunder
> xt81,thunderxt83,ampere1,emag,xgene1,falkor,qdf24xx,exynosm1,phecda,t
> hunderx2t99p1,vulcan,thunderx2t99,cortexa55,cortexa75,cortexa76,cortexa
> 76ae,cortexa77,cortexa78,cortexa78ae,cortexa78c,cortexa65,cortexa65ae,co
> rtexx1,ares,neoversen1,neoversee1,octeontx2,octeontx2t98,octeontx2t96,oc
> teontx2t93,octeontx2f95,octeontx2f95n,octeontx2f95mm,a64fx,tsv110,thun
> derx3t110,zeus,neoversev1,neoverse512tvb,saphira,cortexa57cortexa53,cort
> exa72cortexa53,cortexa73cortexa35,cortexa73cortexa53,cortexa75cortexa55
> ,cortexa76cortexa55,cortexr82,cortexa510,cortexa710,cortexx2,neoversen2,
> demeter,neoversev2"
> +
> "cortexa34,cortexa35,cortexa53,cortexa57,cortexa72,cortexa73,thun
> derx,thunderxt88p1,thunderxt88,octeontx,octeontxt81,octeontxt83,thunder
> xt81,thunderxt83,ampere1,emag,xgene1,falkor,qdf24xx,exynosm1,phecda,t
> hunderx2t99p1,vulcan,thunderx2t99,cortexa55,cortexa75,cortexa76,cortexa
> 76ae,cortexa77,cortexa78,cortexa78ae,cortexa78c,cortexa65,cortexa65ae,co
> rtexx1,ares,neoversen1,neoversee1,octeontx2,octeontx2t98,octeontx2t96,oc
> teontx2t93,octeontx2f95,octeontx2f95n,octeontx2f95mm,a64fx,tsv110,thun
> derx3t110,zeus,neoversev1,neoverse512tvb,saphira,cortexa57cortexa53,cort
> exa72cortexa53,cortexa73cortexa35,cortexa73cortexa53,cortexa75cortexa55
> ,cortexa76cortexa55,cortexr82,cortexa510,cortexa710,cortexa715,cortexx2,n
> eoversen2,demeter,neoversev2"
> (const (symbol_ref "((enum attr_tune) aarch64_tune)")))
> diff --git a/gcc/doc/gcc/gcc-command-options/machine-dependent-
> options/aarch64-options.rst b/gcc/doc/gcc/gcc-command-options/machine-
> dependent-options/aarch64-options.rst
> index
> c2b23a6ee97ef2b7c74119f22c1d3e3d85385f4d..2e1bd6dbfb1fcff53dd562ec5
> e8923d0a21cf715 100644
> --- a/gcc/doc/gcc/gcc-command-options/machine-dependent-
> options/aarch64-options.rst
> +++ b/gcc/doc/gcc/gcc-command-options/machine-dependent-
> options/aarch64-options.rst
> @@ -258,7 +258,8 @@ These options are defined for AArch64
> implementations:
> :samp:`cortex-a73.cortex-a35`, :samp:`cortex-a73.cortex-a53`,
> :samp:`cortex-a75.cortex-a55`, :samp:`cortex-a76.cortex-a55`,
> :samp:`cortex-r82`, :samp:`cortex-x1`, :samp:`cortex-x2`,
> - :samp:`cortex-a510`, :samp:`cortex-a710`, :samp:`ampere1`,
> :samp:`native`.
> + :samp:`cortex-a510`, :samp:`cortex-a710`, :samp:`cortex-a715`,
> :samp:`ampere1`,
> + :samp:`native`.
>
> The values :samp:`cortex-a57.cortex-a53`, :samp:`cortex-a72.cortex-a53`,
> :samp:`cortex-a73.cortex-a35`, :samp:`cortex-a73.cortex-a53`,
>
>
Hi,
> -----Original Message-----
> From: Kyrylo Tkachov <Kyrylo.Tkachov@arm.com>
> Sent: Friday, November 11, 2022 2:24 PM
> To: Srinath Parvathaneni <Srinath.Parvathaneni@arm.com>; gcc-
> patches@gcc.gnu.org
> Cc: Richard Sandiford <Richard.Sandiford@arm.com>
> Subject: RE: [PATCH][GCC] aarch64: Add support for Cortex-A715 CPU.
>
> Hi Srinath,
>
> > -----Original Message-----
> > From: Srinath Parvathaneni <srinath.parvathaneni@arm.com>
> > Sent: Friday, November 11, 2022 11:58 AM
> > To: gcc-patches@gcc.gnu.org
> > Cc: Richard Sandiford <Richard.Sandiford@arm.com>; Kyrylo Tkachov
> > <Kyrylo.Tkachov@arm.com>
> > Subject: [PATCH][GCC] aarch64: Add support for Cortex-A715 CPU.
> >
> > Hi,
> >
> > This patch adds support for Cortex-A715 CPU.
> >
> > Bootstrapped on aarch64-none-linux-gnu and found no regressions.
> >
> > Ok for GCC master?
> >
>
> Ok. Please make sure aarch64-tune.md is appropriately regenerated in
> combination with the other -mcpu options you're adding.
Thank you Kyrill for approving the patches, I have re-checked the regenerated
aarch64-tune.md for the added CPU's support and committed the code on to GCC master.
Regards,
Srinath.
> Thanks,
> Kyrill
>
> > Regards,
> > Srinath.
> >
> > gcc/ChangeLog:
> >
> > 2022-11-09 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
> >
> > * config/aarch64/aarch64-cores.def (AARCH64_CORE): Add
> > Cortex-A715 CPU.
> > * config/aarch64/aarch64-tune.md: Regenerate.
> > *
> > doc/gcc/gcc-command-options/machine-dependent-options/aarch64-
> > options.rst:
> > Document Cortex-A715 CPU.
> >
> >
> > ############### Attachment also inlined for ease of reply
> > ###############
> >
> >
> > diff --git a/gcc/config/aarch64/aarch64-cores.def
> > b/gcc/config/aarch64/aarch64-cores.def
> > index
> >
> e9a4b622be018d92a790db10f4d5cf926bba512c..380bd8d90fdc7bddea2c846
> > 5522a30f938c2ffc5 100644
> > --- a/gcc/config/aarch64/aarch64-cores.def
> > +++ b/gcc/config/aarch64/aarch64-cores.def
> > @@ -167,6 +167,8 @@ AARCH64_CORE("cortex-a510", cortexa510,
> > cortexa55, V9A, (SVE2_BITPERM, MEMTAG,
> >
> > AARCH64_CORE("cortex-a710", cortexa710, cortexa57, V9A,
> > (SVE2_BITPERM, MEMTAG, I8MM, BF16), neoversen2, 0x41, 0xd47, -1)
> >
> > +AARCH64_CORE("cortex-a715", cortexa715, cortexa57, V9A,
> > (SVE2_BITPERM, MEMTAG, I8MM, BF16), neoversen2, 0x41, 0xd4d, -1)
> > +
> > AARCH64_CORE("cortex-x2", cortexx2, cortexa57, V9A, (SVE2_BITPERM,
> > MEMTAG, I8MM, BF16), neoversen2, 0x41, 0xd48, -1)
> >
> > AARCH64_CORE("neoverse-n2", neoversen2, cortexa57, V9A, (I8MM,
> BF16,
> > SVE2_BITPERM, RNG, MEMTAG, PROFILE), neoversen2, 0x41, 0xd49, -1) diff
> > --git a/gcc/config/aarch64/aarch64-tune.md
> > b/gcc/config/aarch64/aarch64-tune.md
> > index
> >
> 84e9bbf44f6222b3e5bcf4cbf8fab7ebf17015e1..f5b1482ba357d14f36e13ca3c
> > 4358865d4238e9a 100644
> > --- a/gcc/config/aarch64/aarch64-tune.md
> > +++ b/gcc/config/aarch64/aarch64-tune.md
> > @@ -1,5 +1,5 @@
> > ;; -*- buffer-read-only: t -*-
> > ;; Generated automatically by gentune.sh from aarch64-cores.def
> > (define_attr "tune"
> > -
> > "cortexa34,cortexa35,cortexa53,cortexa57,cortexa72,cortexa73,thun
> >
> derx,thunderxt88p1,thunderxt88,octeontx,octeontxt81,octeontxt83,thunde
> > r
> >
> xt81,thunderxt83,ampere1,emag,xgene1,falkor,qdf24xx,exynosm1,phecda,t
> > hunderx2t99p1,vulcan,thunderx2t99,cortexa55,cortexa75,cortexa76,cortex
> > a
> > 76ae,cortexa77,cortexa78,cortexa78ae,cortexa78c,cortexa65,cortexa65ae,
> > co
> > rtexx1,ares,neoversen1,neoversee1,octeontx2,octeontx2t98,octeontx2t96,
> > oc
> >
> teontx2t93,octeontx2f95,octeontx2f95n,octeontx2f95mm,a64fx,tsv110,thun
> > derx3t110,zeus,neoversev1,neoverse512tvb,saphira,cortexa57cortexa53,co
> > rt
> >
> exa72cortexa53,cortexa73cortexa35,cortexa73cortexa53,cortexa75cortexa5
> > 5
> > ,cortexa76cortexa55,cortexr82,cortexa510,cortexa710,cortexx2,neoversen
> > 2,
> > demeter,neoversev2"
> > +
> > "cortexa34,cortexa35,cortexa53,cortexa57,cortexa72,cortexa73,thun
> >
> derx,thunderxt88p1,thunderxt88,octeontx,octeontxt81,octeontxt83,thunde
> > r
> >
> xt81,thunderxt83,ampere1,emag,xgene1,falkor,qdf24xx,exynosm1,phecda,t
> > hunderx2t99p1,vulcan,thunderx2t99,cortexa55,cortexa75,cortexa76,cortex
> > a
> > 76ae,cortexa77,cortexa78,cortexa78ae,cortexa78c,cortexa65,cortexa65ae,
> > co
> > rtexx1,ares,neoversen1,neoversee1,octeontx2,octeontx2t98,octeontx2t96,
> > oc
> >
> teontx2t93,octeontx2f95,octeontx2f95n,octeontx2f95mm,a64fx,tsv110,thun
> > derx3t110,zeus,neoversev1,neoverse512tvb,saphira,cortexa57cortexa53,co
> > rt
> >
> exa72cortexa53,cortexa73cortexa35,cortexa73cortexa53,cortexa75cortexa5
> > 5
> > ,cortexa76cortexa55,cortexr82,cortexa510,cortexa710,cortexa715,cortexx
> > 2,n
> > eoversen2,demeter,neoversev2"
> > (const (symbol_ref "((enum attr_tune) aarch64_tune)"))) diff --git
> > a/gcc/doc/gcc/gcc-command-options/machine-dependent-
> > options/aarch64-options.rst b/gcc/doc/gcc/gcc-command-
> options/machine-
> > dependent-options/aarch64-options.rst
> > index
> >
> c2b23a6ee97ef2b7c74119f22c1d3e3d85385f4d..2e1bd6dbfb1fcff53dd562ec5
> > e8923d0a21cf715 100644
> > --- a/gcc/doc/gcc/gcc-command-options/machine-dependent-
> > options/aarch64-options.rst
> > +++ b/gcc/doc/gcc/gcc-command-options/machine-dependent-
> > options/aarch64-options.rst
> > @@ -258,7 +258,8 @@ These options are defined for AArch64
> > implementations:
> > :samp:`cortex-a73.cortex-a35`, :samp:`cortex-a73.cortex-a53`,
> > :samp:`cortex-a75.cortex-a55`, :samp:`cortex-a76.cortex-a55`,
> > :samp:`cortex-r82`, :samp:`cortex-x1`, :samp:`cortex-x2`,
> > - :samp:`cortex-a510`, :samp:`cortex-a710`, :samp:`ampere1`,
> > :samp:`native`.
> > + :samp:`cortex-a510`, :samp:`cortex-a710`, :samp:`cortex-a715`,
> > :samp:`ampere1`,
> > + :samp:`native`.
> >
> > The values :samp:`cortex-a57.cortex-a53`, :samp:`cortex-a72.cortex-a53`,
> > :samp:`cortex-a73.cortex-a35`, :samp:`cortex-a73.cortex-a53`,
> >
> >
@@ -167,6 +167,8 @@ AARCH64_CORE("cortex-a510", cortexa510, cortexa55, V9A, (SVE2_BITPERM, MEMTAG,
AARCH64_CORE("cortex-a710", cortexa710, cortexa57, V9A, (SVE2_BITPERM, MEMTAG, I8MM, BF16), neoversen2, 0x41, 0xd47, -1)
+AARCH64_CORE("cortex-a715", cortexa715, cortexa57, V9A, (SVE2_BITPERM, MEMTAG, I8MM, BF16), neoversen2, 0x41, 0xd4d, -1)
+
AARCH64_CORE("cortex-x2", cortexx2, cortexa57, V9A, (SVE2_BITPERM, MEMTAG, I8MM, BF16), neoversen2, 0x41, 0xd48, -1)
AARCH64_CORE("neoverse-n2", neoversen2, cortexa57, V9A, (I8MM, BF16, SVE2_BITPERM, RNG, MEMTAG, PROFILE), neoversen2, 0x41, 0xd49, -1)
@@ -1,5 +1,5 @@
;; -*- buffer-read-only: t -*-
;; Generated automatically by gentune.sh from aarch64-cores.def
(define_attr "tune"
- "cortexa34,cortexa35,cortexa53,cortexa57,cortexa72,cortexa73,thunderx,thunderxt88p1,thunderxt88,octeontx,octeontxt81,octeontxt83,thunderxt81,thunderxt83,ampere1,emag,xgene1,falkor,qdf24xx,exynosm1,phecda,thunderx2t99p1,vulcan,thunderx2t99,cortexa55,cortexa75,cortexa76,cortexa76ae,cortexa77,cortexa78,cortexa78ae,cortexa78c,cortexa65,cortexa65ae,cortexx1,ares,neoversen1,neoversee1,octeontx2,octeontx2t98,octeontx2t96,octeontx2t93,octeontx2f95,octeontx2f95n,octeontx2f95mm,a64fx,tsv110,thunderx3t110,zeus,neoversev1,neoverse512tvb,saphira,cortexa57cortexa53,cortexa72cortexa53,cortexa73cortexa35,cortexa73cortexa53,cortexa75cortexa55,cortexa76cortexa55,cortexr82,cortexa510,cortexa710,cortexx2,neoversen2,demeter,neoversev2"
+ "cortexa34,cortexa35,cortexa53,cortexa57,cortexa72,cortexa73,thunderx,thunderxt88p1,thunderxt88,octeontx,octeontxt81,octeontxt83,thunderxt81,thunderxt83,ampere1,emag,xgene1,falkor,qdf24xx,exynosm1,phecda,thunderx2t99p1,vulcan,thunderx2t99,cortexa55,cortexa75,cortexa76,cortexa76ae,cortexa77,cortexa78,cortexa78ae,cortexa78c,cortexa65,cortexa65ae,cortexx1,ares,neoversen1,neoversee1,octeontx2,octeontx2t98,octeontx2t96,octeontx2t93,octeontx2f95,octeontx2f95n,octeontx2f95mm,a64fx,tsv110,thunderx3t110,zeus,neoversev1,neoverse512tvb,saphira,cortexa57cortexa53,cortexa72cortexa53,cortexa73cortexa35,cortexa73cortexa53,cortexa75cortexa55,cortexa76cortexa55,cortexr82,cortexa510,cortexa710,cortexa715,cortexx2,neoversen2,demeter,neoversev2"
(const (symbol_ref "((enum attr_tune) aarch64_tune)")))
@@ -258,7 +258,8 @@ These options are defined for AArch64 implementations:
:samp:`cortex-a73.cortex-a35`, :samp:`cortex-a73.cortex-a53`,
:samp:`cortex-a75.cortex-a55`, :samp:`cortex-a76.cortex-a55`,
:samp:`cortex-r82`, :samp:`cortex-x1`, :samp:`cortex-x2`,
- :samp:`cortex-a510`, :samp:`cortex-a710`, :samp:`ampere1`, :samp:`native`.
+ :samp:`cortex-a510`, :samp:`cortex-a710`, :samp:`cortex-a715`, :samp:`ampere1`,
+ :samp:`native`.
The values :samp:`cortex-a57.cortex-a53`, :samp:`cortex-a72.cortex-a53`,
:samp:`cortex-a73.cortex-a35`, :samp:`cortex-a73.cortex-a53`,