From patchwork Mon Sep 4 00:20:45 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tsukasa OI X-Patchwork-Id: 137434 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:ab0a:0:b0:3f2:4152:657d with SMTP id m10csp817683vqo; Sun, 3 Sep 2023 17:21:49 -0700 (PDT) X-Google-Smtp-Source: AGHT+IHffPNsm5X6LcMN7BAJY+mMGbpjw2LaexccVB6tF4earpkp3o4kaazBYUw8t+0r4v6ohwTS X-Received: by 2002:a17:906:5a56:b0:9a1:b705:75d1 with SMTP id my22-20020a1709065a5600b009a1b70575d1mr5413951ejc.51.1693786909462; Sun, 03 Sep 2023 17:21:49 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1693786909; cv=none; d=google.com; s=arc-20160816; b=oktowbcXqwoiS0z3ZSnT4FH1bCqMROaZpIg2k98F5jYRF+i314gArpiQs10TAMwHdz 4UrIW8OVK+wySXTX+QWg7XAUa/QQ4gFomntSEU4TbztPWuIVbyHtOSaWAWusBKQQyiqP ScsnnnRYxd9JrlWiDXLdJ9K5ueio3pnpDFTTL/74r7rqSDRetSmuhw0ekyeyalvaWuk2 Nssh016RnJKbr/tQvkYea/M1D4sAUEh7dFTxKVxGkzIFWOsEq7gA9pb21E3zn5XVvhX4 CZqvcp7TBwaTdy7uMjPNKjuhoyfxG5fnLaDRlqguGKSJovNvvCNh8IsGr05OqSQTwsF3 mjdg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:reply-to:from:list-subscribe:list-help:list-post :list-archive:list-unsubscribe:list-id:precedence :content-transfer-encoding:mime-version:message-id:date:subject:cc :to:dmarc-filter:delivered-to:dkim-signature:dkim-filter; bh=PNPA9e0Glg1OsuznnN7QsnlpZAGVMRHcICd+LMS4cHM=; fh=HKgiOHUFLyfVG2npWMLYE8/3Ecp4EiEdadhQOzpm3aI=; b=wh2lbQqh6k/ijPxcH8NnY41SORONHKYt2W17iaYBS9wCzW2t+O/0wlXrWSAQUJJJ0+ UGOk26r11o6+nQuSEuqt8Z51AErvEiqLT7yUTCoFkMSs45AzWFlIkW+UoQ3EGvFVvdNj OcQ7SCy+yB12TowKgGaAIqMrcDqvogIzJV1VxOeLIgFuS6UOjD/WSyfNQ4t050d6g51N gvE3OhB/9tt1w7m0GoMaq/7iDFM4q4c//H79kHe8pQq6d9l8GQJD9yfgAcpNEy8u3bLr eYEaxM+osAnZNWU737xhODZ1mq9FbajvQGLPADTRQ3Y0oDcWcw2J9Ir3UuaeUk8UGSxp 2QnA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@gcc.gnu.org header.s=default header.b=oRjb+rnN; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=gnu.org Received: from server2.sourceware.org (ip-8-43-85-97.sourceware.org. [8.43.85.97]) by mx.google.com with ESMTPS id kg12-20020a17090776ec00b009828e8bec17si5817137ejc.531.2023.09.03.17.21.49 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 03 Sep 2023 17:21:49 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) client-ip=8.43.85.97; Authentication-Results: mx.google.com; dkim=pass header.i=@gcc.gnu.org header.s=default header.b=oRjb+rnN; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=gnu.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 655993858421 for ; Mon, 4 Sep 2023 00:21:48 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 655993858421 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1693786908; bh=PNPA9e0Glg1OsuznnN7QsnlpZAGVMRHcICd+LMS4cHM=; h=To:Cc:Subject:Date:List-Id:List-Unsubscribe:List-Archive: List-Post:List-Help:List-Subscribe:From:Reply-To:From; b=oRjb+rnN5rrdZ1fO1wajflAbhekopYIfpGANcpAV6VQGgIVkD8A6mwBFFUTwrVFe7 5cCuI707UO6X4U23//cM9uVO1GowmrKcFS8jvsyBpGaBMZBpkI0vDJzsqdKJGb81mL Fv0ls/6gaxbVtShhTD+2gXS7hzZ8kpQdKpXa91eM= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mail-sender-0.a4lg.com (mail-sender.a4lg.com [153.120.152.154]) by sourceware.org (Postfix) with ESMTPS id 43ADC3858C54 for ; Mon, 4 Sep 2023 00:20:55 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 43ADC3858C54 Received: from [127.0.0.1] (localhost [127.0.0.1]) by mail-sender-0.a4lg.com (Postfix) with ESMTPSA id A7986300089; Mon, 4 Sep 2023 00:20:50 +0000 (UTC) To: Tsukasa OI , Kito Cheng , Palmer Dabbelt , Andrew Waterman , Jim Wilson , Jeff Law Cc: gcc-patches@gcc.gnu.org Subject: [PATCH] RISC-V: Fix Zicond ICE on large constants Date: Mon, 4 Sep 2023 00:20:45 +0000 Message-ID: <3cc5403de383d7c8cfd1769948c2bcf9d54b97f9.1693786829.git.research_trasio@irq.a4lg.com> Mime-Version: 1.0 X-Spam-Status: No, score=-11.9 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, GIT_PATCH_0, KAM_MANYTO, KAM_SHORT, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Tsukasa OI via Gcc-patches From: Tsukasa OI Reply-To: Tsukasa OI Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1776064302167254519 X-GMAIL-MSGID: 1776064302167254519 From: Tsukasa OI Large constant cons and/or alt will trigger ICEs building GCC target libraries (libgomp and libatomic) when the 'Zicond' extension is enabled. For instance, zicond-ice-2.c (new test case in this commit) will cause an ICE when SOME_NUMBER is 0x1000 or larger. While opposite numbers corresponding cons/alt (two temp2 variables) are checked, cons/alt themselves are not checked and causing 2 ICEs building GCC target libraries as of this writing: 1. gcc/libatomic/config/posix/lock.c 2. gcc/libgomp/fortran.c Coercing a large value into a register will fix the issue. gcc/ChangeLog: * config/riscv/riscv.cc (riscv_expand_conditional_move): Force large constant cons/alt into a register. gcc/testsuite/ChangeLog: * gcc.target/riscv/zicond-ice-2.c: New test. This is based on an ICE at libat_lock_n func on gcc/libatomic/config/posix/lock.c but heavily minimized. --- gcc/config/riscv/riscv.cc | 16 ++++++++++------ gcc/testsuite/gcc.target/riscv/zicond-ice-2.c | 11 +++++++++++ 2 files changed, 21 insertions(+), 6 deletions(-) create mode 100644 gcc/testsuite/gcc.target/riscv/zicond-ice-2.c base-commit: 78f636d979530c8a649262dbd44914bdfb6f7290 diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc index 8d8f7b4f16ed..cfaa4b6a7720 100644 --- a/gcc/config/riscv/riscv.cc +++ b/gcc/config/riscv/riscv.cc @@ -3940,11 +3940,13 @@ riscv_expand_conditional_move (rtx dest, rtx op, rtx cons, rtx alt) rtx temp1 = gen_reg_rtx (mode); rtx temp2 = gen_int_mode (-1 * INTVAL (cons), mode); - /* TEMP2 might not fit into a signed 12 bit immediate suitable - for an addi instruction. If that's the case, force it into - a register. */ + /* TEMP2 and/or CONS might not fit into a signed 12 bit immediate + suitable for an addi instruction. If that's the case, force it + into a register. */ if (!SMALL_OPERAND (INTVAL (temp2))) temp2 = force_reg (mode, temp2); + if (!SMALL_OPERAND (INTVAL (cons))) + cons = force_reg (mode, cons); riscv_emit_binary (PLUS, temp1, alt, temp2); emit_insn (gen_rtx_SET (dest, @@ -3986,11 +3988,13 @@ riscv_expand_conditional_move (rtx dest, rtx op, rtx cons, rtx alt) rtx temp1 = gen_reg_rtx (mode); rtx temp2 = gen_int_mode (-1 * INTVAL (alt), mode); - /* TEMP2 might not fit into a signed 12 bit immediate suitable - for an addi instruction. If that's the case, force it into - a register. */ + /* TEMP2 and/or ALT might not fit into a signed 12 bit immediate + suitable for an addi instruction. If that's the case, force it + into a register. */ if (!SMALL_OPERAND (INTVAL (temp2))) temp2 = force_reg (mode, temp2); + if (!SMALL_OPERAND (INTVAL (alt))) + alt = force_reg (mode, alt); riscv_emit_binary (PLUS, temp1, cons, temp2); emit_insn (gen_rtx_SET (dest, diff --git a/gcc/testsuite/gcc.target/riscv/zicond-ice-2.c b/gcc/testsuite/gcc.target/riscv/zicond-ice-2.c new file mode 100644 index 000000000000..ffd8dcb5814e --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/zicond-ice-2.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_zicond -mabi=lp64d" { target { rv64 } } } */ +/* { dg-options "-march=rv32gc_zicond -mabi=ilp32d" { target { rv32 } } } */ + +#define SOME_NUMBER 0x1000 + +unsigned long +d (unsigned long n) +{ + return n > SOME_NUMBER ? SOME_NUMBER : n; +}