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[2620:52:3:1:0:246e:9693:128c]) by mx.google.com with ESMTPS id cw15-20020a170906478f00b0078def5c29e3si14505492ejc.596.2022.10.19.01.17.28 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 19 Oct 2022 01:17:28 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) client-ip=2620:52:3:1:0:246e:9693:128c; Authentication-Results: mx.google.com; dkim=pass header.i=@gcc.gnu.org header.s=default header.b=Ysa405CS; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=gnu.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 360253858D39 for ; Wed, 19 Oct 2022 08:17:27 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 360253858D39 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1666167447; bh=5odklD6aH2KJCZ0YXtQyWmNrRjzHm+A201ckSQEnttY=; h=Date:Subject:To:References:In-Reply-To:List-Id:List-Unsubscribe: List-Archive:List-Post:List-Help:List-Subscribe:From:Reply-To: From; b=Ysa405CScH6O6N36xX8lySqcgIJb/LhXaKYJ3m1UMFez84qlQbIAf0DGCPHl3z+JK xTHg220UQ6TsqVEjOMEnVkgqYUV/kgyihtUtd1ShEy9aM/JMF6G9bxtaKvzMiVNChe CZ+TBcrxV0ZL01Hest7hecULteaqWG1WBuKL+Ml0= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from sonicconh6002-vm1.mail.ssk.yahoo.co.jp (sonicconh6002-vm1.mail.ssk.yahoo.co.jp [182.22.37.26]) by sourceware.org (Postfix) with ESMTPS id 0C3A43858D39 for ; Wed, 19 Oct 2022 08:16:33 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 0C3A43858D39 X-YMail-OSG: tfpfdxkVM1k8Er1erQQpzWLl92DNTmGwy8NvM6BrG2A2ibt.B1h_yIoeBPrR96l 3rk9KXUVB_yx7IPathAX.o_YE7rncTaGQARqp8RWkUCsFZ_6JoXmCt6I5hF0qynN6_TxH.CziAJo JD3M6b8TAnlbK8aTUu21CIpxMaXTUyzWWHM8dhynsZunIF2cnqTVjkFWoqu6bJ7RXfOCg.s..D04 SQWJGFs98xHL0cTj5hBp3l1Q2YeOQmy4kkc1vP7NLn5Ux0YhrvIuwwbhVHBdGh7UA9Z0LBHEnllh KV15TluJyv.sznShvBQLwkfO_duRbaSU7b_aejekBtpvVhmZ13K58IPlKOArep_1LHt_RhNrfr1n Ch6.yXFT8IEyOctXAK4tHNy_7JtUz_3V2F9uUMJJMy9CjKvrdWRd2fw53GorI_YgfYD8fDeHzJxw jI6GOGejey_8JL8V_VUeTARvDGb.aQi0UUuwy2oRXnoD7MrpWSsOIJspZCUWf5KZN973SYqNXqRU .yZV.VXwdH.MEnmksCBI.9cMw2JR0U7guGEErqJgVyUMkidO2CNayTxJdcgMWqMlNnyY476ZQqhE 46g1YH8oA4ea0ZEwNi27QnFVULIuJgwxwkvP_LXf1BICAG53v8AYVg4PWY3jboc79E3WkABtHrM8 a_Xk_gJZi1RSJy97M7060lmRf9dbs9jc4WxX5ByK4pKiXNPU2f1IsuAjcdMqVW_l7o4PJwG7sd2z kIlV.PTV_hWmDGsTVaLd_V.wysh1RiiubBxcnOITLQDppSJ8fvJbrq2W91h.UtmAfWONoBv_GQCp r_JFxauRUn22mupbK5OWcajvsle.fIz9Bbuop7YoC4lfRefbIClkvqK2kSubm2g43h22TIUnokvH SbePZNiYuufHH5YkrTZmRMnkQfj09rka.Yudf495QlBAyi47h7UcxvItXb.RtOZqM9JnVXL7e92V tK4EGUHM- Received: from sonicgw.mail.yahoo.co.jp by sonicconh6002.mail.ssk.yahoo.co.jp with HTTP; Wed, 19 Oct 2022 08:16:29 +0000 Received: by smtphe6003.mail.ssk.ynwp.yahoo.co.jp (YJ Hermes SMTP Server) with ESMTPA ID fd2053b193b153d0b62dc43a5dcba0c5; Wed, 19 Oct 2022 17:16:27 +0900 (JST) Message-ID: <3054719f-6688-211c-da07-93c0fbf7c038@yahoo.co.jp> Date: Wed, 19 Oct 2022 17:16:24 +0900 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Windows NT 6.1; Win64; x64; rv:102.0) Gecko/20100101 Thunderbird/102.3.3 Subject: [PATCH v3] xtensa: Prepare the transition from Reload to LRA To: GCC Patches References: <7e3fe210-6dbc-fc29-dbb8-b951e89cf7e9@yahoo.co.jp> <87f124f0-8a10-6c3b-6b12-cabf855e2e4b@yahoo.co.jp> <3296b387-083a-40cf-1bb5-40269e804f52@yahoo.co.jp> In-Reply-To: X-Spam-Status: No, score=-12.2 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, FREEMAIL_ENVFROM_END_DIGIT, FREEMAIL_FROM, GIT_PATCH_0, RCVD_IN_DNSWL_NONE, SCC_5_SHORT_WORD_LINES, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Takayuki 'January June' Suwa via Gcc-patches From: Takayuki 'January June' Suwa Reply-To: Takayuki 'January June' Suwa Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1746661695533076011?= X-GMAIL-MSGID: =?utf-8?q?1747103198499905355?= On 2022/10/18 21:16, Max Filippov wrote: > Hi Suwa-san, Hi! > I've noticed that this is related to the following hunk: > > -#define CALL_USED_REGISTERS \ > +#define CALL_REALLY_USED_REGISTERS \ > { \ > - 1, 1, 4, 4, 4, 4, 4, 4, 1, 1, 1, 1, 2, 2, 2, 2, \ > - 1, 1, 1, \ > + 0, 0, 4, 4, 4, 4, 4, 4, 1, 1, 1, 1, 2, 2, 2, 2, \ > + 0, 0, 1, \ > 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ > 1, \ > } > > And the following change on top of v2 fixes this regression for me: > > diff --git a/gcc/config/xtensa/xtensa.h b/gcc/config/xtensa/xtensa.h > index 6b60e5960625..897f87f735da 100644 > --- a/gcc/config/xtensa/xtensa.h > +++ b/gcc/config/xtensa/xtensa.h > @@ -244,7 +244,7 @@ along with GCC; see the file COPYING3. If not see > > #define CALL_REALLY_USED_REGISTERS \ > { \ > - 0, 0, 4, 4, 4, 4, 4, 4, 1, 1, 1, 1, 2, 2, 2, 2, \ > + 1, 0, 4, 4, 4, 4, 4, 4, 1, 1, 1, 1, 2, 2, 2, 2, \ > 0, 0, 1, \ > 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ > 1, \ If we take "CALL_REALLY_USED_REGISTERS" literally, it makes sense because the CALL0/CALLX0 instructions actually change the A0 register. (little question: Then FIXED_REGISTERS is interpreted as not including the link register, but is that correct...) === This patch provides the first step in the transition from Reload to LRA in Xtensa. gcc/ChangeLog: * config/xtensa/xtensa-proto.h (xtensa_split1_finished_p, xtensa_split_DI_reg_imm): New prototypes. * config/xtensa/xtensa.cc (xtensa_split1_finished_p, xtensa_split_DI_reg_imm, xtensa_lra_p): New functions. (TARGET_LRA_P): Replace the dummy hook with xtensa_lra_p. (xt_true_regnum): Rework. * gcc/config/xtensa/xtensa.h (CALL_REALLY_USED_REGISTERS): Switch from CALL_USED_REGISTERS, and revise the comment. * gcc/config/xtensa/constraints.md (Y): Use !xtensa_split1_finished_p() instead of can_create_pseudo_p(). * gcc/config/xtensa/predicates.md (move_operand): Ditto. * gcc/config/xtensa/xtensa.md: Add two new split patterns: - splits DImode immediate load into two SImode ones - puts out-of-constraint SImode constants into the constant pool * gcc/config/xtensa/xtensa.opt (-mlra): New target-specific option for testing purpose. --- gcc/config/xtensa/constraints.md | 2 +- gcc/config/xtensa/predicates.md | 2 +- gcc/config/xtensa/xtensa-protos.h | 2 + gcc/config/xtensa/xtensa.cc | 69 ++++++++++++++++++++++++++----- gcc/config/xtensa/xtensa.h | 8 ++-- gcc/config/xtensa/xtensa.md | 36 ++++++++++++---- gcc/config/xtensa/xtensa.opt | 4 ++ 7 files changed, 99 insertions(+), 24 deletions(-) diff --git a/gcc/config/xtensa/constraints.md b/gcc/config/xtensa/constraints.md index e4c314b267c..cd200d6d15a 100644 --- a/gcc/config/xtensa/constraints.md +++ b/gcc/config/xtensa/constraints.md @@ -121,7 +121,7 @@ (ior (and (match_code "const_int,const_double,const,symbol_ref,label_ref") (match_test "TARGET_AUTO_LITPOOLS")) (and (match_code "const_int") - (match_test "can_create_pseudo_p ()")))) + (match_test "! xtensa_split1_finished_p ()")))) ;; Memory constraints. Do not use define_memory_constraint here. Doing so ;; causes reload to force some constants into the constant pool, but since diff --git a/gcc/config/xtensa/predicates.md b/gcc/config/xtensa/predicates.md index 0590c0f81a9..c11e8634dbe 100644 --- a/gcc/config/xtensa/predicates.md +++ b/gcc/config/xtensa/predicates.md @@ -149,7 +149,7 @@ (ior (and (match_code "const_int") (match_test "(GET_MODE_CLASS (mode) == MODE_INT && xtensa_simm12b (INTVAL (op))) - || can_create_pseudo_p ()")) + || ! xtensa_split1_finished_p ()")) (and (match_code "const_int,const_double,const,symbol_ref,label_ref") (match_test "(TARGET_CONST16 || TARGET_AUTO_LITPOOLS) && CONSTANT_P (op) diff --git a/gcc/config/xtensa/xtensa-protos.h b/gcc/config/xtensa/xtensa-protos.h index 459e2aac9fc..bc75ad9698a 100644 --- a/gcc/config/xtensa/xtensa-protos.h +++ b/gcc/config/xtensa/xtensa-protos.h @@ -58,6 +58,8 @@ extern char *xtensa_emit_call (int, rtx *); extern char *xtensa_emit_sibcall (int, rtx *); extern bool xtensa_tls_referenced_p (rtx); extern enum rtx_code xtensa_shlrd_which_direction (rtx, rtx); +extern bool xtensa_split1_finished_p (void); +extern void xtensa_split_DI_reg_imm (rtx *); #ifdef TREE_CODE extern void init_cumulative_args (CUMULATIVE_ARGS *, int); diff --git a/gcc/config/xtensa/xtensa.cc b/gcc/config/xtensa/xtensa.cc index 828c7642b7c..950eb5a59be 100644 --- a/gcc/config/xtensa/xtensa.cc +++ b/gcc/config/xtensa/xtensa.cc @@ -56,6 +56,7 @@ along with GCC; see the file COPYING3. If not see #include "hw-doloop.h" #include "rtl-iter.h" #include "insn-attr.h" +#include "tree-pass.h" /* This file should be included last. */ #include "target-def.h" @@ -199,6 +200,7 @@ static void xtensa_output_mi_thunk (FILE *file, tree thunk ATTRIBUTE_UNUSED, HOST_WIDE_INT delta, HOST_WIDE_INT vcall_offset, tree function); +static bool xtensa_lra_p (void); static rtx xtensa_delegitimize_address (rtx); @@ -295,7 +297,7 @@ static rtx xtensa_delegitimize_address (rtx); #define TARGET_CANNOT_FORCE_CONST_MEM xtensa_cannot_force_const_mem #undef TARGET_LRA_P -#define TARGET_LRA_P hook_bool_void_false +#define TARGET_LRA_P xtensa_lra_p #undef TARGET_LEGITIMATE_ADDRESS_P #define TARGET_LEGITIMATE_ADDRESS_P xtensa_legitimate_address_p @@ -492,21 +494,30 @@ xtensa_mask_immediate (HOST_WIDE_INT v) int xt_true_regnum (rtx x) { - if (GET_CODE (x) == REG) + if (REG_P (x)) { - if (reg_renumber - && REGNO (x) >= FIRST_PSEUDO_REGISTER - && reg_renumber[REGNO (x)] >= 0) + if (! HARD_REGISTER_P (x) + && reg_renumber + && (lra_in_progress || reg_renumber[REGNO (x)] >= 0)) return reg_renumber[REGNO (x)]; return REGNO (x); } - if (GET_CODE (x) == SUBREG) + if (SUBREG_P (x)) { int base = xt_true_regnum (SUBREG_REG (x)); - if (base >= 0 && base < FIRST_PSEUDO_REGISTER) - return base + subreg_regno_offset (REGNO (SUBREG_REG (x)), - GET_MODE (SUBREG_REG (x)), - SUBREG_BYTE (x), GET_MODE (x)); + + if (base >= 0 + && HARD_REGISTER_NUM_P (base)) + { + struct subreg_info info; + + subreg_get_info (lra_in_progress + ? (unsigned) base : REGNO (SUBREG_REG (x)), + GET_MODE (SUBREG_REG (x)), + SUBREG_BYTE (x), GET_MODE (x), &info); + if (info.representable_p) + return base + info.offset; + } } return -1; } @@ -2477,6 +2488,36 @@ xtensa_shlrd_which_direction (rtx op0, rtx op1) } +/* Return true after "split1" pass has been finished. */ + +bool +xtensa_split1_finished_p (void) +{ + return cfun && (cfun->curr_properties & PROP_rtl_split_insns); +} + + +/* Split a DImode pair of reg (operand[0]) and const_int (operand[1]) into + two SImode pairs, the low-part (operands[0] and [1]) and the high-part + (operands[2] and [3]). */ + +void +xtensa_split_DI_reg_imm (rtx *operands) +{ + rtx lowpart, highpart; + + if (WORDS_BIG_ENDIAN) + split_double (operands[1], &highpart, &lowpart); + else + split_double (operands[1], &lowpart, &highpart); + + operands[3] = highpart; + operands[2] = gen_highpart (SImode, operands[0]); + operands[1] = lowpart; + operands[0] = gen_lowpart (SImode, operands[0]); +} + + /* Implement TARGET_CANNOT_FORCE_CONST_MEM. */ static bool @@ -5119,4 +5160,12 @@ xtensa_delegitimize_address (rtx op) return op; } +/* Implement TARGET_LRA_P. */ + +static bool +xtensa_lra_p (void) +{ + return TARGET_LRA; +} + #include "gt-xtensa.h" diff --git a/gcc/config/xtensa/xtensa.h b/gcc/config/xtensa/xtensa.h index 16e3d55e896..2275fe6d426 100644 --- a/gcc/config/xtensa/xtensa.h +++ b/gcc/config/xtensa/xtensa.h @@ -229,7 +229,7 @@ along with GCC; see the file COPYING3. If not see } /* 1 for registers not available across function calls. - These must include the FIXED_REGISTERS and also any + These need not include the FIXED_REGISTERS but must any registers that can be used without being saved. The latter must include the registers where values are returned and the register where structure-value addresses are passed. @@ -242,10 +242,10 @@ along with GCC; see the file COPYING3. If not see Proper values are computed in TARGET_CONDITIONAL_REGISTER_USAGE. */ -#define CALL_USED_REGISTERS \ +#define CALL_REALLY_USED_REGISTERS \ { \ - 1, 1, 4, 4, 4, 4, 4, 4, 1, 1, 1, 1, 2, 2, 2, 2, \ - 1, 1, 1, \ + 1, 0, 4, 4, 4, 4, 4, 4, 1, 1, 1, 1, 2, 2, 2, 2, \ + 0, 0, 1, \ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ 1, \ } diff --git a/gcc/config/xtensa/xtensa.md b/gcc/config/xtensa/xtensa.md index 608110c20bc..2e7f76ada5c 100644 --- a/gcc/config/xtensa/xtensa.md +++ b/gcc/config/xtensa/xtensa.md @@ -940,14 +940,9 @@ because of offering further optimization opportunities. */ if (register_operand (operands[0], DImode)) { - rtx lowpart, highpart; - - if (TARGET_BIG_ENDIAN) - split_double (operands[1], &highpart, &lowpart); - else - split_double (operands[1], &lowpart, &highpart); - emit_insn (gen_movsi (gen_lowpart (SImode, operands[0]), lowpart)); - emit_insn (gen_movsi (gen_highpart (SImode, operands[0]), highpart)); + xtensa_split_DI_reg_imm (operands); + emit_move_insn (operands[0], operands[1]); + emit_move_insn (operands[2], operands[3]); DONE; } @@ -981,6 +976,19 @@ } }) +(define_split + [(set (match_operand:DI 0 "register_operand") + (match_operand:DI 1 "const_int_operand"))] + "!TARGET_CONST16 && !TARGET_AUTO_LITPOOLS + && ! xtensa_split1_finished_p ()" + [(set (match_dup 0) + (match_dup 1)) + (set (match_dup 2) + (match_dup 3))] +{ + xtensa_split_DI_reg_imm (operands); +}) + ;; 32-bit Integer moves (define_expand "movsi" @@ -1017,6 +1025,18 @@ (set_attr "mode" "SI") (set_attr "length" "2,2,2,2,2,2,3,3,3,3,6,3,3,3,3,3")]) +(define_split + [(set (match_operand:SI 0 "register_operand") + (match_operand:SI 1 "const_int_operand"))] + "!TARGET_CONST16 && !TARGET_AUTO_LITPOOLS + && ! xtensa_split1_finished_p () + && ! xtensa_simm12b (INTVAL (operands[1]))" + [(set (match_dup 0) + (match_dup 1))] +{ + operands[1] = force_const_mem (SImode, operands[1]); +}) + (define_split [(set (match_operand:SI 0 "register_operand") (match_operand:SI 1 "constantpool_operand"))] diff --git a/gcc/config/xtensa/xtensa.opt b/gcc/config/xtensa/xtensa.opt index 08338e39060..00d2db4eae1 100644 --- a/gcc/config/xtensa/xtensa.opt +++ b/gcc/config/xtensa/xtensa.opt @@ -34,6 +34,10 @@ mextra-l32r-costs= Target RejectNegative Joined UInteger Var(xtensa_extra_l32r_costs) Init(0) Set extra memory access cost for L32R instruction, in clock-cycle units. +mlra +Target Mask(LRA) +Use LRA instead of reload (transitional). + mtarget-align Target Automatically align branch targets to reduce branch penalties.