From patchwork Tue Jan 9 02:12:26 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: joshua X-Patchwork-Id: 186191 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7300:37c1:b0:101:2151:f287 with SMTP id y1csp1398317dyq; Mon, 8 Jan 2024 18:14:13 -0800 (PST) X-Google-Smtp-Source: AGHT+IE2+Jy3eYl5hTmBHhboTVDb0gvivSq7qGawEGNSR+zb/CWdtg0Sh5jyFxtcgx5rWlzAFn2R X-Received: by 2002:a05:6808:3011:b0:3b9:d6c5:e3c8 with SMTP id ay17-20020a056808301100b003b9d6c5e3c8mr6204509oib.77.1704766452920; Mon, 08 Jan 2024 18:14:12 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1704766452; cv=pass; d=google.com; s=arc-20160816; b=ezFSESbPVH+x5MQCAflplOHre6QMGkLxhFsP76ROlGX2Ozv7Fp29T3KHSZt+SqihE1 WRHgDXwCzSKO6tZPqrq2WWL/TEM5rLsVCMiRdtTzeFYDEwBRqxXcTeyHBe11mucEVcCM ICsV7Lu5GKTx4jEaieAANHnC2aq2DHICzM0nDdiHFd2dq3yFR4ZzPW9A2hOgNySC+1Ik CQeF1uwEyX7AnSvsKe0mrp99ZsxrAySeuCQ7JhAigMqfTtNBO2eNVIr5erZ7U4K37rEV n65yXNO1oWRhy6I9n37KooHOpfpTD1+Se4Isb+xk6zNHlWV7hvUVqyciuHcF0Vt3cD+J W1jg== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=errors-to:reply-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :in-reply-to:references:mime-version:subject:message-id:cc:to:from :date:arc-filter:dmarc-filter:delivered-to; bh=Ea0VEqJXpKx8aLpBdP9nsU9o5c+NT3ZgZFcBgPxdfrA=; fh=eaRxjPBUFZHyIVS9d2CvUxA6FAEHsDDiInXYKNpa2SA=; b=dsXzCWaQXSgOpqKglBVhJulXzHc8+JovzA8z8PiPCgbO8J2PrEApCuNuPhPy4t/wFQ oh6fpytrn9dl23ulA5arT6nIS09IiFIwbt2nCXn+GeRlbpALN3RVAhaX1/GQxxXPQAQP 0JaDhLmFasrghnLqHsNxDzVj7EJeEudZ7UWU9a+qQm2r2dRtNzT+bs8ztNUqlHvA35Su smkfftzg62crBxdKcc0uxEl1DBdgA7WK0w0oA2uvrIMB4hhQMVeFkVXhC9FGMdL1N5zb yjhYyNCMsgEk5cqdmdTJVhgQcY3/hEthrp1/VIzTMZSSibAVc0Etz7OWviEHZmIh7aEC FGAw== ARC-Authentication-Results: i=2; mx.google.com; arc=pass (i=1); spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=alibaba.com Received: from server2.sourceware.org (server2.sourceware.org. [8.43.85.97]) by mx.google.com with ESMTPS id u19-20020a0cdd13000000b00680b5825d4dsi1308366qvk.370.2024.01.08.18.14.12 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 08 Jan 2024 18:14:12 -0800 (PST) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) client-ip=8.43.85.97; Authentication-Results: mx.google.com; arc=pass (i=1); spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=alibaba.com Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 889EE385841C for ; Tue, 9 Jan 2024 02:14:12 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from out30-99.freemail.mail.aliyun.com (out30-99.freemail.mail.aliyun.com [115.124.30.99]) by sourceware.org (Postfix) with ESMTPS id ADB373858283 for ; Tue, 9 Jan 2024 02:12:32 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org ADB373858283 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=linux.alibaba.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=linux.alibaba.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org ADB373858283 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=115.124.30.99 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1704766400; cv=none; b=Ur5w/yZiuFC9n6+wSpCENBjRi7xmsAPkV2WQbo20CH4YAxHS5+ZZ/oDY3FZY8cNJ0ve6VmUEVrhVKZjAM6VX4BsFUkhL80o1SEPQfYInUFd5fyXlNOfYY08WSgJUpP3bJFR00e5dz+zi1wCSMVm+cue3Mw7J366zEldVbmTREME= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1704766400; c=relaxed/simple; bh=Ea0VEqJXpKx8aLpBdP9nsU9o5c+NT3ZgZFcBgPxdfrA=; h=Date:From:To:Message-ID:Subject:MIME-Version; b=jF2wzIEZNO4De6b9q7W9s0SK9XVSqRX9aG8FB2bJ+i/AndTBjCzOoF0cPXSCWq2k6YG+aidrTpYeD2jzw1cBMDyWGobSHeyeb6zKP2jHN9+qlUfsauKET268Wp8EFhstu7QvqNx947DrnhT5Y9lw+nYGURuc8kPnmo2qKPd1A1c= ARC-Authentication-Results: i=1; server2.sourceware.org X-Alimail-AntiSpam: AC=PASS; BC=-1|-1; BR=01201311R181e4; CH=green; DM=||false|; DS=||; FP=0|-1|-1|-1|0|-1|-1|-1; HT=ay29a033018045170; MF=cooper.joshua@linux.alibaba.com; NM=1; PH=DW; RN=10; SR=0; TI=W4_0.2.3_v5ForWebDing_21443577_1704766155297_o7001c868; Received: from WS-web (cooper.joshua@linux.alibaba.com[W4_0.2.3_v5ForWebDing_21443577_1704766155297_o7001c868]) at Tue, 09 Jan 2024 10:12:26 +0800 Date: Tue, 09 Jan 2024 10:12:26 +0800 From: "joshua" To: " =?utf-8?b?6ZKf5bGF5ZOy?= " , "gcc-patches" Cc: "jim.wilson.gcc" , "palmer" , "andrew" , "philipp.tomsich" , "Jeff Law" , " =?utf-8?q?Christoph_M=C3=BCllner?= " , "jinma" , "Cooper Qu" Message-ID: <2ceba0d5-757c-410b-a8eb-72dcf61467f3.cooper.joshua@linux.alibaba.com> Subject: =?utf-8?q?Re=EF=BC=9A=5BPATCH_v4=5D_RISC-V=3A_Handle_differences_be?= =?utf-8?q?tween_XTheadvector_and_Vector?= X-Mailer: [Alimail-Mailagent][W4_0.2.3][v5ForWebDing][Chrome] MIME-Version: 1.0 x-aliyun-im-through: {"mailThroughImNew":true} References: <174C85CC31672D9B+2024010907084358726049@rivai.ai> x-aliyun-mail-creator: W4_0.2.3_v5ForWebDing_SFRTW96aWxsYS81LjAgKFdpbmRvd3MgTlQgMTAuMDsgV2luNjQ7IHg2NCkgQXBwbGVXZWJLaXQvNTM3LjM2IChLSFRNTCwgbGlrZSBHZWNrbykgQ2hyb21lLzEyMC4wLjAuMCBTYWZhcmkvNTM3LjM2IEVkZy8xMjAuMC4wLjA=Ch In-Reply-To: <174C85CC31672D9B+2024010907084358726049@rivai.ai> X-Spam-Status: No, score=-19.4 required=5.0 tests=BAYES_00, BODY_8BITS, ENV_AND_HDR_SPF_MATCH, GIT_PATCH_0, KAM_DMARC_STATUS, KAM_SHORT, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE, UNPARSEABLE_RELAY, UPPERCASE_50_75, USER_IN_DEF_SPF_WL autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-To: joshua Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1786588682693037270 X-GMAIL-MSGID: 1787577188141356484 For the vsetvl issue, we have discussed last week. Maybe riscv_asm_output function cannot return instructions like riscv_output_move. The briefest approach may be to add some logic in the vsetvl patterns. Only 3 patterns need to be modified and that will not be too invasive. ------------------------------------------------------------------ 发件人：钟居哲 发送时间：2024年1月9日(星期二) 07:08 收件人："cooper.joshua"; "gcc-patches" 抄　送："jim.wilson.gcc"; palmer; andrew; "philipp.tomsich"; Jeff Law; "Christoph Müllner"; "cooper.joshua"; jinma; Cooper Qu 主　题：Re: [PATCH v4] RISC-V: Handle differences between XTheadvector and Vector -  return TAIL_ANY; +  return TARGET_XTHEADVECTOR ? TAIL_AGNOSTIC : TAIL_ANY; -  return MASK_ANY; +  return TARGET_XTHEADVECTOR ? MASK_UNDISTURBED : MASK_ANY; You shouldn't change this. -  "vset%i1vli\t%0,%1,e%2,%m3,t%p4,m%p5" +  { return TARGET_XTHEADVECTOR ? "vsetvli\t%0,%1,e%2,%m3" : "vset%i1vli\t%0,%1,e%2,%m3,t%p4,m%p5"; } I prefer do it in ASM_OUTPUT +   Copyright (C) 2022-2023 Free Software Foundation, Inc. Copyright is not correct. juzhe.zhong@rivai.ai   From: Jun Sha (Joshua) Date: 2024-01-03 14:15 To: gcc-patches CC: jim.wilson.gcc; palmer; andrew; philipp.tomsich; jeffreyalaw; christoph.muellner; juzhe.zhong; Jun Sha (Joshua); Jin Ma; Xianmiao Qu Subject: [PATCH v4] RISC-V: Handle differences between XTheadvector and Vector This patch is to handle the differences in instruction generation between Vector and XTheadVector. In this version, we only support partial xtheadvector instructions that leverage directly from current RVV1.0 with simple adding "th." prefix. For different name xtheadvector instructions but share same patterns as RVV1.0 instructions, we will use ASM targethook to rewrite the whole string of the instructions in the following patches.   For some vector patterns that cannot be avoided, we use "!TARGET_XTHEADVECTOR" to disable them in vector.md in order not to generate instructions that xtheadvector does not support, like vmv1r and vsext.vf2.   gcc/ChangeLog:   * config.gcc:  Add files for XTheadVector intrinsics. * config/riscv/autovec.md: Guard XTheadVector. * config/riscv/riscv-c.cc: Add pragma for XTheadVector. * config/riscv/riscv-string.cc (expand_block_move): Guard XTheadVector. (get_prefer_tail_policy): Give specific value for tail. (get_prefer_mask_policy): Give specific value for mask. (vls_mode_valid_p): Avoid autovec. * config/riscv/riscv-vector-builtins-shapes.cc (check_type): (build_one): New function. * config/riscv/riscv-vector-builtins.cc (DEF_RVV_FUNCTION): (DEF_THEAD_RVV_FUNCTION): Add new marcos. (check_required_extensions): (handle_pragma_vector): * config/riscv/riscv-vector-builtins.h (RVV_REQUIRE_VECTOR): (RVV_REQUIRE_XTHEADVECTOR): Add RVV_REQUIRE_VECTOR and RVV_REQUIRE_XTHEADVECTOR. (struct function_group_info): * config/riscv/riscv-vector-switch.def (ENTRY): Disable fractional mode for the XTheadVector extension. (TUPLE_ENTRY): Likewise. * config/riscv/riscv-vsetvl.cc: Add functions for xtheadvector. * config/riscv/riscv.cc (riscv_v_ext_vls_mode_p): Guard XTheadVector. (riscv_v_adjust_bytesize): Likewise. (riscv_preferred_simd_mode): Likewsie. (riscv_autovectorize_vector_modes): Likewise. (riscv_vector_mode_supported_any_target_p): Likewise. (TARGET_VECTOR_MODE_SUPPORTED_ANY_TARGET_P): Likewise. * config/riscv/vector-iterators.md: Remove fractional LMUL. * config/riscv/vector.md: Include thead-vector.md. * config/riscv/riscv_th_vector.h: New file. * config/riscv/thead-vector.md: New file.   gcc/testsuite/ChangeLog:   * gcc.target/riscv/rvv/base/pragma-1.c: Add XTheadVector. * gcc.target/riscv/rvv/base/abi-1.c: Exclude XTheadVector. * lib/target-supports.exp: Add target for XTheadVector.   Co-authored-by: Jin Ma Co-authored-by: Xianmiao Qu Co-authored-by: Christoph Müllner --- gcc/config.gcc                                |   2 +- gcc/config/riscv/autovec.md                   |   2 +- gcc/config/riscv/predicates.md                |   4 +- gcc/config/riscv/riscv-c.cc                   |   3 +- gcc/config/riscv/riscv-string.cc              |   3 +- gcc/config/riscv/riscv-v.cc                   |   6 +- .../riscv/riscv-vector-builtins-bases.cc      |  48 +++-- .../riscv/riscv-vector-builtins-shapes.cc     |  23 +++ gcc/config/riscv/riscv-vector-switch.def      | 150 +++++++------- gcc/config/riscv/riscv.cc                     |  20 +- gcc/config/riscv/riscv_th_vector.h            |  49 +++++ gcc/config/riscv/thead-vector.md              |  69 +++++++ gcc/config/riscv/vector-iterators.md          | 186 +++++++++--------- gcc/config/riscv/vector.md                    |  55 ++++-- .../gcc.target/riscv/rvv/base/abi-1.c         |   2 +- .../gcc.target/riscv/rvv/base/pragma-1.c      |   2 +- gcc/testsuite/lib/target-supports.exp         |  12 ++ 17 files changed, 427 insertions(+), 209 deletions(-) create mode 100644 gcc/config/riscv/riscv_th_vector.h create mode 100644 gcc/config/riscv/thead-vector.md diff --git a/gcc/config.gcc b/gcc/config.gcc index f0676c830e8..1445d98c147 100644 --- a/gcc/config.gcc +++ b/gcc/config.gcc @@ -549,7 +549,7 @@ riscv*) extra_objs="${extra_objs} riscv-vector-builtins.o riscv-vector-builtins-shapes.o riscv-vector-builtins-bases.o" extra_objs="${extra_objs} thead.o riscv-target-attr.o" d_target_objs="riscv-d.o" - extra_headers="riscv_vector.h" + extra_headers="riscv_vector.h riscv_th_vector.h" target_gtfiles="$target_gtfiles \$(srcdir)/config/riscv/riscv-vector-builtins.cc" target_gtfiles="$target_gtfiles \$(srcdir)/config/riscv/riscv-vector-builtins.h" ;; diff --git a/gcc/config/riscv/autovec.md b/gcc/config/riscv/autovec.md index 8b8a92f10a1..1fac56c7095 100644 --- a/gcc/config/riscv/autovec.md +++ b/gcc/config/riscv/autovec.md @@ -2579,7 +2579,7 @@    [(match_operand      0 "register_operand")     (match_operand      1 "memory_operand")     (match_operand:ANYI 2 "const_int_operand")] -  "TARGET_VECTOR" +  "TARGET_VECTOR && !TARGET_XTHEADVECTOR"    {      riscv_vector::expand_rawmemchr(mode, operands[0], operands[1],    operands[2]); diff --git a/gcc/config/riscv/predicates.md b/gcc/config/riscv/predicates.md index b87a6900841..6e36c5afae1 100644 --- a/gcc/config/riscv/predicates.md +++ b/gcc/config/riscv/predicates.md @@ -428,7 +428,9 @@ ;; Predicates for the V extension. (define_special_predicate "vector_length_operand"    (ior (match_operand 0 "pmode_register_operand") -       (match_operand 0 "const_csr_operand"))) +       (and (ior (match_test "TARGET_XTHEADVECTOR && rtx_equal_p (op, const0_rtx)") + (match_test "!TARGET_XTHEADVECTOR")) +    (match_operand 0 "const_csr_operand")))) (define_special_predicate "autovec_length_operand"    (ior (match_operand 0 "pmode_register_operand") diff --git a/gcc/config/riscv/riscv-c.cc b/gcc/config/riscv/riscv-c.cc index d290c58613a..d6fb83ac00c 100644 --- a/gcc/config/riscv/riscv-c.cc +++ b/gcc/config/riscv/riscv-c.cc @@ -195,7 +195,8 @@ riscv_pragma_intrinsic (cpp_reader *)    const char *name = TREE_STRING_POINTER (x); -  if (strcmp (name, "vector") == 0) +  if (strcmp (name, "vector") == 0 +      || strcmp (name, "xtheadvector") == 0)      {        if (!TARGET_VECTOR) { diff --git a/gcc/config/riscv/riscv-string.cc b/gcc/config/riscv/riscv-string.cc index 11c1f74d0b3..f431b562222 100644 --- a/gcc/config/riscv/riscv-string.cc +++ b/gcc/config/riscv/riscv-string.cc @@ -773,7 +773,8 @@ riscv_expand_block_move_scalar (rtx dest, rtx src, rtx length) bool riscv_expand_block_move (rtx dest, rtx src, rtx length) { -  if (TARGET_VECTOR && stringop_strategy & STRATEGY_VECTOR) +  if ((TARGET_VECTOR && !TARGET_XTHEADVECTOR) +      && stringop_strategy & STRATEGY_VECTOR)      {        bool ok = riscv_vector::expand_block_move (dest, src, length);        if (ok) diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc index 038ab084a37..eb061b593a5 100644 --- a/gcc/config/riscv/riscv-v.cc +++ b/gcc/config/riscv/riscv-v.cc @@ -1772,7 +1772,7 @@ get_prefer_tail_policy ()       compiler pick up either agnostic or undisturbed. Maybe we       will have a compile option like -mprefer=agnostic to set       this value???.  */ -  return TAIL_ANY; +  return TARGET_XTHEADVECTOR ? TAIL_AGNOSTIC : TAIL_ANY; } /* Get prefer mask policy.  */ @@ -1783,7 +1783,7 @@ get_prefer_mask_policy ()       compiler pick up either agnostic or undisturbed. Maybe we       will have a compile option like -mprefer=agnostic to set       this value???.  */ -  return MASK_ANY; +  return TARGET_XTHEADVECTOR ? MASK_UNDISTURBED : MASK_ANY; } /* Get avl_type rtx.  */ @@ -4383,7 +4383,7 @@ cmp_lmul_gt_one (machine_mode mode) bool vls_mode_valid_p (machine_mode vls_mode) { -  if (!TARGET_VECTOR) +  if (!TARGET_VECTOR || TARGET_XTHEADVECTOR)      return false;    if (riscv_autovec_preference == RVV_SCALABLE) diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.cc b/gcc/config/riscv/riscv-vector-builtins-bases.cc index c51affde353..22d877af9be 100644 --- a/gcc/config/riscv/riscv-vector-builtins-bases.cc +++ b/gcc/config/riscv/riscv-vector-builtins-bases.cc @@ -115,23 +115,37 @@ public:      tree type = builtin_types[e.type.index].vector;      machine_mode mode = TYPE_MODE (type); -    /* Normalize same RATO (SEW/LMUL) into same vsetvl instruction. - - - e8,mf8/e16,mf4/e32,mf2/e64,m1 --> e8mf8 - - e8,mf4/e16,mf2/e32,m1/e64,m2  --> e8mf4 - - e8,mf2/e16,m1/e32,m2/e64,m4   --> e8mf2 - - e8,m1/e16,m2/e32,m4/e64,m8    --> e8m1 - - e8,m2/e16,m4/e32,m8           --> e8m2 - - e8,m4/e16,m8                  --> e8m4 - - e8,m8                         --> e8m8 -    */ -    /* SEW.  */ -    e.add_input_operand (Pmode, gen_int_mode (8, Pmode)); - -    /* LMUL.  */ -    machine_mode e8_mode -      = get_vector_mode (QImode, GET_MODE_NUNITS (mode)).require (); -    e.add_input_operand (Pmode, gen_int_mode (get_vlmul (e8_mode), Pmode)); + +    if (TARGET_XTHEADVECTOR) +      { + machine_mode inner_mode = GET_MODE_INNER (mode); + /* SEW.  */ + e.add_input_operand (Pmode, +   gen_int_mode (GET_MODE_BITSIZE (inner_mode), Pmode)); + /* LMUL.  */ + e.add_input_operand (Pmode, +   gen_int_mode (get_vlmul (mode), Pmode)); +      } +    else +      { + /* Normalize same RATO (SEW/LMUL) into same vsetvl instruction. + +      - e8,mf8/e16,mf4/e32,mf2/e64,m1 --> e8mf8 +      - e8,mf4/e16,mf2/e32,m1/e64,m2  --> e8mf4 +      - e8,mf2/e16,m1/e32,m2/e64,m4   --> e8mf2 +      - e8,m1/e16,m2/e32,m4/e64,m8    --> e8m1 +      - e8,m2/e16,m4/e32,m8           --> e8m2 +      - e8,m4/e16,m8                  --> e8m4 +      - e8,m8                         --> e8m8 + */ + /* SEW.  */ + e.add_input_operand (Pmode, gen_int_mode (8, Pmode)); + + /* LMUL.  */ + machine_mode e8_mode +   = get_vector_mode (QImode, GET_MODE_NUNITS (mode)).require (); + e.add_input_operand (Pmode, gen_int_mode (get_vlmul (e8_mode), Pmode)); +      }      /* TAIL_ANY.  */      e.add_input_operand (Pmode, diff --git a/gcc/config/riscv/riscv-vector-builtins-shapes.cc b/gcc/config/riscv/riscv-vector-builtins-shapes.cc index 4a754e0228f..6b49404a1fa 100644 --- a/gcc/config/riscv/riscv-vector-builtins-shapes.cc +++ b/gcc/config/riscv/riscv-vector-builtins-shapes.cc @@ -33,6 +33,25 @@ namespace riscv_vector { +/* Check whether the RETURN_TYPE and ARGUMENT_TYPES are +   valid for the function.  */ + +static bool +check_type (tree return_type, vec &argument_types) +{ +  tree arg; +  unsigned i; + +  if (!return_type) +    return false; + +  FOR_EACH_VEC_ELT (argument_types, i, arg) +    if (!arg) +      return false; + +  return true; +} + /* Add one function instance for GROUP, using operand suffix at index OI,     mode suffix at index PAIR && bi and predication suffix at index pred_idx.  */ static void @@ -49,6 +68,10 @@ build_one (function_builder &b, const function_group_info &group,      group.ops_infos.types[vec_type_idx].index);    b.allocate_argument_types (function_instance, argument_types);    b.apply_predication (function_instance, return_type, argument_types); + +  if (TARGET_XTHEADVECTOR && !check_type (return_type, argument_types)) +    return; +    b.add_overloaded_function (function_instance, *group.shape);    b.add_unique_function (function_instance, (*group.shape), return_type, argument_types); diff --git a/gcc/config/riscv/riscv-vector-switch.def b/gcc/config/riscv/riscv-vector-switch.def index 5c9f9bcbc3e..f7a66b34bae 100644 --- a/gcc/config/riscv/riscv-vector-switch.def +++ b/gcc/config/riscv/riscv-vector-switch.def @@ -68,9 +68,9 @@ Encode the ratio of SEW/LMUL into the mask types. #endif /* Disable modes if TARGET_MIN_VLEN == 32.  */ -ENTRY (RVVMF64BI, TARGET_MIN_VLEN > 32, LMUL_F8, 64) -ENTRY (RVVMF32BI, true, LMUL_F4, 32) -ENTRY (RVVMF16BI, true, LMUL_F2, 16) +ENTRY (RVVMF64BI, TARGET_MIN_VLEN > 32, TARGET_XTHEADVECTOR ? LMUL_1 :LMUL_F8, 64) +ENTRY (RVVMF32BI, true, TARGET_XTHEADVECTOR ? LMUL_1 :LMUL_F4, 32) +ENTRY (RVVMF16BI, true, TARGET_XTHEADVECTOR ? LMUL_1 : LMUL_F2 , 16) ENTRY (RVVMF8BI, true, LMUL_1, 8) ENTRY (RVVMF4BI, true, LMUL_2, 4) ENTRY (RVVMF2BI, true, LMUL_4, 2) @@ -81,39 +81,39 @@ ENTRY (RVVM8QI, true, LMUL_8, 1) ENTRY (RVVM4QI, true, LMUL_4, 2) ENTRY (RVVM2QI, true, LMUL_2, 4) ENTRY (RVVM1QI, true, LMUL_1, 8) -ENTRY (RVVMF2QI, true, LMUL_F2, 16) -ENTRY (RVVMF4QI, true, LMUL_F4, 32) -ENTRY (RVVMF8QI, TARGET_MIN_VLEN > 32, LMUL_F8, 64) +ENTRY (RVVMF2QI, !TARGET_XTHEADVECTOR, LMUL_F2, 16) +ENTRY (RVVMF4QI, !TARGET_XTHEADVECTOR, LMUL_F4, 32) +ENTRY (RVVMF8QI, TARGET_MIN_VLEN > 32 && !TARGET_XTHEADVECTOR, LMUL_F8, 64) /* Disable modes if TARGET_MIN_VLEN == 32.  */ ENTRY (RVVM8HI, true, LMUL_8, 2) ENTRY (RVVM4HI, true, LMUL_4, 4) ENTRY (RVVM2HI, true, LMUL_2, 8) ENTRY (RVVM1HI, true, LMUL_1, 16) -ENTRY (RVVMF2HI, true, LMUL_F2, 32) -ENTRY (RVVMF4HI, TARGET_MIN_VLEN > 32, LMUL_F4, 64) +ENTRY (RVVMF2HI, !TARGET_XTHEADVECTOR, LMUL_F2, 32) +ENTRY (RVVMF4HI, TARGET_MIN_VLEN > 32 && !TARGET_XTHEADVECTOR, LMUL_F4, 64) /* Disable modes if TARGET_MIN_VLEN == 32 or !TARGET_VECTOR_ELEN_FP_16.  */ ENTRY (RVVM8HF, TARGET_VECTOR_ELEN_FP_16, LMUL_8, 2) ENTRY (RVVM4HF, TARGET_VECTOR_ELEN_FP_16, LMUL_4, 4) ENTRY (RVVM2HF, TARGET_VECTOR_ELEN_FP_16, LMUL_2, 8) ENTRY (RVVM1HF, TARGET_VECTOR_ELEN_FP_16, LMUL_1, 16) -ENTRY (RVVMF2HF, TARGET_VECTOR_ELEN_FP_16, LMUL_F2, 32) -ENTRY (RVVMF4HF, TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN > 32, LMUL_F4, 64) +ENTRY (RVVMF2HF, TARGET_VECTOR_ELEN_FP_16 && !TARGET_XTHEADVECTOR, LMUL_F2, 32) +ENTRY (RVVMF4HF, TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN > 32 && !TARGET_XTHEADVECTOR, LMUL_F4, 64) /* Disable modes if TARGET_MIN_VLEN == 32.  */ ENTRY (RVVM8SI, true, LMUL_8, 4) ENTRY (RVVM4SI, true, LMUL_4, 8) ENTRY (RVVM2SI, true, LMUL_2, 16) ENTRY (RVVM1SI, true, LMUL_1, 32) -ENTRY (RVVMF2SI, TARGET_MIN_VLEN > 32, LMUL_F2, 64) +ENTRY (RVVMF2SI, TARGET_MIN_VLEN > 32 && !TARGET_XTHEADVECTOR, LMUL_F2, 64) /* Disable modes if TARGET_MIN_VLEN == 32 or !TARGET_VECTOR_ELEN_FP_32.  */ ENTRY (RVVM8SF, TARGET_VECTOR_ELEN_FP_32, LMUL_8, 4) ENTRY (RVVM4SF, TARGET_VECTOR_ELEN_FP_32, LMUL_4, 8) ENTRY (RVVM2SF, TARGET_VECTOR_ELEN_FP_32, LMUL_2, 16) ENTRY (RVVM1SF, TARGET_VECTOR_ELEN_FP_32, LMUL_1, 32) -ENTRY (RVVMF2SF, TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32, LMUL_F2, 64) +ENTRY (RVVMF2SF, TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32 && !TARGET_XTHEADVECTOR, LMUL_F2, 64) /* Disable modes if !TARGET_VECTOR_ELEN_64.  */ ENTRY (RVVM8DI, TARGET_VECTOR_ELEN_64, LMUL_8, 8) @@ -140,127 +140,127 @@ ENTRY (RVVM1DF, TARGET_VECTOR_ELEN_FP_64, LMUL_1, 64) #endif TUPLE_ENTRY (RVVM1x8QI, true, RVVM1QI, 8, LMUL_1, 8) -TUPLE_ENTRY (RVVMF2x8QI, true, RVVMF2QI, 8, LMUL_F2, 16) -TUPLE_ENTRY (RVVMF4x8QI, true, RVVMF4QI, 8, LMUL_F4, 32) -TUPLE_ENTRY (RVVMF8x8QI, TARGET_MIN_VLEN > 32, RVVMF8QI, 8, LMUL_F8, 64) +TUPLE_ENTRY (RVVMF2x8QI, !TARGET_XTHEADVECTOR, RVVMF2QI, 8, LMUL_F2, 16) +TUPLE_ENTRY (RVVMF4x8QI, !TARGET_XTHEADVECTOR, RVVMF4QI, 8, LMUL_F4, 32) +TUPLE_ENTRY (RVVMF8x8QI, TARGET_MIN_VLEN > 32 && !TARGET_XTHEADVECTOR, RVVMF8QI, 8, LMUL_F8, 64) TUPLE_ENTRY (RVVM1x7QI, true, RVVM1QI, 7, LMUL_1, 8) -TUPLE_ENTRY (RVVMF2x7QI, true, RVVMF2QI, 7, LMUL_F2, 16) -TUPLE_ENTRY (RVVMF4x7QI, true, RVVMF4QI, 7, LMUL_F4, 32) -TUPLE_ENTRY (RVVMF8x7QI, TARGET_MIN_VLEN > 32, RVVMF8QI, 7, LMUL_F8, 64) +TUPLE_ENTRY (RVVMF2x7QI, !TARGET_XTHEADVECTOR, RVVMF2QI, 7, LMUL_F2, 16) +TUPLE_ENTRY (RVVMF4x7QI, !TARGET_XTHEADVECTOR, RVVMF4QI, 7, LMUL_F4, 32) +TUPLE_ENTRY (RVVMF8x7QI, TARGET_MIN_VLEN > 32 && !TARGET_XTHEADVECTOR, RVVMF8QI, 7, LMUL_F8, 64) TUPLE_ENTRY (RVVM1x6QI, true, RVVM1QI, 6, LMUL_1, 8) -TUPLE_ENTRY (RVVMF2x6QI, true, RVVMF2QI, 6, LMUL_F2, 16) -TUPLE_ENTRY (RVVMF4x6QI, true, RVVMF4QI, 6, LMUL_F4, 32) -TUPLE_ENTRY (RVVMF8x6QI, TARGET_MIN_VLEN > 32, RVVMF8QI, 6, LMUL_F8, 64) +TUPLE_ENTRY (RVVMF2x6QI, !TARGET_XTHEADVECTOR, RVVMF2QI, 6, LMUL_F2, 16) +TUPLE_ENTRY (RVVMF4x6QI, !TARGET_XTHEADVECTOR, RVVMF4QI, 6, LMUL_F4, 32) +TUPLE_ENTRY (RVVMF8x6QI, TARGET_MIN_VLEN > 32 && !TARGET_XTHEADVECTOR, RVVMF8QI, 6, LMUL_F8, 64) TUPLE_ENTRY (RVVM1x5QI, true, RVVM1QI, 5, LMUL_1, 8) -TUPLE_ENTRY (RVVMF2x5QI, true, RVVMF2QI, 5, LMUL_F2, 16) -TUPLE_ENTRY (RVVMF4x5QI, true, RVVMF4QI, 5, LMUL_F4, 32) -TUPLE_ENTRY (RVVMF8x5QI, TARGET_MIN_VLEN > 32, RVVMF8QI, 5, LMUL_F8, 64) +TUPLE_ENTRY (RVVMF2x5QI, !TARGET_XTHEADVECTOR, RVVMF2QI, 5, LMUL_F2, 16) +TUPLE_ENTRY (RVVMF4x5QI, !TARGET_XTHEADVECTOR, RVVMF4QI, 5, LMUL_F4, 32) +TUPLE_ENTRY (RVVMF8x5QI, TARGET_MIN_VLEN > 32 && !TARGET_XTHEADVECTOR, RVVMF8QI, 5, LMUL_F8, 64) TUPLE_ENTRY (RVVM2x4QI, true, RVVM2QI, 4, LMUL_2, 4) TUPLE_ENTRY (RVVM1x4QI, true, RVVM1QI, 4, LMUL_1, 8) -TUPLE_ENTRY (RVVMF2x4QI, true, RVVMF2QI, 4, LMUL_F2, 16) -TUPLE_ENTRY (RVVMF4x4QI, true, RVVMF4QI, 4, LMUL_F4, 32) -TUPLE_ENTRY (RVVMF8x4QI, TARGET_MIN_VLEN > 32, RVVMF8QI, 4, LMUL_F8, 64) +TUPLE_ENTRY (RVVMF2x4QI, !TARGET_XTHEADVECTOR, RVVMF2QI, 4, LMUL_F2, 16) +TUPLE_ENTRY (RVVMF4x4QI, !TARGET_XTHEADVECTOR, RVVMF4QI, 4, LMUL_F4, 32) +TUPLE_ENTRY (RVVMF8x4QI, TARGET_MIN_VLEN > 32 && !TARGET_XTHEADVECTOR, RVVMF8QI, 4, LMUL_F8, 64) TUPLE_ENTRY (RVVM2x3QI, true, RVVM2QI, 3, LMUL_2, 4) TUPLE_ENTRY (RVVM1x3QI, true, RVVM1QI, 3, LMUL_1, 8) -TUPLE_ENTRY (RVVMF2x3QI, true, RVVMF2QI, 3, LMUL_F2, 16) -TUPLE_ENTRY (RVVMF4x3QI, true, RVVMF4QI, 3, LMUL_F4, 32) -TUPLE_ENTRY (RVVMF8x3QI, TARGET_MIN_VLEN > 32, RVVMF8QI, 3, LMUL_F8, 64) +TUPLE_ENTRY (RVVMF2x3QI, !TARGET_XTHEADVECTOR, RVVMF2QI, 3, LMUL_F2, 16) +TUPLE_ENTRY (RVVMF4x3QI, !TARGET_XTHEADVECTOR, RVVMF4QI, 3, LMUL_F4, 32) +TUPLE_ENTRY (RVVMF8x3QI, TARGET_MIN_VLEN > 32 && !TARGET_XTHEADVECTOR, RVVMF8QI, 3, LMUL_F8, 64) TUPLE_ENTRY (RVVM4x2QI, true, RVVM4QI, 2, LMUL_4, 2) TUPLE_ENTRY (RVVM2x2QI, true, RVVM2QI, 2, LMUL_2, 4) TUPLE_ENTRY (RVVM1x2QI, true, RVVM1QI, 2, LMUL_1, 8) -TUPLE_ENTRY (RVVMF2x2QI, true, RVVMF2QI, 2, LMUL_F2, 16) -TUPLE_ENTRY (RVVMF4x2QI, true, RVVMF4QI, 2, LMUL_F4, 32) -TUPLE_ENTRY (RVVMF8x2QI, TARGET_MIN_VLEN > 32, RVVMF8QI, 2, LMUL_F8, 64) +TUPLE_ENTRY (RVVMF2x2QI, !TARGET_XTHEADVECTOR, RVVMF2QI, 2, LMUL_F2, 16) +TUPLE_ENTRY (RVVMF4x2QI, !TARGET_XTHEADVECTOR, RVVMF4QI, 2, LMUL_F4, 32) +TUPLE_ENTRY (RVVMF8x2QI, TARGET_MIN_VLEN > 32 && !TARGET_XTHEADVECTOR, RVVMF8QI, 2, LMUL_F8, 64) TUPLE_ENTRY (RVVM1x8HI, true, RVVM1HI, 8, LMUL_1, 16) -TUPLE_ENTRY (RVVMF2x8HI, true, RVVMF2HI, 8, LMUL_F2, 32) -TUPLE_ENTRY (RVVMF4x8HI, TARGET_MIN_VLEN > 32, RVVMF4HI, 8, LMUL_F4, 64) +TUPLE_ENTRY (RVVMF2x8HI, !TARGET_XTHEADVECTOR, RVVMF2HI, 8, LMUL_F2, 32) +TUPLE_ENTRY (RVVMF4x8HI, TARGET_MIN_VLEN > 32 && !TARGET_XTHEADVECTOR, RVVMF4HI, 8, LMUL_F4, 64) TUPLE_ENTRY (RVVM1x7HI, true, RVVM1HI, 7, LMUL_1, 16) -TUPLE_ENTRY (RVVMF2x7HI, true, RVVMF2HI, 7, LMUL_F2, 32) -TUPLE_ENTRY (RVVMF4x7HI, TARGET_MIN_VLEN > 32, RVVMF4HI, 7, LMUL_F4, 64) +TUPLE_ENTRY (RVVMF2x7HI, !TARGET_XTHEADVECTOR, RVVMF2HI, 7, LMUL_F2, 32) +TUPLE_ENTRY (RVVMF4x7HI, TARGET_MIN_VLEN > 32 && !TARGET_XTHEADVECTOR, RVVMF4HI, 7, LMUL_F4, 64) TUPLE_ENTRY (RVVM1x6HI, true, RVVM1HI, 6, LMUL_1, 16) -TUPLE_ENTRY (RVVMF2x6HI, true, RVVMF2HI, 6, LMUL_F2, 32) -TUPLE_ENTRY (RVVMF4x6HI, TARGET_MIN_VLEN > 32, RVVMF4HI, 6, LMUL_F4, 64) +TUPLE_ENTRY (RVVMF2x6HI, !TARGET_XTHEADVECTOR, RVVMF2HI, 6, LMUL_F2, 32) +TUPLE_ENTRY (RVVMF4x6HI, TARGET_MIN_VLEN > 32 && !TARGET_XTHEADVECTOR, RVVMF4HI, 6, LMUL_F4, 64) TUPLE_ENTRY (RVVM1x5HI, true, RVVM1HI, 5, LMUL_1, 16) -TUPLE_ENTRY (RVVMF2x5HI, true, RVVMF2HI, 5, LMUL_F2, 32) -TUPLE_ENTRY (RVVMF4x5HI, TARGET_MIN_VLEN > 32, RVVMF4HI, 5, LMUL_F4, 64) +TUPLE_ENTRY (RVVMF2x5HI, !TARGET_XTHEADVECTOR, RVVMF2HI, 5, LMUL_F2, 32) +TUPLE_ENTRY (RVVMF4x5HI, TARGET_MIN_VLEN > 32 && !TARGET_XTHEADVECTOR, RVVMF4HI, 5, LMUL_F4, 64) TUPLE_ENTRY (RVVM2x4HI, true, RVVM2HI, 4, LMUL_2, 8) TUPLE_ENTRY (RVVM1x4HI, true, RVVM1HI, 4, LMUL_1, 16) -TUPLE_ENTRY (RVVMF2x4HI, true, RVVMF2HI, 4, LMUL_F2, 32) -TUPLE_ENTRY (RVVMF4x4HI, TARGET_MIN_VLEN > 32, RVVMF4HI, 4, LMUL_F4, 64) +TUPLE_ENTRY (RVVMF2x4HI, !TARGET_XTHEADVECTOR, RVVMF2HI, 4, LMUL_F2, 32) +TUPLE_ENTRY (RVVMF4x4HI, TARGET_MIN_VLEN > 32 && !TARGET_XTHEADVECTOR, RVVMF4HI, 4, LMUL_F4, 64) TUPLE_ENTRY (RVVM2x3HI, true, RVVM2HI, 3, LMUL_2, 8) TUPLE_ENTRY (RVVM1x3HI, true, RVVM1HI, 3, LMUL_1, 16) -TUPLE_ENTRY (RVVMF2x3HI, true, RVVMF2HI, 3, LMUL_F2, 32) -TUPLE_ENTRY (RVVMF4x3HI, TARGET_MIN_VLEN > 32, RVVMF4HI, 3, LMUL_F4, 64) +TUPLE_ENTRY (RVVMF2x3HI, !TARGET_XTHEADVECTOR, RVVMF2HI, 3, LMUL_F2, 32) +TUPLE_ENTRY (RVVMF4x3HI, TARGET_MIN_VLEN > 32 && !TARGET_XTHEADVECTOR, RVVMF4HI, 3, LMUL_F4, 64) TUPLE_ENTRY (RVVM4x2HI, true, RVVM4HI, 2, LMUL_4, 4) TUPLE_ENTRY (RVVM2x2HI, true, RVVM2HI, 2, LMUL_2, 8) TUPLE_ENTRY (RVVM1x2HI, true, RVVM1HI, 2, LMUL_1, 16) -TUPLE_ENTRY (RVVMF2x2HI, true, RVVMF2HI, 2, LMUL_F2, 32) -TUPLE_ENTRY (RVVMF4x2HI, TARGET_MIN_VLEN > 32, RVVMF4HI, 2, LMUL_F4, 64) +TUPLE_ENTRY (RVVMF2x2HI, !TARGET_XTHEADVECTOR, RVVMF2HI, 2, LMUL_F2, 32) +TUPLE_ENTRY (RVVMF4x2HI, TARGET_MIN_VLEN > 32 && !TARGET_XTHEADVECTOR, RVVMF4HI, 2, LMUL_F4, 64) TUPLE_ENTRY (RVVM1x8HF, TARGET_VECTOR_ELEN_FP_16, RVVM1HF, 8, LMUL_1, 16) -TUPLE_ENTRY (RVVMF2x8HF, TARGET_VECTOR_ELEN_FP_16, RVVMF2HF, 8, LMUL_F2, 32) -TUPLE_ENTRY (RVVMF4x8HF, TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN > 32, RVVMF4HF, 8, LMUL_F4, 64) +TUPLE_ENTRY (RVVMF2x8HF, TARGET_VECTOR_ELEN_FP_16 && !TARGET_XTHEADVECTOR, RVVMF2HF, 8, LMUL_F2, 32) +TUPLE_ENTRY (RVVMF4x8HF, TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN > 32 && !TARGET_XTHEADVECTOR, RVVMF4HF, 8, LMUL_F4, 64) TUPLE_ENTRY (RVVM1x7HF, TARGET_VECTOR_ELEN_FP_16, RVVM1HF, 7, LMUL_1, 16) -TUPLE_ENTRY (RVVMF2x7HF, TARGET_VECTOR_ELEN_FP_16, RVVMF2HF, 7, LMUL_F2, 32) -TUPLE_ENTRY (RVVMF4x7HF, TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN > 32, RVVMF4HF, 7, LMUL_F4, 64) +TUPLE_ENTRY (RVVMF2x7HF, TARGET_VECTOR_ELEN_FP_16 && !TARGET_XTHEADVECTOR, RVVMF2HF, 7, LMUL_F2, 32) +TUPLE_ENTRY (RVVMF4x7HF, TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN > 32 && !TARGET_XTHEADVECTOR, RVVMF4HF, 7, LMUL_F4, 64) TUPLE_ENTRY (RVVM1x6HF, TARGET_VECTOR_ELEN_FP_16, RVVM1HF, 6, LMUL_1, 16) -TUPLE_ENTRY (RVVMF2x6HF, TARGET_VECTOR_ELEN_FP_16, RVVMF2HF, 6, LMUL_F2, 32) -TUPLE_ENTRY (RVVMF4x6HF, TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN > 32, RVVMF4HF, 6, LMUL_F4, 64) +TUPLE_ENTRY (RVVMF2x6HF, TARGET_VECTOR_ELEN_FP_16 && !TARGET_XTHEADVECTOR, RVVMF2HF, 6, LMUL_F2, 32) +TUPLE_ENTRY (RVVMF4x6HF, TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN > 32 && !TARGET_XTHEADVECTOR, RVVMF4HF, 6, LMUL_F4, 64) TUPLE_ENTRY (RVVM1x5HF, TARGET_VECTOR_ELEN_FP_16, RVVM1HF, 5, LMUL_1, 16) -TUPLE_ENTRY (RVVMF2x5HF, TARGET_VECTOR_ELEN_FP_16, RVVMF2HF, 5, LMUL_F2, 32) -TUPLE_ENTRY (RVVMF4x5HF, TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN > 32, RVVMF4HF, 5, LMUL_F4, 64) +TUPLE_ENTRY (RVVMF2x5HF, TARGET_VECTOR_ELEN_FP_16 && !TARGET_XTHEADVECTOR, RVVMF2HF, 5, LMUL_F2, 32) +TUPLE_ENTRY (RVVMF4x5HF, TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN > 32 && !TARGET_XTHEADVECTOR, RVVMF4HF, 5, LMUL_F4, 64) TUPLE_ENTRY (RVVM2x4HF, TARGET_VECTOR_ELEN_FP_16, RVVM2HF, 4, LMUL_2, 8) TUPLE_ENTRY (RVVM1x4HF, TARGET_VECTOR_ELEN_FP_16, RVVM1HF, 4, LMUL_1, 16) -TUPLE_ENTRY (RVVMF2x4HF, TARGET_VECTOR_ELEN_FP_16, RVVMF2HF, 4, LMUL_F2, 32) -TUPLE_ENTRY (RVVMF4x4HF, TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN > 32, RVVMF4HF, 4, LMUL_F4, 64) +TUPLE_ENTRY (RVVMF2x4HF, TARGET_VECTOR_ELEN_FP_16 && !TARGET_XTHEADVECTOR, RVVMF2HF, 4, LMUL_F2, 32) +TUPLE_ENTRY (RVVMF4x4HF, TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN > 32 && !TARGET_XTHEADVECTOR, RVVMF4HF, 4, LMUL_F4, 64) TUPLE_ENTRY (RVVM2x3HF, TARGET_VECTOR_ELEN_FP_16, RVVM2HF, 3, LMUL_2, 8) TUPLE_ENTRY (RVVM1x3HF, TARGET_VECTOR_ELEN_FP_16, RVVM1HF, 3, LMUL_1, 16) -TUPLE_ENTRY (RVVMF2x3HF, TARGET_VECTOR_ELEN_FP_16, RVVMF2HF, 3, LMUL_F2, 32) -TUPLE_ENTRY (RVVMF4x3HF, TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN > 32, RVVMF4HF, 3, LMUL_F4, 64) +TUPLE_ENTRY (RVVMF2x3HF, TARGET_VECTOR_ELEN_FP_16 && !TARGET_XTHEADVECTOR, RVVMF2HF, 3, LMUL_F2, 32) +TUPLE_ENTRY (RVVMF4x3HF, TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN > 32 && !TARGET_XTHEADVECTOR, RVVMF4HF, 3, LMUL_F4, 64) TUPLE_ENTRY (RVVM4x2HF, TARGET_VECTOR_ELEN_FP_16, RVVM4HF, 2, LMUL_4, 4) TUPLE_ENTRY (RVVM2x2HF, TARGET_VECTOR_ELEN_FP_16, RVVM2HF, 2, LMUL_2, 8) TUPLE_ENTRY (RVVM1x2HF, TARGET_VECTOR_ELEN_FP_16, RVVM1HF, 2, LMUL_1, 16) -TUPLE_ENTRY (RVVMF2x2HF, TARGET_VECTOR_ELEN_FP_16, RVVMF2HF, 2, LMUL_F2, 32) -TUPLE_ENTRY (RVVMF4x2HF, TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN > 32, RVVMF4HF, 2, LMUL_F4, 64) +TUPLE_ENTRY (RVVMF2x2HF, TARGET_VECTOR_ELEN_FP_16 && !TARGET_XTHEADVECTOR, RVVMF2HF, 2, LMUL_F2, 32) +TUPLE_ENTRY (RVVMF4x2HF, TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN > 32 && !TARGET_XTHEADVECTOR, RVVMF4HF, 2, LMUL_F4, 64) TUPLE_ENTRY (RVVM1x8SI, true, RVVM1SI, 8, LMUL_1, 16) -TUPLE_ENTRY (RVVMF2x8SI, TARGET_MIN_VLEN > 32, RVVMF2SI, 8, LMUL_F2, 32) +TUPLE_ENTRY (RVVMF2x8SI, (TARGET_MIN_VLEN > 32) && !TARGET_XTHEADVECTOR, RVVMF2SI, 8, LMUL_F2, 32) TUPLE_ENTRY (RVVM1x7SI, true, RVVM1SI, 7, LMUL_1, 16) -TUPLE_ENTRY (RVVMF2x7SI, TARGET_MIN_VLEN > 32, RVVMF2SI, 7, LMUL_F2, 32) +TUPLE_ENTRY (RVVMF2x7SI, (TARGET_MIN_VLEN > 32) && !TARGET_XTHEADVECTOR, RVVMF2SI, 7, LMUL_F2, 32) TUPLE_ENTRY (RVVM1x6SI, true, RVVM1SI, 6, LMUL_1, 16) -TUPLE_ENTRY (RVVMF2x6SI, TARGET_MIN_VLEN > 32, RVVMF2SI, 6, LMUL_F2, 32) +TUPLE_ENTRY (RVVMF2x6SI, TARGET_MIN_VLEN > 32 && !TARGET_XTHEADVECTOR, RVVMF2SI, 6, LMUL_F2, 32) TUPLE_ENTRY (RVVM1x5SI, true, RVVM1SI, 5, LMUL_1, 16) -TUPLE_ENTRY (RVVMF2x5SI, TARGET_MIN_VLEN > 32, RVVMF2SI, 5, LMUL_F2, 32) +TUPLE_ENTRY (RVVMF2x5SI, TARGET_MIN_VLEN > 32 && !TARGET_XTHEADVECTOR, RVVMF2SI, 5, LMUL_F2, 32) TUPLE_ENTRY (RVVM2x4SI, true, RVVM2SI, 4, LMUL_2, 8) TUPLE_ENTRY (RVVM1x4SI, true, RVVM1SI, 4, LMUL_1, 16) -TUPLE_ENTRY (RVVMF2x4SI, TARGET_MIN_VLEN > 32, RVVMF2SI, 4, LMUL_F2, 32) +TUPLE_ENTRY (RVVMF2x4SI, TARGET_MIN_VLEN > 32 && !TARGET_XTHEADVECTOR, RVVMF2SI, 4, LMUL_F2, 32) TUPLE_ENTRY (RVVM2x3SI, true, RVVM2SI, 3, LMUL_2, 8) TUPLE_ENTRY (RVVM1x3SI, true, RVVM1SI, 3, LMUL_1, 16) -TUPLE_ENTRY (RVVMF2x3SI, TARGET_MIN_VLEN > 32, RVVMF2SI, 3, LMUL_F2, 32) +TUPLE_ENTRY (RVVMF2x3SI, TARGET_MIN_VLEN > 32 && !TARGET_XTHEADVECTOR, RVVMF2SI, 3, LMUL_F2, 32) TUPLE_ENTRY (RVVM4x2SI, true, RVVM4SI, 2, LMUL_4, 4) TUPLE_ENTRY (RVVM2x2SI, true, RVVM2SI, 2, LMUL_2, 8) TUPLE_ENTRY (RVVM1x2SI, true, RVVM1SI, 2, LMUL_1, 16) -TUPLE_ENTRY (RVVMF2x2SI, TARGET_MIN_VLEN > 32, RVVMF2SI, 2, LMUL_F2, 32) +TUPLE_ENTRY (RVVMF2x2SI, TARGET_MIN_VLEN > 32 && !TARGET_XTHEADVECTOR, RVVMF2SI, 2, LMUL_F2, 32) TUPLE_ENTRY (RVVM1x8SF, TARGET_VECTOR_ELEN_FP_32, RVVM1SF, 8, LMUL_1, 16) -TUPLE_ENTRY (RVVMF2x8SF, TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32, RVVMF2SF, 8, LMUL_F2, 32) +TUPLE_ENTRY (RVVMF2x8SF, TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32 && !TARGET_XTHEADVECTOR, RVVMF2SF, 8, LMUL_F2, 32) TUPLE_ENTRY (RVVM1x7SF, TARGET_VECTOR_ELEN_FP_32, RVVM1SF, 7, LMUL_1, 16) -TUPLE_ENTRY (RVVMF2x7SF, TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32, RVVMF2SF, 7, LMUL_F2, 32) +TUPLE_ENTRY (RVVMF2x7SF, TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32 && !TARGET_XTHEADVECTOR, RVVMF2SF, 7, LMUL_F2, 32) TUPLE_ENTRY (RVVM1x6SF, TARGET_VECTOR_ELEN_FP_32, RVVM1SF, 6, LMUL_1, 16) -TUPLE_ENTRY (RVVMF2x6SF, TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32, RVVMF2SF, 6, LMUL_F2, 32) +TUPLE_ENTRY (RVVMF2x6SF, TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32 && !TARGET_XTHEADVECTOR, RVVMF2SF, 6, LMUL_F2, 32) TUPLE_ENTRY (RVVM1x5SF, TARGET_VECTOR_ELEN_FP_32, RVVM1SF, 5, LMUL_1, 16) -TUPLE_ENTRY (RVVMF2x5SF, TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32, RVVMF2SF, 5, LMUL_F2, 32) +TUPLE_ENTRY (RVVMF2x5SF, TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32 && !TARGET_XTHEADVECTOR, RVVMF2SF, 5, LMUL_F2, 32) TUPLE_ENTRY (RVVM2x4SF, TARGET_VECTOR_ELEN_FP_32, RVVM2SF, 4, LMUL_2, 8) TUPLE_ENTRY (RVVM1x4SF, TARGET_VECTOR_ELEN_FP_32, RVVM1SF, 4, LMUL_1, 16) -TUPLE_ENTRY (RVVMF2x4SF, TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32, RVVMF2SF, 4, LMUL_F2, 32) +TUPLE_ENTRY (RVVMF2x4SF, TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32 && !TARGET_XTHEADVECTOR, RVVMF2SF, 4, LMUL_F2, 32) TUPLE_ENTRY (RVVM2x3SF, TARGET_VECTOR_ELEN_FP_32, RVVM2SF, 3, LMUL_2, 8) TUPLE_ENTRY (RVVM1x3SF, TARGET_VECTOR_ELEN_FP_32, RVVM1SF, 3, LMUL_1, 16) -TUPLE_ENTRY (RVVMF2x3SF, TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32, RVVMF2SF, 3, LMUL_F2, 32) +TUPLE_ENTRY (RVVMF2x3SF, TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32 && !TARGET_XTHEADVECTOR, RVVMF2SF, 3, LMUL_F2, 32) TUPLE_ENTRY (RVVM4x2SF, TARGET_VECTOR_ELEN_FP_32, RVVM4SF, 2, LMUL_4, 4) TUPLE_ENTRY (RVVM2x2SF, TARGET_VECTOR_ELEN_FP_32, RVVM2SF, 2, LMUL_2, 8) TUPLE_ENTRY (RVVM1x2SF, TARGET_VECTOR_ELEN_FP_32, RVVM1SF, 2, LMUL_1, 16) -TUPLE_ENTRY (RVVMF2x2SF, TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32, RVVMF2SF, 2, LMUL_F2, 32) +TUPLE_ENTRY (RVVMF2x2SF, TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32 && !TARGET_XTHEADVECTOR, RVVMF2SF, 2, LMUL_F2, 32) TUPLE_ENTRY (RVVM1x8DI, TARGET_VECTOR_ELEN_64, RVVM1DI, 8, LMUL_1, 16) TUPLE_ENTRY (RVVM1x7DI, TARGET_VECTOR_ELEN_64, RVVM1DI, 7, LMUL_1, 16) diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc index 51878797287..44a36db7803 100644 --- a/gcc/config/riscv/riscv.cc +++ b/gcc/config/riscv/riscv.cc @@ -1406,6 +1406,9 @@ riscv_v_adjust_bytesize (machine_mode mode, int scale) {    if (riscv_v_ext_vector_mode_p (mode))      { +      if (TARGET_XTHEADVECTOR) + return BYTES_PER_RISCV_VECTOR; +        poly_int64 nunits = GET_MODE_NUNITS (mode);        poly_int64 mode_size = GET_MODE_SIZE (mode); @@ -9962,7 +9965,7 @@ riscv_use_divmod_expander (void) static machine_mode riscv_preferred_simd_mode (scalar_mode mode) { -  if (TARGET_VECTOR) +  if (TARGET_VECTOR && !TARGET_XTHEADVECTOR)      return riscv_vector::preferred_simd_mode (mode);    return word_mode; @@ -10313,7 +10316,7 @@ riscv_mode_priority (int, int n) unsigned int riscv_autovectorize_vector_modes (vector_modes *modes, bool all) { -  if (TARGET_VECTOR) +  if (TARGET_VECTOR && !TARGET_XTHEADVECTOR)      return riscv_vector::autovectorize_vector_modes (modes, all);    return default_autovectorize_vector_modes (modes, all); @@ -10496,6 +10499,16 @@ extract_base_offset_in_addr (rtx mem, rtx *base, rtx *offset)    return false; } +/* Implements target hook vector_mode_supported_any_target_p.  */ + +static bool +riscv_vector_mode_supported_any_target_p (machine_mode mode) +{ +  if (TARGET_XTHEADVECTOR) +    return false; +  return true; +} + /* Initialize the GCC target structure.  */ #undef TARGET_ASM_ALIGNED_HI_OP #define TARGET_ASM_ALIGNED_HI_OP "\t.half\t" @@ -10839,6 +10852,9 @@ extract_base_offset_in_addr (rtx mem, rtx *base, rtx *offset) #undef TARGET_PREFERRED_ELSE_VALUE #define TARGET_PREFERRED_ELSE_VALUE riscv_preferred_else_value +#undef TARGET_VECTOR_MODE_SUPPORTED_ANY_TARGET_P +#define TARGET_VECTOR_MODE_SUPPORTED_ANY_TARGET_P riscv_vector_mode_supported_any_target_p + struct gcc_target targetm = TARGET_INITIALIZER; #include "gt-riscv.h" diff --git a/gcc/config/riscv/riscv_th_vector.h b/gcc/config/riscv/riscv_th_vector.h new file mode 100644 index 00000000000..a897b9cb90a --- /dev/null +++ b/gcc/config/riscv/riscv_th_vector.h @@ -0,0 +1,49 @@ +/* RISC-V 'XTheadVector' Extension intrinsics include file. +   Copyright (C) 2022-2023 Free Software Foundation, Inc. + +   This file is part of GCC. + +   GCC is free software; you can redistribute it and/or modify it +   under the terms of the GNU General Public License as published +   by the Free Software Foundation; either version 3, or (at your +   option) any later version. + +   GCC is distributed in the hope that it will be useful, but WITHOUT +   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY +   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public +   License for more details. + +   Under Section 7 of GPL version 3, you are granted additional +   permissions described in the GCC Runtime Library Exception, version +   3.1, as published by the Free Software Foundation. + +   You should have received a copy of the GNU General Public License and +   a copy of the GCC Runtime Library Exception along with this program; +   see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see +   <" target="_blank">http://www.gnu.org/licenses/>.  */ + +#ifndef __RISCV_TH_VECTOR_H +#define __RISCV_TH_VECTOR_H + +#include +#include + +#ifndef __riscv_xtheadvector +#error "XTheadVector intrinsics require the xtheadvector extension." +#else +#ifdef __cplusplus +extern "C" { +#endif + +/* NOTE: This implementation of riscv_th_vector.h is intentionally short.  It does +   not define the RVV types and intrinsic functions directly in C and C++ +   code, but instead uses the following pragma to tell GCC to insert the +   necessary type and function definitions itself.  The net effect is the +   same, and the file is a complete implementation of riscv_th_vector.h.  */ +#pragma riscv intrinsic "xtheadvector" + +#ifdef __cplusplus +} +#endif // __cplusplus +#endif // __riscv_xtheadvector +#endif // __RISCV_TH_ECTOR_H diff --git a/gcc/config/riscv/thead-vector.md b/gcc/config/riscv/thead-vector.md new file mode 100644 index 00000000000..1230bfb5994 --- /dev/null +++ b/gcc/config/riscv/thead-vector.md @@ -0,0 +1,69 @@ +(define_c_enum "unspec" [ +  UNSPEC_TH_VWLDST +]) + +(define_mode_iterator V_VLS_VT [V VLS VT]) +(define_mode_iterator V_VB_VLS_VT [V VB VLS VT]) + +(define_split +  [(set (match_operand:V_VB_VLS_VT 0 "reg_or_mem_operand") + (match_operand:V_VB_VLS_VT 1 "reg_or_mem_operand"))] +  "TARGET_XTHEADVECTOR" +  [(const_int 0)] +  { +    emit_insn (gen_pred_th_whole_mov (mode, operands[0], operands[1], +       RVV_VLMAX, GEN_INT(riscv_vector::VLMAX))); +    DONE; +  }) + +(define_insn_and_split "@pred_th_whole_mov" +  [(set (match_operand:V_VLS_VT 0 "reg_or_mem_operand"  "=vr,vr, m") + (unspec:V_VLS_VT +   [(match_operand:V_VLS_VT 1 "reg_or_mem_operand" " vr, m,vr") +    (match_operand 2 "vector_length_operand"   " rK, rK, rK") +    (match_operand 3 "const_1_operand"         "  i, i, i") +    (reg:SI VL_REGNUM) +    (reg:SI VTYPE_REGNUM)] + UNSPEC_TH_VWLDST))] +  "TARGET_XTHEADVECTOR" +  "@ +   vmv.v.v\t%0,%1 +   vle.v\t%0,%1 +   vse.v\t%1,%0" +  "&& REG_P (operands[0]) && REG_P (operands[1]) +   && REGNO (operands[0]) == REGNO (operands[1])" +  [(const_int 0)] +  "" +  [(set_attr "type" "vimov,vlds,vlds") +   (set_attr "mode" "") +   (set (attr "ta") (symbol_ref "riscv_vector::TAIL_UNDISTURBED")) +   (set (attr "ma") (symbol_ref "riscv_vector::MASK_UNDISTURBED")) +   (set (attr "avl_type_idx") (const_int 3)) +   (set_attr "vl_op_idx" "2")]) + +(define_insn_and_split "@pred_th_whole_mov" +  [(set (match_operand:VB 0 "reg_or_mem_operand"  "=vr,vr, m") + (unspec:VB +   [(match_operand:VB 1 "reg_or_mem_operand" " vr, m,vr") +    (match_operand 2 "vector_length_operand"   " rK, rK, rK") +    (match_operand 3 "const_1_operand"         "  i, i, i") +    (reg:SI VL_REGNUM) +    (reg:SI VTYPE_REGNUM)] + UNSPEC_TH_VWLDST))] +  "TARGET_XTHEADVECTOR" +  "@ +   vmv.v.v\t%0,%1 +   vle.v\t%0,%1 +   vse.v\t%1,%0" +  "&& REG_P (operands[0]) && REG_P (operands[1]) +   && REGNO (operands[0]) == REGNO (operands[1])" +  [(const_int 0)] +  "" +  [(set_attr "type" "vimov,vlds,vlds") +   (set_attr "mode" "") +   (set (attr "ta") (symbol_ref "riscv_vector::TAIL_UNDISTURBED")) +   (set (attr "ma") (symbol_ref "riscv_vector::MASK_UNDISTURBED")) +   (set (attr "avl_type_idx") (const_int 3)) +   (set_attr "vl_op_idx" "2") +   (set (attr "sew") (const_int 8)) +   (set (attr "vlmul") (symbol_ref "riscv_vector::LMUL_1"))]) diff --git a/gcc/config/riscv/vector-iterators.md b/gcc/config/riscv/vector-iterators.md index 5f5f7b5b986..c0fc7a2441d 100644 --- a/gcc/config/riscv/vector-iterators.md +++ b/gcc/config/riscv/vector-iterators.md @@ -109,11 +109,11 @@ ]) (define_mode_iterator VI [ -  RVVM8QI RVVM4QI RVVM2QI RVVM1QI RVVMF2QI RVVMF4QI (RVVMF8QI "TARGET_MIN_VLEN > 32") +  RVVM8QI RVVM4QI RVVM2QI RVVM1QI (RVVMF2QI "!TARGET_XTHEADVECTOR") (RVVMF4QI "!TARGET_XTHEADVECTOR") (RVVMF8QI "!TARGET_XTHEADVECTOR && TARGET_MIN_VLEN > 32") -  RVVM8HI RVVM4HI RVVM2HI RVVM1HI RVVMF2HI (RVVMF4HI "TARGET_MIN_VLEN > 32") +  RVVM8HI RVVM4HI RVVM2HI RVVM1HI (RVVMF2HI "!TARGET_XTHEADVECTOR") (RVVMF4HI "!TARGET_XTHEADVECTOR && TARGET_MIN_VLEN > 32") -  RVVM8SI RVVM4SI RVVM2SI RVVM1SI (RVVMF2SI "TARGET_MIN_VLEN > 32") +  RVVM8SI RVVM4SI RVVM2SI RVVM1SI (RVVMF2SI "!TARGET_XTHEADVECTOR && TARGET_MIN_VLEN > 32")    (RVVM8DI "TARGET_VECTOR_ELEN_64") (RVVM4DI "TARGET_VECTOR_ELEN_64")    (RVVM2DI "TARGET_VECTOR_ELEN_64") (RVVM1DI "TARGET_VECTOR_ELEN_64") @@ -128,11 +128,11 @@ ;; allow the instruction and mode to be matched during combine et al. (define_mode_iterator VF [    (RVVM8HF "TARGET_ZVFH") (RVVM4HF "TARGET_ZVFH") (RVVM2HF "TARGET_ZVFH") -  (RVVM1HF "TARGET_ZVFH") (RVVMF2HF "TARGET_ZVFH") -  (RVVMF4HF "TARGET_ZVFH && TARGET_MIN_VLEN > 32") +  (RVVM1HF "TARGET_ZVFH") (RVVMF2HF "!TARGET_XTHEADVECTOR && TARGET_ZVFH") +  (RVVMF4HF "!TARGET_XTHEADVECTOR && TARGET_ZVFH && TARGET_MIN_VLEN > 32")    (RVVM8SF "TARGET_VECTOR_ELEN_FP_32") (RVVM4SF "TARGET_VECTOR_ELEN_FP_32") (RVVM2SF "TARGET_VECTOR_ELEN_FP_32") -  (RVVM1SF "TARGET_VECTOR_ELEN_FP_32") (RVVMF2SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32") +  (RVVM1SF "TARGET_VECTOR_ELEN_FP_32") (RVVMF2SF "!TARGET_XTHEADVECTOR && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32")    (RVVM8DF "TARGET_VECTOR_ELEN_FP_64") (RVVM4DF "TARGET_VECTOR_ELEN_FP_64")    (RVVM2DF "TARGET_VECTOR_ELEN_FP_64") (RVVM1DF "TARGET_VECTOR_ELEN_FP_64") @@ -140,11 +140,11 @@ (define_mode_iterator VF_ZVFHMIN [    (RVVM8HF "TARGET_VECTOR_ELEN_FP_16") (RVVM4HF "TARGET_VECTOR_ELEN_FP_16") (RVVM2HF "TARGET_VECTOR_ELEN_FP_16") -  (RVVM1HF "TARGET_VECTOR_ELEN_FP_16") (RVVMF2HF "TARGET_VECTOR_ELEN_FP_16") -  (RVVMF4HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN > 32") +  (RVVM1HF "TARGET_VECTOR_ELEN_FP_16") (RVVMF2HF "!TARGET_XTHEADVECTOR && TARGET_VECTOR_ELEN_FP_16") +  (RVVMF4HF "!TARGET_XTHEADVECTOR && TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN > 32")    (RVVM8SF "TARGET_VECTOR_ELEN_FP_32") (RVVM4SF "TARGET_VECTOR_ELEN_FP_32") (RVVM2SF "TARGET_VECTOR_ELEN_FP_32") -  (RVVM1SF "TARGET_VECTOR_ELEN_FP_32") (RVVMF2SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32") +  (RVVM1SF "TARGET_VECTOR_ELEN_FP_32") (RVVMF2SF "!TARGET_XTHEADVECTOR && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32")    (RVVM8DF "TARGET_VECTOR_ELEN_FP_64") (RVVM4DF "TARGET_VECTOR_ELEN_FP_64")    (RVVM2DF "TARGET_VECTOR_ELEN_FP_64") (RVVM1DF "TARGET_VECTOR_ELEN_FP_64") @@ -271,16 +271,16 @@ ]) (define_mode_iterator VEEWEXT2 [ -  RVVM8HI RVVM4HI RVVM2HI RVVM1HI RVVMF2HI (RVVMF4HI "TARGET_MIN_VLEN > 32") +  RVVM8HI RVVM4HI RVVM2HI RVVM1HI (RVVMF2HI "!TARGET_XTHEADVECTOR") (RVVMF4HI "!TARGET_XTHEADVECTOR && TARGET_MIN_VLEN > 32")    (RVVM8HF "TARGET_VECTOR_ELEN_FP_16") (RVVM4HF "TARGET_VECTOR_ELEN_FP_16") (RVVM2HF "TARGET_VECTOR_ELEN_FP_16") -  (RVVM1HF "TARGET_VECTOR_ELEN_FP_16") (RVVMF2HF "TARGET_VECTOR_ELEN_FP_16") -  (RVVMF4HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN > 32") +  (RVVM1HF "TARGET_VECTOR_ELEN_FP_16") (RVVMF2HF "!TARGET_XTHEADVECTOR && TARGET_VECTOR_ELEN_FP_16") +  (RVVMF4HF "!TARGET_XTHEADVECTOR && TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN > 32") -  RVVM8SI RVVM4SI RVVM2SI RVVM1SI (RVVMF2SI "TARGET_MIN_VLEN > 32") +  RVVM8SI RVVM4SI RVVM2SI RVVM1SI (RVVMF2SI "!TARGET_XTHEADVECTOR && TARGET_MIN_VLEN > 32")    (RVVM8SF "TARGET_VECTOR_ELEN_FP_32") (RVVM4SF "TARGET_VECTOR_ELEN_FP_32") (RVVM2SF "TARGET_VECTOR_ELEN_FP_32") -  (RVVM1SF "TARGET_VECTOR_ELEN_FP_32") (RVVMF2SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32") +  (RVVM1SF "TARGET_VECTOR_ELEN_FP_32") (RVVMF2SF "!TARGET_XTHEADVECTOR && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32")    (RVVM8DI "TARGET_VECTOR_ELEN_64") (RVVM4DI "TARGET_VECTOR_ELEN_64")    (RVVM2DI "TARGET_VECTOR_ELEN_64") (RVVM1DI "TARGET_VECTOR_ELEN_64") @@ -290,10 +290,10 @@ ]) (define_mode_iterator VEEWEXT4 [ -  RVVM8SI RVVM4SI RVVM2SI RVVM1SI (RVVMF2SI "TARGET_MIN_VLEN > 32") +  RVVM8SI RVVM4SI RVVM2SI RVVM1SI (RVVMF2SI "!TARGET_XTHEADVECTOR && TARGET_MIN_VLEN > 32")    (RVVM8SF "TARGET_VECTOR_ELEN_FP_32") (RVVM4SF "TARGET_VECTOR_ELEN_FP_32") (RVVM2SF "TARGET_VECTOR_ELEN_FP_32") -  (RVVM1SF "TARGET_VECTOR_ELEN_FP_32") (RVVMF2SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32") +  (RVVM1SF "TARGET_VECTOR_ELEN_FP_32") (RVVMF2SF "!TARGET_XTHEADVECTOR && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32")    (RVVM8DI "TARGET_VECTOR_ELEN_64") (RVVM4DI "TARGET_VECTOR_ELEN_64")    (RVVM2DI "TARGET_VECTOR_ELEN_64") (RVVM1DI "TARGET_VECTOR_ELEN_64") @@ -311,59 +311,59 @@ ]) (define_mode_iterator VEEWTRUNC2 [ -  RVVM4QI RVVM2QI RVVM1QI RVVMF2QI RVVMF4QI (RVVMF8QI "TARGET_MIN_VLEN > 32") +  RVVM4QI RVVM2QI RVVM1QI (RVVMF2QI "!TARGET_XTHEADVECTOR") (RVVMF4QI "!TARGET_XTHEADVECTOR") (RVVMF8QI "!TARGET_XTHEADVECTOR && TARGET_MIN_VLEN > 32") -  RVVM4HI RVVM2HI RVVM1HI RVVMF2HI (RVVMF4HI "TARGET_MIN_VLEN > 32") +  RVVM4HI RVVM2HI RVVM1HI (RVVMF2HI "!TARGET_XTHEADVECTOR") (RVVMF4HI "!TARGET_XTHEADVECTOR && TARGET_MIN_VLEN > 32")    (RVVM4HF "TARGET_VECTOR_ELEN_FP_16") (RVVM2HF "TARGET_VECTOR_ELEN_FP_16") -  (RVVM1HF "TARGET_VECTOR_ELEN_FP_16") (RVVMF2HF "TARGET_VECTOR_ELEN_FP_16") -  (RVVMF4HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN > 32") +  (RVVM1HF "TARGET_VECTOR_ELEN_FP_16") (RVVMF2HF "!TARGET_XTHEADVECTOR && TARGET_VECTOR_ELEN_FP_16") +  (RVVMF4HF "!TARGET_XTHEADVECTOR && TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN > 32")    (RVVM4SI "TARGET_64BIT")    (RVVM2SI "TARGET_64BIT")    (RVVM1SI "TARGET_64BIT") -  (RVVMF2SI "TARGET_MIN_VLEN > 32 && TARGET_64BIT") +  (RVVMF2SI "!TARGET_XTHEADVECTOR && TARGET_MIN_VLEN > 32 && TARGET_64BIT")    (RVVM4SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_64BIT")    (RVVM2SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_64BIT")    (RVVM1SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_64BIT") -  (RVVMF2SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32 && TARGET_64BIT") +  (RVVMF2SF "!TARGET_XTHEADVECTOR && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32 && TARGET_64BIT") ]) (define_mode_iterator VEEWTRUNC4 [ -  RVVM2QI RVVM1QI RVVMF2QI RVVMF4QI (RVVMF8QI "TARGET_MIN_VLEN > 32") +  RVVM2QI RVVM1QI (RVVMF2QI "!TARGET_XTHEADVECTOR") (RVVMF4QI "!TARGET_XTHEADVECTOR") (RVVMF8QI "!TARGET_XTHEADVECTOR && TARGET_MIN_VLEN > 32")    (RVVM2HI "TARGET_64BIT")    (RVVM1HI "TARGET_64BIT") -  (RVVMF2HI "TARGET_64BIT") -  (RVVMF4HI "TARGET_MIN_VLEN > 32 && TARGET_64BIT") +  (RVVMF2HI "!TARGET_XTHEADVECTOR && TARGET_64BIT") +  (RVVMF4HI "!TARGET_XTHEADVECTOR && TARGET_MIN_VLEN > 32 && TARGET_64BIT")    (RVVM2HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_64BIT")    (RVVM1HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_64BIT") -  (RVVMF2HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_64BIT") -  (RVVMF4HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN > 32 && TARGET_64BIT") +  (RVVMF2HF "!TARGET_XTHEADVECTOR && TARGET_VECTOR_ELEN_FP_16 && TARGET_64BIT") +  (RVVMF4HF "!TARGET_XTHEADVECTOR && TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN > 32 && TARGET_64BIT") ]) (define_mode_iterator VEEWTRUNC8 [    (RVVM1QI "TARGET_64BIT") -  (RVVMF2QI "TARGET_64BIT") -  (RVVMF4QI "TARGET_64BIT") -  (RVVMF8QI "TARGET_MIN_VLEN > 32 && TARGET_64BIT") +  (RVVMF2QI "!TARGET_XTHEADVECTOR && TARGET_64BIT") +  (RVVMF4QI "!TARGET_XTHEADVECTOR && TARGET_64BIT") +  (RVVMF8QI "!TARGET_XTHEADVECTOR && TARGET_MIN_VLEN > 32 && TARGET_64BIT") ]) (define_mode_iterator VEI16 [ -  RVVM4QI RVVM2QI RVVM1QI RVVMF2QI RVVMF4QI (RVVMF8QI "TARGET_MIN_VLEN > 32") +  RVVM4QI RVVM2QI RVVM1QI (RVVMF2QI "!TARGET_XTHEADVECTOR") (RVVMF4QI "!TARGET_XTHEADVECTOR") (RVVMF8QI "!TARGET_XTHEADVECTOR && TARGET_MIN_VLEN > 32") -  RVVM8HI RVVM4HI RVVM2HI RVVM1HI RVVMF2HI (RVVMF4HI "TARGET_MIN_VLEN > 32") +  RVVM8HI RVVM4HI RVVM2HI RVVM1HI (RVVMF2HI "!TARGET_XTHEADVECTOR") (RVVMF4HI "!TARGET_XTHEADVECTOR && TARGET_MIN_VLEN > 32")    (RVVM8HF "TARGET_VECTOR_ELEN_FP_16") (RVVM4HF "TARGET_VECTOR_ELEN_FP_16") (RVVM2HF "TARGET_VECTOR_ELEN_FP_16") -  (RVVM1HF "TARGET_VECTOR_ELEN_FP_16") (RVVMF2HF "TARGET_VECTOR_ELEN_FP_16") -  (RVVMF4HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN > 32") +  (RVVM1HF "TARGET_VECTOR_ELEN_FP_16") (RVVMF2HF "!TARGET_XTHEADVECTOR && TARGET_VECTOR_ELEN_FP_16") +  (RVVMF4HF "!TARGET_XTHEADVECTOR && TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN > 32") -  RVVM8SI RVVM4SI RVVM2SI RVVM1SI (RVVMF2SI "TARGET_MIN_VLEN > 32") +  RVVM8SI RVVM4SI RVVM2SI RVVM1SI (RVVMF2SI "!TARGET_XTHEADVECTOR && TARGET_MIN_VLEN > 32")    (RVVM8SF "TARGET_VECTOR_ELEN_FP_32") (RVVM4SF "TARGET_VECTOR_ELEN_FP_32") (RVVM2SF "TARGET_VECTOR_ELEN_FP_32") -  (RVVM1SF "TARGET_VECTOR_ELEN_FP_32") (RVVMF2SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32") +  (RVVM1SF "TARGET_VECTOR_ELEN_FP_32") (RVVMF2SF "!TARGET_XTHEADVECTOR && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32")    (RVVM8DI "TARGET_VECTOR_ELEN_64") (RVVM4DI "TARGET_VECTOR_ELEN_64")    (RVVM2DI "TARGET_VECTOR_ELEN_64") (RVVM1DI "TARGET_VECTOR_ELEN_64") @@ -452,11 +452,11 @@ ]) (define_mode_iterator VFULLI [ -  RVVM8QI RVVM4QI RVVM2QI RVVM1QI RVVMF2QI RVVMF4QI (RVVMF8QI "TARGET_MIN_VLEN > 32") +  RVVM8QI RVVM4QI RVVM2QI RVVM1QI (RVVMF2QI "!TARGET_XTHEADVECTOR") (RVVMF4QI "!TARGET_XTHEADVECTOR") (RVVMF8QI "!TARGET_XTHEADVECTOR && TARGET_MIN_VLEN > 32") -  RVVM8HI RVVM4HI RVVM2HI RVVM1HI RVVMF2HI (RVVMF4HI "TARGET_MIN_VLEN > 32") +  RVVM8HI RVVM4HI RVVM2HI RVVM1HI (RVVMF2HI "!TARGET_XTHEADVECTOR") (RVVMF4HI "!TARGET_XTHEADVECTOR && TARGET_MIN_VLEN > 32") -  RVVM8SI RVVM4SI RVVM2SI RVVM1SI (RVVMF2SI "TARGET_MIN_VLEN > 32") +  RVVM8SI RVVM4SI RVVM2SI RVVM1SI (RVVMF2SI "!TARGET_XTHEADVECTOR && TARGET_MIN_VLEN > 32")    (RVVM8DI "TARGET_FULL_V") (RVVM4DI "TARGET_FULL_V") (RVVM2DI "TARGET_FULL_V") (RVVM1DI "TARGET_FULL_V") @@ -509,17 +509,17 @@ ]) (define_mode_iterator VI_QH [ -  RVVM8QI RVVM4QI RVVM2QI RVVM1QI RVVMF2QI RVVMF4QI (RVVMF8QI "TARGET_MIN_VLEN > 32") +  RVVM8QI RVVM4QI RVVM2QI RVVM1QI (RVVMF2QI "!TARGET_XTHEADVECTOR") (RVVMF4QI "!TARGET_XTHEADVECTOR") (RVVMF8QI "!TARGET_XTHEADVECTOR && TARGET_MIN_VLEN > 32") -  RVVM8HI RVVM4HI RVVM2HI RVVM1HI RVVMF2HI (RVVMF4HI "TARGET_MIN_VLEN > 32") +  RVVM8HI RVVM4HI RVVM2HI RVVM1HI (RVVMF2HI "!TARGET_XTHEADVECTOR") (RVVMF4HI "!TARGET_XTHEADVECTOR && TARGET_MIN_VLEN > 32") ]) (define_mode_iterator VI_QHS [ -  RVVM8QI RVVM4QI RVVM2QI RVVM1QI RVVMF2QI RVVMF4QI (RVVMF8QI "TARGET_MIN_VLEN > 32") +  RVVM8QI RVVM4QI RVVM2QI RVVM1QI (RVVMF2QI "!TARGET_XTHEADVECTOR") (RVVMF4QI "!TARGET_XTHEADVECTOR") (RVVMF8QI "!TARGET_XTHEADVECTOR && TARGET_MIN_VLEN > 32") -  RVVM8HI RVVM4HI RVVM2HI RVVM1HI RVVMF2HI (RVVMF4HI "TARGET_MIN_VLEN > 32") +  RVVM8HI RVVM4HI RVVM2HI RVVM1HI (RVVMF2HI "!TARGET_XTHEADVECTOR") (RVVMF4HI "!TARGET_XTHEADVECTOR && TARGET_MIN_VLEN > 32") -  RVVM8SI RVVM4SI RVVM2SI RVVM1SI (RVVMF2SI "TARGET_MIN_VLEN > 32") +  RVVM8SI RVVM4SI RVVM2SI RVVM1SI (RVVMF2SI "!TARGET_XTHEADVECTOR && TARGET_MIN_VLEN > 32")    (V1QI "riscv_vector::vls_mode_valid_p (V1QImode)")    (V2QI "riscv_vector::vls_mode_valid_p (V2QImode)") @@ -560,11 +560,11 @@ ]) (define_mode_iterator VI_QHS_NO_M8 [ -  RVVM4QI RVVM2QI RVVM1QI RVVMF2QI RVVMF4QI (RVVMF8QI "TARGET_MIN_VLEN > 32") +  RVVM4QI RVVM2QI RVVM1QI (RVVMF2QI "!TARGET_XTHEADVECTOR") (RVVMF4QI "!TARGET_XTHEADVECTOR") (RVVMF8QI "!TARGET_XTHEADVECTOR && TARGET_MIN_VLEN > 32") -  RVVM4HI RVVM2HI RVVM1HI RVVMF2HI (RVVMF4HI "TARGET_MIN_VLEN > 32") +  RVVM4HI RVVM2HI RVVM1HI (RVVMF2HI "!TARGET_XTHEADVECTOR") (RVVMF4HI "!TARGET_XTHEADVECTOR && TARGET_MIN_VLEN > 32") -  RVVM4SI RVVM2SI RVVM1SI (RVVMF2SI "TARGET_MIN_VLEN > 32") +  RVVM4SI RVVM2SI RVVM1SI (RVVMF2SI "!TARGET_XTHEADVECTOR && TARGET_MIN_VLEN > 32")    (V1QI "riscv_vector::vls_mode_valid_p (V1QImode)")    (V2QI "riscv_vector::vls_mode_valid_p (V2QImode)") @@ -603,11 +603,11 @@ (define_mode_iterator VF_HS [    (RVVM8HF "TARGET_ZVFH") (RVVM4HF "TARGET_ZVFH") (RVVM2HF "TARGET_ZVFH") -  (RVVM1HF "TARGET_ZVFH") (RVVMF2HF "TARGET_ZVFH") -  (RVVMF4HF "TARGET_ZVFH && TARGET_MIN_VLEN > 32") +  (RVVM1HF "TARGET_ZVFH") (RVVMF2HF "!TARGET_XTHEADVECTOR && TARGET_ZVFH") +  (RVVMF4HF "!TARGET_XTHEADVECTOR && TARGET_ZVFH && TARGET_MIN_VLEN > 32")    (RVVM8SF "TARGET_VECTOR_ELEN_FP_32") (RVVM4SF "TARGET_VECTOR_ELEN_FP_32") (RVVM2SF "TARGET_VECTOR_ELEN_FP_32") -  (RVVM1SF "TARGET_VECTOR_ELEN_FP_32") (RVVMF2SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32") +  (RVVM1SF "TARGET_VECTOR_ELEN_FP_32") (RVVMF2SF "!TARGET_XTHEADVECTOR && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32")    (V1HF "riscv_vector::vls_mode_valid_p (V1HFmode) && TARGET_ZVFH")    (V2HF "riscv_vector::vls_mode_valid_p (V2HFmode) && TARGET_ZVFH") @@ -638,12 +638,12 @@    (RVVM4HF "TARGET_ZVFH")    (RVVM2HF "TARGET_ZVFH")    (RVVM1HF "TARGET_ZVFH") -  (RVVMF2HF "TARGET_ZVFH") -  (RVVMF4HF "TARGET_ZVFH && TARGET_MIN_VLEN > 32") +  (RVVMF2HF "!TARGET_XTHEADVECTOR && TARGET_ZVFH") +  (RVVMF4HF "!TARGET_XTHEADVECTOR && TARGET_ZVFH && TARGET_MIN_VLEN > 32")    (RVVM4SF "TARGET_VECTOR_ELEN_FP_32")    (RVVM2SF "TARGET_VECTOR_ELEN_FP_32")    (RVVM1SF "TARGET_VECTOR_ELEN_FP_32") -  (RVVMF2SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32") +  (RVVMF2SF "!TARGET_XTHEADVECTOR && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32")    (V1HF "riscv_vector::vls_mode_valid_p (V1HFmode) && TARGET_ZVFH")    (V2HF "riscv_vector::vls_mode_valid_p (V2HFmode) && TARGET_ZVFH") @@ -674,11 +674,11 @@ ]) (define_mode_iterator V_VLSI_QHS [ -  RVVM8QI RVVM4QI RVVM2QI RVVM1QI RVVMF2QI RVVMF4QI (RVVMF8QI "TARGET_MIN_VLEN > 32") +  RVVM8QI RVVM4QI RVVM2QI RVVM1QI (RVVMF2QI "!TARGET_XTHEADVECTOR") (RVVMF4QI "!TARGET_XTHEADVECTOR") (RVVMF8QI "!TARGET_XTHEADVECTOR && TARGET_MIN_VLEN > 32") -  RVVM8HI RVVM4HI RVVM2HI RVVM1HI RVVMF2HI (RVVMF4HI "TARGET_MIN_VLEN > 32") +  RVVM8HI RVVM4HI RVVM2HI RVVM1HI (RVVMF2HI "!TARGET_XTHEADVECTOR") (RVVMF4HI "!TARGET_XTHEADVECTOR && TARGET_MIN_VLEN > 32") -  RVVM8SI RVVM4SI RVVM2SI RVVM1SI (RVVMF2SI "TARGET_MIN_VLEN > 32") +  RVVM8SI RVVM4SI RVVM2SI RVVM1SI (RVVMF2SI "!TARGET_XTHEADVECTOR && TARGET_MIN_VLEN > 32")    (V1QI "riscv_vector::vls_mode_valid_p (V1QImode)")    (V2QI "riscv_vector::vls_mode_valid_p (V2QImode)") @@ -756,27 +756,27 @@ ;; E.g. when index mode = RVVM8QImde and Pmode = SImode, if it is not zero_extend or ;; scalar != 1, such gather/scatter is not allowed since we don't have RVVM32SImode. (define_mode_iterator RATIO64 [ -  (RVVMF8QI "TARGET_MIN_VLEN > 32") -  (RVVMF4HI "TARGET_MIN_VLEN > 32") -  (RVVMF2SI "TARGET_MIN_VLEN > 32") +  (RVVMF8QI "!TARGET_XTHEADVECTOR && TARGET_MIN_VLEN > 32") +  (RVVMF4HI "!TARGET_XTHEADVECTOR && TARGET_MIN_VLEN > 32") +  (RVVMF2SI "!TARGET_XTHEADVECTOR && TARGET_MIN_VLEN > 32")    (RVVM1DI "TARGET_VECTOR_ELEN_64") -  (RVVMF4HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN > 32") -  (RVVMF2SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32") +  (RVVMF4HF "!TARGET_XTHEADVECTOR && TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN > 32") +  (RVVMF2SF "!TARGET_XTHEADVECTOR && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32")    (RVVM1DF "TARGET_VECTOR_ELEN_FP_64") ]) (define_mode_iterator RATIO32 [ -  RVVMF4QI -  RVVMF2HI +  (RVVMF4QI "!TARGET_XTHEADVECTOR") +  (RVVMF2HI "!TARGET_XTHEADVECTOR")    RVVM1SI    (RVVM2DI "TARGET_VECTOR_ELEN_64") -  (RVVMF2HF "TARGET_VECTOR_ELEN_FP_16") +  (RVVMF2HF "!TARGET_XTHEADVECTOR && TARGET_VECTOR_ELEN_FP_16")    (RVVM1SF "TARGET_VECTOR_ELEN_FP_32")    (RVVM2DF "TARGET_VECTOR_ELEN_FP_64") ]) (define_mode_iterator RATIO16 [ -  RVVMF2QI +  (RVVMF2QI "!TARGET_XTHEADVECTOR")    RVVM1HI    RVVM2SI    (RVVM4DI "TARGET_VECTOR_ELEN_64") @@ -814,21 +814,21 @@ ]) (define_mode_iterator RATIO64I [ -  (RVVMF8QI "TARGET_MIN_VLEN > 32") -  (RVVMF4HI "TARGET_MIN_VLEN > 32") -  (RVVMF2SI "TARGET_MIN_VLEN > 32") +  (RVVMF8QI "!TARGET_XTHEADVECTOR && TARGET_MIN_VLEN > 32") +  (RVVMF4HI "!TARGET_XTHEADVECTOR && TARGET_MIN_VLEN > 32") +  (RVVMF2SI "!TARGET_XTHEADVECTOR && TARGET_MIN_VLEN > 32")    (RVVM1DI "TARGET_VECTOR_ELEN_64 && TARGET_64BIT") ]) (define_mode_iterator RATIO32I [ -  RVVMF4QI -  RVVMF2HI +  (RVVMF4QI "!TARGET_XTHEADVECTOR") +  (RVVMF2HI "!TARGET_XTHEADVECTOR")    RVVM1SI    (RVVM2DI "TARGET_VECTOR_ELEN_64 && TARGET_64BIT") ]) (define_mode_iterator RATIO16I [ -  RVVMF2QI +  (RVVMF2QI "!TARGET_XTHEADVECTOR")    RVVM1HI    RVVM2SI    (RVVM4DI "TARGET_VECTOR_ELEN_64 && TARGET_64BIT") @@ -873,21 +873,21 @@ ]) (define_mode_iterator V_FRACT [ -  RVVMF2QI RVVMF4QI (RVVMF8QI "TARGET_MIN_VLEN > 32") +  (RVVMF2QI "!TARGET_XTHEADVECTOR") (RVVMF4QI "!TARGET_XTHEADVECTOR") (RVVMF8QI "!TARGET_XTHEADVECTOR && TARGET_MIN_VLEN > 32") -  RVVMF2HI (RVVMF4HI "TARGET_MIN_VLEN > 32") +  (RVVMF2HI "!TARGET_XTHEADVECTOR") (RVVMF4HI "!TARGET_XTHEADVECTOR && TARGET_MIN_VLEN > 32") -  (RVVMF2HF "TARGET_VECTOR_ELEN_FP_16") (RVVMF4HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN > 32") +  (RVVMF2HF "!TARGET_XTHEADVECTOR && TARGET_VECTOR_ELEN_FP_16") (RVVMF4HF "!TARGET_XTHEADVECTOR && TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN > 32") -  (RVVMF2SI "TARGET_MIN_VLEN > 32") +  (RVVMF2SI "!TARGET_XTHEADVECTOR && TARGET_MIN_VLEN > 32") -  (RVVMF2SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32") +  (RVVMF2SF "!TARGET_XTHEADVECTOR && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32") ]) (define_mode_iterator VWEXTI [ -  RVVM8HI RVVM4HI RVVM2HI RVVM1HI RVVMF2HI (RVVMF4HI "TARGET_MIN_VLEN > 32") +  RVVM8HI RVVM4HI RVVM2HI RVVM1HI (RVVMF2HI "!TARGET_XTHEADVECTOR") (RVVMF4HI "!TARGET_XTHEADVECTOR && TARGET_MIN_VLEN > 32") -  RVVM8SI RVVM4SI RVVM2SI RVVM1SI (RVVMF2SI "TARGET_MIN_VLEN > 32") +  RVVM8SI RVVM4SI RVVM2SI RVVM1SI (RVVMF2SI "!TARGET_XTHEADVECTOR && TARGET_MIN_VLEN > 32")    (RVVM8DI "TARGET_VECTOR_ELEN_64") (RVVM4DI "TARGET_VECTOR_ELEN_64")    (RVVM2DI "TARGET_VECTOR_ELEN_64") (RVVM1DI "TARGET_VECTOR_ELEN_64") @@ -933,7 +933,7 @@    (RVVM4SF "TARGET_VECTOR_ELEN_FP_16 && TARGET_VECTOR_ELEN_FP_32")    (RVVM2SF "TARGET_VECTOR_ELEN_FP_16 && TARGET_VECTOR_ELEN_FP_32")    (RVVM1SF "TARGET_VECTOR_ELEN_FP_16 && TARGET_VECTOR_ELEN_FP_32") -  (RVVMF2SF "TARGET_VECTOR_ELEN_FP_16 && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32") +  (RVVMF2SF "!TARGET_XTHEADVECTOR && TARGET_VECTOR_ELEN_FP_16 && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32")    (RVVM8DF "TARGET_VECTOR_ELEN_FP_64") (RVVM4DF "TARGET_VECTOR_ELEN_FP_64")    (RVVM2DF "TARGET_VECTOR_ELEN_FP_64") (RVVM1DF "TARGET_VECTOR_ELEN_FP_64") @@ -966,7 +966,7 @@    (RVVM4SF "TARGET_ZVFH && TARGET_VECTOR_ELEN_FP_32")    (RVVM2SF "TARGET_ZVFH && TARGET_VECTOR_ELEN_FP_32")    (RVVM1SF "TARGET_ZVFH && TARGET_VECTOR_ELEN_FP_32") -  (RVVMF2SF "TARGET_ZVFH && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32") +  (RVVMF2SF "!TARGET_XTHEADVECTOR && TARGET_ZVFH && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32")    (RVVM8DF "TARGET_VECTOR_ELEN_FP_64") (RVVM4DF "TARGET_VECTOR_ELEN_FP_64")    (RVVM2DF "TARGET_VECTOR_ELEN_FP_64") (RVVM1DF "TARGET_VECTOR_ELEN_FP_64") @@ -996,7 +996,7 @@ (define_mode_iterator VWCONVERTI [    (RVVM8SI "TARGET_ZVFH") (RVVM4SI "TARGET_ZVFH") (RVVM2SI "TARGET_ZVFH") (RVVM1SI "TARGET_ZVFH") -  (RVVMF2SI "TARGET_ZVFH") +  (RVVMF2SI "!TARGET_XTHEADVECTOR && TARGET_ZVFH")    (RVVM8DI "TARGET_VECTOR_ELEN_64 && TARGET_VECTOR_ELEN_FP_32")    (RVVM4DI "TARGET_VECTOR_ELEN_64 && TARGET_VECTOR_ELEN_FP_32") @@ -1045,7 +1045,7 @@ ]) (define_mode_iterator VQEXTI [ -  RVVM8SI RVVM4SI RVVM2SI RVVM1SI (RVVMF2SI "TARGET_MIN_VLEN > 32") +  RVVM8SI RVVM4SI RVVM2SI RVVM1SI (RVVMF2SI "!TARGET_XTHEADVECTOR && TARGET_MIN_VLEN > 32")    (RVVM8DI "TARGET_VECTOR_ELEN_64") (RVVM4DI "TARGET_VECTOR_ELEN_64")    (RVVM2DI "TARGET_VECTOR_ELEN_64") (RVVM1DI "TARGET_VECTOR_ELEN_64") @@ -1456,11 +1456,11 @@ ;; VINDEXED [VI8 VI16 VI32 (VI64 "TARGET_64BIT")]. (define_mode_iterator VINDEXED [ -  RVVM8QI RVVM4QI RVVM2QI RVVM1QI RVVMF2QI RVVMF4QI (RVVMF8QI "TARGET_MIN_VLEN > 32") +  RVVM8QI RVVM4QI RVVM2QI RVVM1QI (RVVMF2QI "!TARGET_XTHEADVECTOR") (RVVMF4QI "!TARGET_XTHEADVECTOR") (RVVMF8QI "!TARGET_XTHEADVECTOR && TARGET_MIN_VLEN > 32") -  RVVM8HI RVVM4HI RVVM2HI RVVM1HI RVVMF2HI (RVVMF4HI "TARGET_MIN_VLEN > 32") +  RVVM8HI RVVM4HI RVVM2HI RVVM1HI (RVVMF2HI "!TARGET_XTHEADVECTOR") (RVVMF4HI "!TARGET_XTHEADVECTOR && TARGET_MIN_VLEN > 32") -  RVVM8SI RVVM4SI RVVM2SI RVVM1SI (RVVMF2SI "TARGET_MIN_VLEN > 32") +  RVVM8SI RVVM4SI RVVM2SI RVVM1SI (RVVMF2SI "!TARGET_XTHEADVECTOR && TARGET_MIN_VLEN > 32")    (RVVM8DI "TARGET_VECTOR_ELEN_64 && TARGET_64BIT")    (RVVM4DI "TARGET_VECTOR_ELEN_64 && TARGET_64BIT") @@ -1468,12 +1468,12 @@    (RVVM1DI "TARGET_VECTOR_ELEN_64 && TARGET_64BIT")    (RVVM8HF "TARGET_ZVFH") (RVVM4HF "TARGET_ZVFH") (RVVM2HF "TARGET_ZVFH") -  (RVVM1HF "TARGET_ZVFH") (RVVMF2HF "TARGET_ZVFH") -  (RVVMF4HF "TARGET_ZVFH && TARGET_MIN_VLEN > 32") +  (RVVM1HF "TARGET_ZVFH") (RVVMF2HF "!TARGET_XTHEADVECTOR && TARGET_ZVFH") +  (RVVMF4HF "!TARGET_XTHEADVECTOR && TARGET_ZVFH && TARGET_MIN_VLEN > 32")    (RVVM8SF "TARGET_VECTOR_ELEN_FP_32") (RVVM4SF "TARGET_VECTOR_ELEN_FP_32")    (RVVM2SF "TARGET_VECTOR_ELEN_FP_32") (RVVM1SF "TARGET_VECTOR_ELEN_FP_32") -  (RVVMF2SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32") +  (RVVMF2SF "!TARGET_XTHEADVECTOR && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32")    (RVVM8DF "TARGET_VECTOR_ELEN_FP_64 && TARGET_64BIT")    (RVVM4DF "TARGET_VECTOR_ELEN_FP_64 && TARGET_64BIT") @@ -3173,11 +3173,11 @@ (define_mode_iterator V_VLS_F_CONVERT_SI [    (RVVM4HF "TARGET_ZVFH") (RVVM2HF "TARGET_ZVFH") (RVVM1HF "TARGET_ZVFH") -  (RVVMF2HF "TARGET_ZVFH") (RVVMF4HF "TARGET_ZVFH && TARGET_MIN_VLEN > 32") +  (RVVMF2HF "!TARGET_XTHEADVECTOR && TARGET_ZVFH") (RVVMF4HF "!TARGET_XTHEADVECTOR && TARGET_ZVFH && TARGET_MIN_VLEN > 32")    (RVVM8SF "TARGET_VECTOR_ELEN_FP_32") (RVVM4SF "TARGET_VECTOR_ELEN_FP_32")    (RVVM2SF "TARGET_VECTOR_ELEN_FP_32") (RVVM1SF "TARGET_VECTOR_ELEN_FP_32") -  (RVVMF2SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32") +  (RVVMF2SF "!TARGET_XTHEADVECTOR && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32")    (RVVM8DF "TARGET_VECTOR_ELEN_FP_64")    (RVVM4DF "TARGET_VECTOR_ELEN_FP_64") @@ -3290,12 +3290,12 @@ ]) (define_mode_iterator V_VLS_F_CONVERT_DI [ -  (RVVM2HF "TARGET_ZVFH") (RVVM1HF "TARGET_ZVFH") (RVVMF2HF "TARGET_ZVFH") -  (RVVMF4HF "TARGET_ZVFH && TARGET_MIN_VLEN > 32") +  (RVVM2HF "TARGET_ZVFH") (RVVM1HF "TARGET_ZVFH") (RVVMF2HF "!TARGET_XTHEADVECTOR && TARGET_ZVFH") +  (RVVMF4HF "!TARGET_XTHEADVECTOR && TARGET_ZVFH && TARGET_MIN_VLEN > 32")    (RVVM4SF "TARGET_VECTOR_ELEN_FP_32") (RVVM2SF "TARGET_VECTOR_ELEN_FP_32")    (RVVM1SF "TARGET_VECTOR_ELEN_FP_32") -  (RVVMF2SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32") +  (RVVMF2SF "!TARGET_XTHEADVECTOR && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32")    (RVVM8DF "TARGET_VECTOR_ELEN_FP_64") (RVVM4DF "TARGET_VECTOR_ELEN_FP_64")    (RVVM2DF "TARGET_VECTOR_ELEN_FP_64") (RVVM1DF "TARGET_VECTOR_ELEN_FP_64") diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md index b5a9055cdc4..cb30c9ae97c 100644 --- a/gcc/config/riscv/vector.md +++ b/gcc/config/riscv/vector.md @@ -83,7 +83,7 @@ ;; check. However, we need default value of SEW for vsetvl instruction since there ;; is no field for ratio in the vsetvl instruction encoding. (define_attr "sew" "" -  (cond [(eq_attr "mode" "RVVMF64BI,RVVMF32BI,RVVMF16BI,RVVMF8BI,RVVMF4BI,RVVMF2BI,RVVM1BI,\ +  (cond [(eq_attr "mode" "RVVMF8BI,RVVMF4BI,RVVMF2BI,RVVM1BI,\   RVVM8QI,RVVM4QI,RVVM2QI,RVVM1QI,RVVMF2QI,RVVMF4QI,RVVMF8QI,\   RVVM1x8QI,RVVMF2x8QI,RVVMF4x8QI,RVVMF8x8QI,\   RVVM1x7QI,RVVMF2x7QI,RVVMF4x7QI,RVVMF8x7QI,\ @@ -95,6 +95,18 @@   V1QI,V2QI,V4QI,V8QI,V16QI,V32QI,V64QI,V128QI,V256QI,V512QI,V1024QI,V2048QI,V4096QI,\   V1BI,V2BI,V4BI,V8BI,V16BI,V32BI,V64BI,V128BI,V256BI,V512BI,V1024BI,V2048BI,V4096BI") (const_int 8) + (eq_attr "mode" "RVVMF16BI") +    (if_then_else (match_test "TARGET_XTHEADVECTOR") +      (const_int 16) +      (const_int 8)) + (eq_attr "mode" "RVVMF32BI") +    (if_then_else (match_test "TARGET_XTHEADVECTOR") +      (const_int 32) +      (const_int 8)) + (eq_attr "mode" "RVVMF64BI") +    (if_then_else (match_test "TARGET_XTHEADVECTOR") +      (const_int 64) +      (const_int 8)) (eq_attr "mode" "RVVM8HI,RVVM4HI,RVVM2HI,RVVM1HI,RVVMF2HI,RVVMF4HI,\   RVVM1x8HI,RVVMF2x8HI,RVVMF4x8HI,\   RVVM1x7HI,RVVMF2x7HI,RVVMF4x7HI,\ @@ -155,9 +167,9 @@ (eq_attr "mode" "RVVM4QI,RVVMF2BI") (symbol_ref "riscv_vector::LMUL_4") (eq_attr "mode" "RVVM2QI,RVVMF4BI") (symbol_ref "riscv_vector::LMUL_2") (eq_attr "mode" "RVVM1QI,RVVMF8BI") (symbol_ref "riscv_vector::LMUL_1") - (eq_attr "mode" "RVVMF2QI,RVVMF16BI") (symbol_ref "riscv_vector::LMUL_F2") - (eq_attr "mode" "RVVMF4QI,RVVMF32BI") (symbol_ref "riscv_vector::LMUL_F4") - (eq_attr "mode" "RVVMF8QI,RVVMF64BI") (symbol_ref "riscv_vector::LMUL_F8") + (eq_attr "mode" "RVVMF2QI,RVVMF16BI") (symbol_ref "TARGET_XTHEADVECTOR ? riscv_vector::LMUL_1 : riscv_vector::LMUL_F2") + (eq_attr "mode" "RVVMF4QI,RVVMF32BI") (symbol_ref "TARGET_XTHEADVECTOR ? riscv_vector::LMUL_1 : riscv_vector::LMUL_F4") + (eq_attr "mode" "RVVMF8QI,RVVMF64BI") (symbol_ref "TARGET_XTHEADVECTOR ? riscv_vector::LMUL_1 : riscv_vector::LMUL_F8") (eq_attr "mode" "RVVM8HI") (symbol_ref "riscv_vector::LMUL_8") (eq_attr "mode" "RVVM4HI") (symbol_ref "riscv_vector::LMUL_4") (eq_attr "mode" "RVVM2HI") (symbol_ref "riscv_vector::LMUL_2") @@ -428,6 +440,10 @@   vislide1up,vislide1down,vfslide1up,vfslide1down,\   vgather,vcompress,vlsegdux,vlsegdox,vssegtux,vssegtox")    (const_int INVALID_ATTRIBUTE) + (and (eq_attr "type" "vlde,vste,vlsegde,vssegte,vlsegds,vssegts,\ +        vlsegdff,vssegtux,vlsegdox,vlsegdux") +       (match_test "TARGET_XTHEADVECTOR")) +    (const_int INVALID_ATTRIBUTE) (eq_attr "mode" "RVVM8QI,RVVM1BI") (const_int 1) (eq_attr "mode" "RVVM4QI,RVVMF2BI") (const_int 2) (eq_attr "mode" "RVVM2QI,RVVMF4BI") (const_int 4) @@ -888,6 +904,8 @@ (symbol_ref "riscv_vector::FRM_DYN")] (symbol_ref "riscv_vector::FRM_NONE"))) +(include "thead-vector.md") + ;; ----------------------------------------------------------------- ;; ---- Miscellaneous Operations ;; ----------------------------------------------------------------- @@ -1061,6 +1079,12 @@         - We can not leave it to TARGET_SECONDARY_RELOAD since it happens before spilling. The clobber scratch is used by spilling fractional registers in IRA/LRA so it's too early.  */ +  if (TARGET_XTHEADVECTOR) +    { +      emit_insn (gen_pred_th_whole_mov (mode, operands[0], operands[1], + RVV_VLMAX, GEN_INT(riscv_vector::VLMAX))); +      DONE; +    }    if (riscv_vector::legitimize_move (operands[0], &operands[1]))      DONE; @@ -1097,7 +1121,7 @@ (define_insn "*mov_whole"    [(set (match_operand:V_WHOLE 0 "reg_or_mem_operand" "=vr, m,vr") (match_operand:V_WHOLE 1 "reg_or_mem_operand" "  m,vr,vr"))] -  "TARGET_VECTOR" +  "TARGET_VECTOR && !TARGET_XTHEADVECTOR"    "@     vl%m1re.v\t%0,%1     vs%m1r.v\t%1,%0 @@ -1118,6 +1142,13 @@ (match_operand:VB 1 "general_operand"))]    "TARGET_VECTOR" { +  if (TARGET_XTHEADVECTOR) +    { +      emit_insn (gen_pred_th_whole_mov (mode, operands[0], operands[1], + RVV_VLMAX, GEN_INT(riscv_vector::VLMAX))); +      DONE; +    } +    if (riscv_vector::legitimize_move (operands[0], &operands[1]))      DONE; }) @@ -1125,7 +1156,7 @@ (define_insn "*mov"    [(set (match_operand:VB 0 "register_operand" "=vr") (match_operand:VB 1 "register_operand" " vr"))] -  "TARGET_VECTOR" +  "TARGET_VECTOR && !TARGET_XTHEADVECTOR"    "vmv1r.v\t%0,%1"    [(set_attr "type" "vmov")     (set_attr "mode" "")]) @@ -1511,7 +1542,7 @@     (match_dup 4)     (match_dup 5)] UNSPEC_VSETVL))]    "TARGET_VECTOR" -  "vset%i1vli\t%0,%1,e%2,%m3,t%p4,m%p5" +  { return TARGET_XTHEADVECTOR ? "vsetvli\t%0,%1,e%2,%m3" : "vset%i1vli\t%0,%1,e%2,%m3,t%p4,m%p5"; }    [(set_attr "type" "vsetvl")     (set_attr "mode" "")     (set (attr "sew") (symbol_ref "INTVAL (operands[2])")) @@ -1529,7 +1560,7 @@    (match_operand 2 "const_int_operand" "i")    (match_operand 3 "const_int_operand" "i")] UNSPEC_VSETVL))]    "TARGET_VECTOR" -  "vsetvli\tzero,zero,e%0,%m1,t%p2,m%p3" +  { return TARGET_XTHEADVECTOR ? "vsetvli\tzero,zero,e%0,%m1" : "vsetvli\tzero,zero,e%0,%m1,t%p2,m%p3"; }    [(set_attr "type" "vsetvl")     (set_attr "mode" "SI")     (set (attr "sew") (symbol_ref "INTVAL (operands[0])")) @@ -1551,7 +1582,7 @@     (match_operand 3 "const_int_operand" "i")     (match_operand 4 "const_int_operand" "i")] UNSPEC_VSETVL))]    "TARGET_VECTOR" -  "vset%i0vli\tzero,%0,e%1,%m2,t%p3,m%p4" +  { return TARGET_XTHEADVECTOR ? "vsetvli\tzero,%0,e%1,%m2" : "vset%i0vli\tzero,%0,e%1,%m2,t%p3,m%p4"; }    [(set_attr "type" "vsetvl")     (set_attr "mode" "")     (set (attr "sew") (symbol_ref "INTVAL (operands[1])")) @@ -3680,7 +3711,7 @@   (any_extend:VWEXTI     (match_operand: 3 "register_operand"   "W21,W21,W21,W21,W42,W42,W42,W42,W84,W84,W84,W84,   vr,   vr"))   (match_operand:VWEXTI 2 "vector_merge_operand"           " vu, vu,  0,  0, vu, vu,  0,  0, vu, vu,  0,  0,   vu,    0")))] -  "TARGET_VECTOR" +  "TARGET_VECTOR && !TARGET_XTHEADVECTOR"    "vext.vf2\t%0,%3%p1"    [(set_attr "type" "vext")     (set_attr "mode" "") @@ -3701,7 +3732,7 @@   (any_extend:VQEXTI     (match_operand: 3 "register_operand"   "W43,W43,W43,W43,W86,W86,W86,W86,   vr,   vr"))   (match_operand:VQEXTI 2 "vector_merge_operand"         " vu, vu,  0,  0, vu, vu,  0,  0,   vu,    0")))] -  "TARGET_VECTOR" +  "TARGET_VECTOR && !TARGET_XTHEADVECTOR"    "vext.vf4\t%0,%3%p1"    [(set_attr "type" "vext")     (set_attr "mode" "") @@ -3722,7 +3753,7 @@   (any_extend:VOEXTI     (match_operand: 3 "register_operand"   "W87,W87,W87,W87,   vr,   vr"))   (match_operand:VOEXTI 2 "vector_merge_operand"        " vu, vu,  0,  0,   vu,    0")))] -  "TARGET_VECTOR" +  "TARGET_VECTOR && !TARGET_XTHEADVECTOR"    "vext.vf8\t%0,%3%p1"    [(set_attr "type" "vext")     (set_attr "mode" "") diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/abi-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/abi-1.c index 2e0e12aa045..2eef9e1e1a8 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/abi-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/abi-1.c @@ -1,4 +1,4 @@ -/* { dg-do compile } */ +/* { dg-do compile { target { ! riscv_xtheadvector } } } */ /* { dg-skip-if "test rvv intrinsic" { *-*-* } { "*" } { "-march=rv*v*" } } */ void foo0 () {__rvv_bool64_t t;} diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pragma-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pragma-1.c index 3d81b179235..ef329e30785 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/pragma-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pragma-1.c @@ -1,4 +1,4 @@ /* { dg-do compile } */ /* { dg-options "-O3 -march=rv32gc -mabi=ilp32d" } */ -#pragma riscv intrinsic "vector" /* { dg-error {#pragma riscv intrinsic' option 'vector' needs 'V' extension enabled} } */ +#pragma riscv intrinsic "vector" /* { dg-error {#pragma riscv intrinsic' option 'vector' needs 'V' or 'XTHEADVECTOR' extension enabled} } */ diff --git a/gcc/testsuite/lib/target-supports.exp b/gcc/testsuite/lib/target-supports.exp index 7f13ff0ca56..70df6b1401c 100644 --- a/gcc/testsuite/lib/target-supports.exp +++ b/gcc/testsuite/lib/target-supports.exp @@ -1952,6 +1952,18 @@ proc check_effective_target_riscv_zbb { } {      }] } +# Return 1 if the target arch supports the XTheadVector extension, 0 otherwise. +# Cache the result. + +proc check_effective_target_riscv_xtheadvector { } { +    return [check_no_compiler_messages riscv_ext_xtheadvector assembly { +       #ifndef __riscv_xtheadvector +       #error "Not __riscv_xtheadvector" +       #endif +    }] +} + + # Return 1 if we can execute code when using dg-add-options riscv_v proc check_effective_target_riscv_v_ok { } {