diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc
index fcca062a8709..eea427b1ca51 100644
--- a/gcc/config/rs6000/rs6000.cc
+++ b/gcc/config/rs6000/rs6000.cc
@@ -21998,11 +21998,11 @@ rs6000_rtx_costs (rtx x, machine_mode mode, int outer_code,
       if (!TARGET_MODULO && (code == MOD || code == UMOD))
 	*total += COSTS_N_INSNS (2);
       return false;
 
     case CTZ:
-      *total = COSTS_N_INSNS (TARGET_CTZ ? 1 : 4);
+      *total = COSTS_N_INSNS (TARGET_MODULO ? 1 : 4);
       return false;
 
     case FFS:
       *total = COSTS_N_INSNS (4);
       return false;
diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h
index eb7b21584970..ee887efd1122 100644
--- a/gcc/config/rs6000/rs6000.h
+++ b/gcc/config/rs6000/rs6000.h
@@ -456,20 +456,17 @@ extern int rs6000_vector_align[];
 			 || TARGET_PPC_GPOPT	/* 970/power4 */	\
 			 || TARGET_POPCNTB	/* ISA 2.02 */		\
 			 || TARGET_CMPB		/* ISA 2.05 */		\
 			 || TARGET_POPCNTD)	/* ISA 2.06 */
 
-#define TARGET_FCTIDZ	TARGET_FCFID
 #define TARGET_STFIWX	TARGET_PPC_GFXOPT
 #define TARGET_LFIWAX	TARGET_CMPB
 #define TARGET_LFIWZX	TARGET_POPCNTD
 #define TARGET_FCFIDS	TARGET_POPCNTD
 #define TARGET_FCFIDU	TARGET_POPCNTD
 #define TARGET_FCFIDUS	TARGET_POPCNTD
 #define TARGET_FCTIDUZ	TARGET_POPCNTD
-#define TARGET_FCTIWUZ	TARGET_POPCNTD
-#define TARGET_CTZ	TARGET_MODULO
 #define TARGET_EXTSWSLI	(TARGET_MODULO && TARGET_POWERPC64)
 #define TARGET_MADDLD	TARGET_MODULO
 
 #define TARGET_XSCVDPSPN	(TARGET_DIRECT_MOVE || TARGET_P8_VECTOR)
 #define TARGET_XSCVSPDPN	(TARGET_DIRECT_MOVE || TARGET_P8_VECTOR)
@@ -1751,11 +1748,11 @@ typedef struct rs6000_args
 
 /* The CTZ patterns that are implemented in terms of CLZ return -1 for input of
    zero.  The hardware instructions added in Power9 and the sequences using
    popcount return 32 or 64.  */
 #define CTZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE)				\
-  (TARGET_CTZ || TARGET_POPCNTD						\
+  (TARGET_MODULO || TARGET_POPCNTD						\
    ? ((VALUE) = GET_MODE_BITSIZE (MODE), 2)				\
    : ((VALUE) = -1, 2))
 
 /* Specify the machine mode that pointers have.
    After generation of rtl, the compiler makes no further distinction
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index ad5a4cf2ef83..619a87374734 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -2414,11 +2414,11 @@ (define_insn "clz<mode>2"
 (define_expand "ctz<mode>2"
    [(set (match_operand:GPR 0 "gpc_reg_operand")
 	 (ctz:GPR (match_operand:GPR 1 "gpc_reg_operand")))]
   ""
 {
-  if (TARGET_CTZ)
+  if (TARGET_MODULO)
     {
       emit_insn (gen_ctz<mode>2_hw (operands[0], operands[1]));
       DONE;
     }
 
@@ -2445,11 +2445,11 @@ (define_expand "ctz<mode>2"
 })
 
 (define_insn "ctz<mode>2_hw"
   [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
 	(ctz:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")))]
-  "TARGET_CTZ"
+  "TARGET_MODULO"
   "cnttz<wd> %0,%1"
   [(set_attr "type" "cntlz")])
 
 (define_expand "ffs<mode>2"
   [(set (match_operand:GPR 0 "gpc_reg_operand")
@@ -6326,11 +6326,11 @@ (define_insn_and_split "*fix<uns>_trunc<SFDF:mode><QHSI:mode>2_mem"
 })
 
 (define_expand "fixuns_trunc<mode>si2"
   [(set (match_operand:SI 0 "gpc_reg_operand")
 	(unsigned_fix:SI (match_operand:SFDF 1 "gpc_reg_operand")))]
-  "TARGET_HARD_FLOAT && TARGET_FCTIWUZ && TARGET_STFIWX"
+  "TARGET_HARD_FLOAT && TARGET_POPCNTD && TARGET_STFIWX"
 {
   if (!TARGET_P8_VECTOR)
     {
       emit_insn (gen_fixuns_trunc<mode>si2_stfiwx (operands[0], operands[1]));
       DONE;
@@ -6339,11 +6339,11 @@ (define_expand "fixuns_trunc<mode>si2"
 
 (define_insn_and_split "fixuns_trunc<mode>si2_stfiwx"
   [(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
 	(unsigned_fix:SI (match_operand:SFDF 1 "gpc_reg_operand" "d")))
    (clobber (match_scratch:DI 2 "=d"))]
-  "TARGET_HARD_FLOAT && TARGET_FCTIWUZ
+  "TARGET_HARD_FLOAT && TARGET_POPCNTD
    && TARGET_STFIWX && can_create_pseudo_p ()
    && !TARGET_P8_VECTOR"
   "#"
   "&& 1"
   [(pc)]
@@ -6542,11 +6542,11 @@ (define_insn "fctiwz_<mode>"
 (define_insn "fctiwuz_<mode>"
   [(set (match_operand:DI 0 "gpc_reg_operand" "=d,wa")
 	(unspec:DI [(unsigned_fix:SI
 		     (match_operand:SFDF 1 "gpc_reg_operand" "d,wa"))]
 		   UNSPEC_FCTIWUZ))]
-  "TARGET_HARD_FLOAT && TARGET_FCTIWUZ"
+  "TARGET_HARD_FLOAT && TARGET_POPCNTD"
   "@
    fctiwuz %0,%1
    xscvdpuxws %x0,%x1"
   [(set_attr "type" "fp")])
 
