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Mon, 19 Sep 2022 23:19:16 GMT Received: from smtpav06.dal12v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 9543A58043; Mon, 19 Sep 2022 23:19:16 +0000 (GMT) Received: from smtpav06.dal12v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 0A2AC58059; Mon, 19 Sep 2022 23:19:16 +0000 (GMT) Received: from sig-9-77-144-60.ibm.com (unknown [9.77.144.60]) by smtpav06.dal12v.mail.ibm.com (Postfix) with ESMTP; Mon, 19 Sep 2022 23:19:15 +0000 (GMT) Message-ID: <2cc39864b6a4c52b948f86d54e5988e4d5a37ecb.camel@vnet.ibm.com> Subject: [PATCH, rs6000] Eliminate TARGET_CTZ,TARGET_FCTIDZ,FCTIWUZ defines To: GCC patches Date: Mon, 19 Sep 2022 18:19:15 -0500 X-Mailer: Evolution 3.28.5 (3.28.5-18.el8) Mime-Version: 1.0 X-TM-AS-GCONF: 00 X-Proofpoint-ORIG-GUID: mJNcy8YAJGKJWpvv5FuWRSmldwqp0p2q X-Proofpoint-GUID: 6dvbPB_x9cz0ItfUdbKPOdJ8XozDqogO X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.895,Hydra:6.0.528,FMLib:17.11.122.1 definitions=2022-09-19_05,2022-09-16_01,2022-06-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 suspectscore=0 mlxlogscore=708 spamscore=0 lowpriorityscore=0 bulkscore=0 mlxscore=0 impostorscore=0 adultscore=0 priorityscore=1501 phishscore=0 malwarescore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2209130000 definitions=main-2209190154 X-Spam-Status: No, score=-10.6 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_EF, GIT_PATCH_0, RCVD_IN_MSPIKE_H2, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: will schmidt via Gcc-patches From: will schmidt Reply-To: will schmidt Cc: David Edelsohn , Segher Boessenkool Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1744442076270370599?= X-GMAIL-MSGID: =?utf-8?q?1744442076270370599?= [PATCH, rs6000] Eliminate TARGET_CTZ,TARGET_FCTIDZ,FCTIWUZ defines Hi, This is the first of a batch of changes that eliminate a number of define TARGET_foo entries we have collected over time. TARGET_CTZ is defined as TARGET_MODULO, and has a low number of uses. References to TARGET_CTZ should be safe to replace with TARGET_MODULO throughout. TARGET_FCTIDZ is entirely unused, and safe to remove. TARGET_FCTIWUZ has a low number of uses, and can be directly replaced with TARGET_POPCNTD. This eliminates three defines. There should be no codegen changes, and this has regtested OK. OK for trunk? Thanks, gcc/ * config/rs6000/rs6000.h (TARGET_CTZ): Replace with TARGET_MODULO. (TARGET_FCTIDZ): Remove. (TARGET_FCTIWUZ): Replace with TARGET_POPCNTD. * config/rs6000/rs6000.cc (TARGET_CTZ): Replace with TARGET_MODULO. * config/rs6000/rs6000.md (ctz2): Replace TARGET_CTZ with TARGET_MODULO. (ctz2_hw): Same. (fixuns_truncsi2): Replace TARGET_FCTIWUZ with TARGET_POPCNTD. (fixuns_truncsi2_stfiwx): Same. (fctiwz_): Same. diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc index fcca062a8709..eea427b1ca51 100644 --- a/gcc/config/rs6000/rs6000.cc +++ b/gcc/config/rs6000/rs6000.cc @@ -21998,11 +21998,11 @@ rs6000_rtx_costs (rtx x, machine_mode mode, int outer_code, if (!TARGET_MODULO && (code == MOD || code == UMOD)) *total += COSTS_N_INSNS (2); return false; case CTZ: - *total = COSTS_N_INSNS (TARGET_CTZ ? 1 : 4); + *total = COSTS_N_INSNS (TARGET_MODULO ? 1 : 4); return false; case FFS: *total = COSTS_N_INSNS (4); return false; diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h index eb7b21584970..ee887efd1122 100644 --- a/gcc/config/rs6000/rs6000.h +++ b/gcc/config/rs6000/rs6000.h @@ -456,20 +456,17 @@ extern int rs6000_vector_align[]; || TARGET_PPC_GPOPT /* 970/power4 */ \ || TARGET_POPCNTB /* ISA 2.02 */ \ || TARGET_CMPB /* ISA 2.05 */ \ || TARGET_POPCNTD) /* ISA 2.06 */ -#define TARGET_FCTIDZ TARGET_FCFID #define TARGET_STFIWX TARGET_PPC_GFXOPT #define TARGET_LFIWAX TARGET_CMPB #define TARGET_LFIWZX TARGET_POPCNTD #define TARGET_FCFIDS TARGET_POPCNTD #define TARGET_FCFIDU TARGET_POPCNTD #define TARGET_FCFIDUS TARGET_POPCNTD #define TARGET_FCTIDUZ TARGET_POPCNTD -#define TARGET_FCTIWUZ TARGET_POPCNTD -#define TARGET_CTZ TARGET_MODULO #define TARGET_EXTSWSLI (TARGET_MODULO && TARGET_POWERPC64) #define TARGET_MADDLD TARGET_MODULO #define TARGET_XSCVDPSPN (TARGET_DIRECT_MOVE || TARGET_P8_VECTOR) #define TARGET_XSCVSPDPN (TARGET_DIRECT_MOVE || TARGET_P8_VECTOR) @@ -1751,11 +1748,11 @@ typedef struct rs6000_args /* The CTZ patterns that are implemented in terms of CLZ return -1 for input of zero. The hardware instructions added in Power9 and the sequences using popcount return 32 or 64. */ #define CTZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \ - (TARGET_CTZ || TARGET_POPCNTD \ + (TARGET_MODULO || TARGET_POPCNTD \ ? ((VALUE) = GET_MODE_BITSIZE (MODE), 2) \ : ((VALUE) = -1, 2)) /* Specify the machine mode that pointers have. After generation of rtl, the compiler makes no further distinction diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md index ad5a4cf2ef83..619a87374734 100644 --- a/gcc/config/rs6000/rs6000.md +++ b/gcc/config/rs6000/rs6000.md @@ -2414,11 +2414,11 @@ (define_insn "clz2" (define_expand "ctz2" [(set (match_operand:GPR 0 "gpc_reg_operand") (ctz:GPR (match_operand:GPR 1 "gpc_reg_operand")))] "" { - if (TARGET_CTZ) + if (TARGET_MODULO) { emit_insn (gen_ctz2_hw (operands[0], operands[1])); DONE; } @@ -2445,11 +2445,11 @@ (define_expand "ctz2" }) (define_insn "ctz2_hw" [(set (match_operand:GPR 0 "gpc_reg_operand" "=r") (ctz:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")))] - "TARGET_CTZ" + "TARGET_MODULO" "cnttz %0,%1" [(set_attr "type" "cntlz")]) (define_expand "ffs2" [(set (match_operand:GPR 0 "gpc_reg_operand") @@ -6326,11 +6326,11 @@ (define_insn_and_split "*fix_trunc2_mem" }) (define_expand "fixuns_truncsi2" [(set (match_operand:SI 0 "gpc_reg_operand") (unsigned_fix:SI (match_operand:SFDF 1 "gpc_reg_operand")))] - "TARGET_HARD_FLOAT && TARGET_FCTIWUZ && TARGET_STFIWX" + "TARGET_HARD_FLOAT && TARGET_POPCNTD && TARGET_STFIWX" { if (!TARGET_P8_VECTOR) { emit_insn (gen_fixuns_truncsi2_stfiwx (operands[0], operands[1])); DONE; @@ -6339,11 +6339,11 @@ (define_expand "fixuns_truncsi2" (define_insn_and_split "fixuns_truncsi2_stfiwx" [(set (match_operand:SI 0 "nonimmediate_operand" "=rm") (unsigned_fix:SI (match_operand:SFDF 1 "gpc_reg_operand" "d"))) (clobber (match_scratch:DI 2 "=d"))] - "TARGET_HARD_FLOAT && TARGET_FCTIWUZ + "TARGET_HARD_FLOAT && TARGET_POPCNTD && TARGET_STFIWX && can_create_pseudo_p () && !TARGET_P8_VECTOR" "#" "&& 1" [(pc)] @@ -6542,11 +6542,11 @@ (define_insn "fctiwz_" (define_insn "fctiwuz_" [(set (match_operand:DI 0 "gpc_reg_operand" "=d,wa") (unspec:DI [(unsigned_fix:SI (match_operand:SFDF 1 "gpc_reg_operand" "d,wa"))] UNSPEC_FCTIWUZ))] - "TARGET_HARD_FLOAT && TARGET_FCTIWUZ" + "TARGET_HARD_FLOAT && TARGET_POPCNTD" "@ fctiwuz %0,%1 xscvdpuxws %x0,%x1" [(set_attr "type" "fp")])