diff mbox series

[v2,2/9] MIPS: Add MOVx instructions support for mips16e2

Message ID	29fac431d96e573ab1932a60ce9b9be6a6a600fe.1683871682.git.jie.mei@oss.cipunited.com
State	Accepted
Headers	Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) client-ip=8.43.85.97; DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 1003A3858CDA Mime-Version: 1.0 References: <cover.1683871682.git.jie.mei@oss.cipunited.com> From: "Jie Mei" <jie.mei@oss.cipunited.com> In-Reply-To: <cover.1683871682.git.jie.mei@oss.cipunited.com> To: <gcc-patches@gcc.gnu.org> Message-Id: <29fac431d96e573ab1932a60ce9b9be6a6a600fe.1683871682.git.jie.mei@oss.cipunited.com> Subject: [PATCH v2 2/9] MIPS: Add MOVx instructions support for mips16e2 Date: Fri, 12 May 2023 14:18:49 +0800 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Precedence: list Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" <gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org> X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?=
Series	MIPS: Add MIPS16e2 ASE instrucions. \| [v2,0/9] MIPS: Add MIPS16e2 ASE instrucions. [v2,1/9] MIPS: Add basic support for mips16e2 [v2,2/9] MIPS: Add MOVx instructions support for mips16e2 [v2,3/9] MIPS: Add instruction about global pointer register for mips16e2 [v2,4/9] MIPS: Add bitwise instructions for mips16e2 [v2,5/9] MIPS: Add LUI instruction for mips16e2 [v2,6/9] MIPS: Add load/store word left/right instructions for mips16e2 [v2,7/9] MIPS: Use ISA_HAS_9BIT_DISPLACEMENT for mips16e2 [v2,8/9] MIPS: Add CACHE instruction for mips16e2 [v2,9/9] MIPS: Make mips16e2 generating ZEB/ZEH instead of ANDI under certain conditions

Checks

Context	Check	Description
snail/gcc-patch-check	success	Github commit url

Commit Message

梅杰 May 12, 2023, 6:18 a.m. UTC

  This patch adds MOVx instructions from mips16e2
(movn,movz,movtn,movtz) with corresponding tests.

gcc/ChangeLog:

	* config/mips/mips.h(ISA_HAS_CONDMOVE): Add condition for ISA_HAS_MIPS16E2.
	* config/mips/mips.md(*mov<GPR:mode>_on_<MOVECC:mode>): Add logics for MOVx insts.
	(*mov<GPR:mode>_on_<MOVECC:mode>_mips16e2): Generate MOVx instruction.
	(*mov<GPR:mode>_on_<GPR2:mode>_ne): Add logics for MOVx insts.
	(*mov<GPR:mode>_on_<GPR2:mode>_ne_mips16e2): Generate MOVx instruction.
	* config/mips/predicates.md(reg_or_0_operand_mips16e2): New predicate for MOVx insts.

gcc/testsuite/ChangeLog:

	* gcc.target/mips/mips16e2-cmov.c: Added tests for MOVx instructions.
---
 gcc/config/mips/mips.h                        |  1 +
 gcc/config/mips/mips.md                       | 38 ++++++++++-
 gcc/config/mips/predicates.md                 |  6 ++
 gcc/testsuite/gcc.target/mips/mips16e2-cmov.c | 68 +++++++++++++++++++
 4 files changed, 111 insertions(+), 2 deletions(-)
 create mode 100644 gcc/testsuite/gcc.target/mips/mips16e2-cmov.c

diff mbox series

Patch

diff --git a/gcc/config/mips/mips.h b/gcc/config/mips/mips.h
index 8db92c6468f..c396e5ea2f3 100644
--- a/gcc/config/mips/mips.h
+++ b/gcc/config/mips/mips.h
@@ -1081,6 +1081,7 @@  struct mips_cpu_info {
    ST Loongson 2E/2F.  */
 #define ISA_HAS_CONDMOVE        (ISA_HAS_FP_CONDMOVE			\
 				 || TARGET_MIPS5900			\
+				 || ISA_HAS_MIPS16E2			\
 				 || TARGET_LOONGSON_2EF)
 
 /* ISA has LDC1 and SDC1.  */
diff --git a/gcc/config/mips/mips.md b/gcc/config/mips/mips.md
index ac1d77afc7d..48d5f419ce0 100644
--- a/gcc/config/mips/mips.md
+++ b/gcc/config/mips/mips.md
@@ -7341,26 +7341,60 @@ 
 		 (const_int 0)])
 	 (match_operand:GPR 2 "reg_or_0_operand" "dJ,0")
 	 (match_operand:GPR 3 "reg_or_0_operand" "0,dJ")))]
-  "ISA_HAS_CONDMOVE"
+  "!TARGET_MIPS16 && ISA_HAS_CONDMOVE"
   "@
     mov%T4\t%0,%z2,%1
     mov%t4\t%0,%z3,%1"
   [(set_attr "type" "condmove")
    (set_attr "mode" "<GPR:MODE>")])
 
+(define_insn "*mov<GPR:mode>_on_<MOVECC:mode>_mips16e2"
+  [(set (match_operand:GPR 0 "register_operand" "=d,d,d,d")
+    (if_then_else:GPR
+     (match_operator 4 "equality_operator"
+        [(match_operand:MOVECC 1 "register_operand" "<MOVECC:reg>,<MOVECC:reg>,t,t")
+         (const_int 0)])
+     (match_operand:GPR 2 "reg_or_0_operand_mips16e2" "dJ,0,dJ,0")
+     (match_operand:GPR 3 "reg_or_0_operand_mips16e2" "0,dJ,0,dJ")))]
+  "ISA_HAS_MIPS16E2 && ISA_HAS_CONDMOVE"
+  "@
+    mov%T4\t%0,%z2,%1
+    mov%t4\t%0,%z3,%1
+    movt%T4\t%0,%z2
+    movt%t4\t%0,%z3"
+  [(set_attr "type" "condmove")
+   (set_attr "mode" "<GPR:MODE>")
+   (set_attr "extended_mips16" "yes")])
+
 (define_insn "*mov<GPR:mode>_on_<GPR2:mode>_ne"
   [(set (match_operand:GPR 0 "register_operand" "=d,d")
        (if_then_else:GPR
         (match_operand:GPR2 1 "register_operand" "<GPR2:reg>,<GPR2:reg>")
         (match_operand:GPR 2 "reg_or_0_operand" "dJ,0")
         (match_operand:GPR 3 "reg_or_0_operand" "0,dJ")))]
-  "ISA_HAS_CONDMOVE"
+  "!TARGET_MIPS16 && ISA_HAS_CONDMOVE"
   "@
     movn\t%0,%z2,%1
     movz\t%0,%z3,%1"
   [(set_attr "type" "condmove")
    (set_attr "mode" "<GPR:MODE>")])
 
+(define_insn "*mov<GPR:mode>_on_<GPR2:mode>_ne_mips16e2"
+  [(set (match_operand:GPR 0 "register_operand" "=d,d,d,d")
+       (if_then_else:GPR
+        (match_operand:GPR2 1 "register_operand" "<GPR2:reg>,<GPR2:reg>,t,t")
+        (match_operand:GPR 2 "reg_or_0_operand_mips16e2" "dJ,0,dJ,0")
+        (match_operand:GPR 3 "reg_or_0_operand_mips16e2" "0,dJ,0,dJ")))]
+ "ISA_HAS_MIPS16E2 && ISA_HAS_CONDMOVE"
+  "@
+    movn\t%0,%z2,%1
+    movz\t%0,%z3,%1
+    movtn\t%0,%z2
+    movtz\t%0,%z3"
+  [(set_attr "type" "condmove")
+   (set_attr "mode" "<GPR:MODE>")
+   (set_attr "extended_mips16" "yes")])
+
 (define_insn "*mov<SCALARF:mode>_on_<MOVECC:mode>"
   [(set (match_operand:SCALARF 0 "register_operand" "=f,f")
 	(if_then_else:SCALARF
diff --git a/gcc/config/mips/predicates.md b/gcc/config/mips/predicates.md
index 87460a64652..e2cd5a8c65f 100644
--- a/gcc/config/mips/predicates.md
+++ b/gcc/config/mips/predicates.md
@@ -114,6 +114,12 @@ 
 	    (not (match_test "TARGET_MIPS16")))
        (match_operand 0 "register_operand")))
 
+(define_predicate "reg_or_0_operand_mips16e2"
+  (ior (and (match_operand 0 "const_0_operand")
+            (ior (not (match_test "TARGET_MIPS16"))
+                 (match_test "ISA_HAS_MIPS16E2")))
+       (match_operand 0 "register_operand")))
+
 (define_predicate "const_1_operand"
   (and (match_code "const_int,const_double,const_vector")
        (match_test "op == CONST1_RTX (GET_MODE (op))")))
diff --git a/gcc/testsuite/gcc.target/mips/mips16e2-cmov.c b/gcc/testsuite/gcc.target/mips/mips16e2-cmov.c
new file mode 100644
index 00000000000..6e9dd82ebf3
--- /dev/null
+++ b/gcc/testsuite/gcc.target/mips/mips16e2-cmov.c
@@ -0,0 +1,68 @@ 
+/* { dg-options "-mno-abicalls -mgpopt -G8 -mabi=32 -mips16 -mmips16e2" } */
+/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */
+
+/* Test MOVN.  */
+
+/* { dg-final { scan-assembler-times "test01:.*\tmovn\t.*test01\n" 1 } } */
+int
+test01 (int a, int b, int c)
+{
+  return (a==0) ? b : c;
+}
+
+/* { dg-final { scan-assembler-times "test02:.*\tmovn\t\\\$.,\\\$0.*test02\n" 1 } } */
+int
+test02 (int a, int b, int c)
+{
+  return (a==0) ? b : 0;
+}
+
+/* Test MOVZ.  */
+
+/* { dg-final { scan-assembler-times "test03:.*\tmovz\t.*test03\n" 1 } } */
+int
+test03 (int a, int b, int c)
+{
+  return a ? b : c;
+}
+
+/* { dg-final { scan-assembler-times "test04:.*\tmovz\t\\\$.,\\\$0.*test04\n" 1 } } */
+int
+test04 (int a, int b, int c)
+{
+  return a ? b : 0;
+}
+
+/* Test MOVTN.  */
+
+/* { dg-final { scan-assembler-times "test05:.*\tmovtn\t.*test05\n" 1 } } */
+int
+test05 (int a, int b, int c, int d)
+{
+  return a >= b ? c : d;
+}
+
+/* { dg-final { scan-assembler-times "test06:.*\tmovtn\t\\\$2,\\\$0.*test06\n" 1 } } */
+int
+test06 (int a, int b, int c, int d)
+{
+  return a >= b ? c : 0;
+}
+
+/* Test MOVTZ.  */
+
+/* { dg-final { scan-assembler-times "test07:.*\tmovtz\t.*test07\n" 1 } } */
+int
+test07 (int a, int b, int c, int d)
+{
+  return a < b ? c : d;
+}
+
+/* { dg-final { scan-assembler-times "test08:.*\tmovtz\t\\\$.,\\\$0.*test08\n" 1 } } */
+int
+test08 (int a, int b, int c, int d)
+{
+  return a < b ? c : 0;
+}
+
+