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[23.233.12.249]) by smtp.gmail.com with ESMTPSA id ph4-20020a0562144a4400b006815ec86ab3sm920678qvb.46.2024.01.15.07.26.48 for (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 15 Jan 2024 07:26:49 -0800 (PST) Message-ID: <2719a083-baca-3671-7a49-e7796d68adfb@redhat.com> Date: Mon, 15 Jan 2024 10:26:48 -0500 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.15.1 To: "gcc-patches@gcc.gnu.org" From: Vladimir Makarov Subject: [pushed][PR113354][LRA]: Fixing LRA failure on building MIPS GCC X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Language: en-US X-Spam-Status: No, score=-11.6 required=5.0 tests=BAYES_00, DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, KAM_SHORT, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H4, RCVD_IN_MSPIKE_WL, RCVD_IN_SORBS_WEB, SPF_HELO_NONE, SPF_NONE, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1788170687105303059 X-GMAIL-MSGID: 1788170687105303059 The following patch fixes https://gcc.gnu.org/bugzilla/show_bug.cgi?id=113354 The patch was tested on building MIPS target. The patch was successfully tested and bootstrapped on x86-64, ppc64le, aarch64. commit 5f662bce28618ea5417f68a17d5c2d34b052ecb2 Author: Vladimir N. Makarov Date: Mon Jan 15 10:19:39 2024 -0500 [PR113354][LRA]: Fixing LRA failure on building MIPS GCC My recent patch for PR112918 triggered a hidden bug in LRA on MIPS. A pseudo is matched to a register constraint and assigned to a hard registers at the first constraint sub-pass but later it is matched to X constraint. Keeping this pseudo in the register (MD0) prevents to use the same register for another pseudo in the insn and this results in LRA failure. The patch fixes this by spilling the pseudo at the constraint subpass when the chosen alternative constraint not require hard register anymore. gcc/ChangeLog: PR middle-end/113354 * lra-constraints.cc (curr_insn_transform): Spill pseudo only used in the insn if the corresponding operand does not require hard register anymore. diff --git a/gcc/lra-constraints.cc b/gcc/lra-constraints.cc index dc41bc3d6c6..3379b88ff22 100644 --- a/gcc/lra-constraints.cc +++ b/gcc/lra-constraints.cc @@ -4491,23 +4491,18 @@ curr_insn_transform (bool check_only_p) { if (goal_alt[i] == NO_REGS && REG_P (op) - /* When we assign NO_REGS it means that we will not - assign a hard register to the scratch pseudo by - assigment pass and the scratch pseudo will be - spilled. Spilled scratch pseudos are transformed - back to scratches at the LRA end. */ - && ira_former_scratch_operand_p (curr_insn, i) - && ira_former_scratch_p (REGNO (op))) + && (regno = REGNO (op)) >= FIRST_PSEUDO_REGISTER + /* We assigned a hard register to the pseudo in the past but now + decided to spill it for the insn. If the pseudo is used only + in this insn, it is better to spill it here as we free hard + registers for other pseudos referenced in the insn. The most + common case of this is a scratch register which will be + transformed to scratch back at the end of LRA. */ + && lra_get_regno_hard_regno (regno) >= 0 + && bitmap_single_bit_set_p (&lra_reg_info[regno].insn_bitmap)) { - int regno = REGNO (op); lra_change_class (regno, NO_REGS, " Change to", true); - if (lra_get_regno_hard_regno (regno) >= 0) - /* We don't have to mark all insn affected by the - spilled pseudo as there is only one such insn, the - current one. */ - reg_renumber[regno] = -1; - lra_assert (bitmap_single_bit_set_p - (&lra_reg_info[REGNO (op)].insn_bitmap)); + reg_renumber[regno] = -1; } /* We can do an optional reload. If the pseudo got a hard reg, we might improve the code through inheritance. If