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bh=jqTNcyvgmQmHXskIiCAZrL4dFNCzkKfBmfsYs53YXUw=; b=aEK7041tf0bxqk9eXth6Hhsa+zjp4DWzF1+esjfN6EDp4/F69/ntJZcyS4KrwMsw3P 19SvpKQ5l5Z+mM11iSwBoXZMym/Fe3sMyKeNX3EbtP2IljCt8TySFDLgoKDnMicehj70 fVArqvgPxlU5BMSSbZl1JINWnZmR5W1U5jWtXZTm/9gyKASsDJjvZgDwcziOoB0YLacY roKDeOD0S8GnsFlKpXHL/k1137ta44b/p+lCQEIfh/Dg+LndmLixeiWX8yYjAH2ThEA1 gy7oUoXbTuF6vGUGSMzDorVkUPLAjJwmHpsUMvKmsYlIwAGzZP1CR9lyuEoUr7Sq1ec6 25tg== X-Gm-Message-State: AOJu0YxexfPrhEWRLCTNa9nRCc5lYAj6TcmuOvGUI1/4en/YBomB29bi S2VLke6gEi8jHGCWjyZY2d5wcGSl7DJVX5LYcNAWMfT/CXVyiKDQkBBp06a2pFxD25gR13PF8nb q X-Received: by 2002:a17:902:ea0e:b0:1d9:e181:51b0 with SMTP id s14-20020a170902ea0e00b001d9e18151b0mr438122plg.23.1707959490931; Wed, 14 Feb 2024 17:11:30 -0800 (PST) Received: from ewlu.ba.rivosinc.com ([64.71.180.162]) by smtp.gmail.com with ESMTPSA id 21-20020a170902c25500b001d8f12b0009sm60611plg.293.2024.02.14.17.11.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 14 Feb 2024 17:11:30 -0800 (PST) From: Edwin Lu To: gcc-patches@gcc.gnu.org Cc: gnu-toolchain@rivosinc.com, Edwin Lu Subject: [PATCH V4 3/5] RISC-V: Use default cost model for insn scheduling Date: Wed, 14 Feb 2024 17:11:19 -0800 Message-Id: <20240215011121.2434218-4-ewlu@rivosinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240215011121.2434218-1-ewlu@rivosinc.com> References: <20240215011121.2434218-1-ewlu@rivosinc.com> MIME-Version: 1.0 X-Spam-Status: No, score=-11.9 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, GIT_PATCH_0, KAM_SHORT, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1790925449360065776 X-GMAIL-MSGID: 1790925449360065776 Use default cost model scheduling on these test cases. All these tests introduce scan dump failures with -mtune generic-ooo. Since the vector cost models are the same across all three tunes, some of the tests in PR113249 will be fixed with this patch series. PR target/113249 gcc/testsuite/ChangeLog: * g++.target/riscv/rvv/base/bug-1.C: use default scheduling * gcc.target/riscv/rvv/autovec/reduc/reduc_call-2.c: ditto * gcc.target/riscv/rvv/base/binop_vx_constraint-102.c: ditto * gcc.target/riscv/rvv/base/binop_vx_constraint-108.c: ditto * gcc.target/riscv/rvv/base/binop_vx_constraint-114.c: ditto * gcc.target/riscv/rvv/base/binop_vx_constraint-119.c: ditto * gcc.target/riscv/rvv/base/binop_vx_constraint-12.c: ditto * gcc.target/riscv/rvv/base/binop_vx_constraint-16.c: ditto * gcc.target/riscv/rvv/base/binop_vx_constraint-17.c: ditto * gcc.target/riscv/rvv/base/binop_vx_constraint-19.c: ditto * gcc.target/riscv/rvv/base/binop_vx_constraint-21.c: ditto * gcc.target/riscv/rvv/base/binop_vx_constraint-23.c: ditto * gcc.target/riscv/rvv/base/binop_vx_constraint-25.c: ditto * gcc.target/riscv/rvv/base/binop_vx_constraint-27.c: ditto * gcc.target/riscv/rvv/base/binop_vx_constraint-29.c: ditto * gcc.target/riscv/rvv/base/binop_vx_constraint-31.c: ditto * gcc.target/riscv/rvv/base/binop_vx_constraint-33.c: ditto * gcc.target/riscv/rvv/base/binop_vx_constraint-35.c: ditto * gcc.target/riscv/rvv/base/binop_vx_constraint-4.c: ditto * gcc.target/riscv/rvv/base/binop_vx_constraint-40.c: ditto * gcc.target/riscv/rvv/base/binop_vx_constraint-44.c: ditto * gcc.target/riscv/rvv/base/binop_vx_constraint-50.c: ditto * gcc.target/riscv/rvv/base/binop_vx_constraint-56.c: ditto * gcc.target/riscv/rvv/base/binop_vx_constraint-62.c: ditto * gcc.target/riscv/rvv/base/binop_vx_constraint-68.c: ditto * gcc.target/riscv/rvv/base/binop_vx_constraint-74.c: ditto * gcc.target/riscv/rvv/base/binop_vx_constraint-79.c: ditto * gcc.target/riscv/rvv/base/binop_vx_constraint-8.c: ditto * gcc.target/riscv/rvv/base/binop_vx_constraint-84.c: ditto * gcc.target/riscv/rvv/base/binop_vx_constraint-90.c: ditto * gcc.target/riscv/rvv/base/binop_vx_constraint-96.c: ditto * gcc.target/riscv/rvv/base/float-point-dynamic-frm-30.c: ditto * gcc.target/riscv/rvv/base/pr108185-1.c: ditto * gcc.target/riscv/rvv/base/pr108185-2.c: ditto * gcc.target/riscv/rvv/base/pr108185-3.c: ditto * gcc.target/riscv/rvv/base/pr108185-4.c: ditto * gcc.target/riscv/rvv/base/pr108185-5.c: ditto * gcc.target/riscv/rvv/base/pr108185-6.c: ditto * gcc.target/riscv/rvv/base/pr108185-7.c: ditto * gcc.target/riscv/rvv/base/shift_vx_constraint-1.c: ditto * gcc.target/riscv/rvv/vsetvl/pr111037-3.c: ditto * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-28.c: ditto * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-29.c: ditto * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-32.c: ditto * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-33.c: ditto * gcc.target/riscv/rvv/vsetvl/vlmax_single_block-17.c: ditto * gcc.target/riscv/rvv/vsetvl/vlmax_single_block-18.c: ditto * gcc.target/riscv/rvv/vsetvl/vlmax_single_block-19.c: ditto * gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-10.c: ditto * gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-11.c: ditto * gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-12.c: ditto * gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-4.c: ditto * gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-5.c: ditto * gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-6.c: ditto * gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-7.c: ditto * gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-8.c: ditto * gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-9.c: ditto * gfortran.dg/vect/vect-8.f90: ditto Signed-off-by: Edwin Lu --- V2: - New patch V3/V4: - No change --- gcc/testsuite/g++.target/riscv/rvv/base/bug-1.C | 2 ++ gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_call-2.c | 2 ++ .../gcc.target/riscv/rvv/base/binop_vx_constraint-102.c | 2 ++ .../gcc.target/riscv/rvv/base/binop_vx_constraint-108.c | 2 ++ .../gcc.target/riscv/rvv/base/binop_vx_constraint-114.c | 2 ++ .../gcc.target/riscv/rvv/base/binop_vx_constraint-119.c | 2 ++ .../gcc.target/riscv/rvv/base/binop_vx_constraint-12.c | 2 ++ .../gcc.target/riscv/rvv/base/binop_vx_constraint-16.c | 2 ++ .../gcc.target/riscv/rvv/base/binop_vx_constraint-17.c | 2 ++ .../gcc.target/riscv/rvv/base/binop_vx_constraint-19.c | 2 ++ .../gcc.target/riscv/rvv/base/binop_vx_constraint-21.c | 2 ++ .../gcc.target/riscv/rvv/base/binop_vx_constraint-23.c | 2 ++ .../gcc.target/riscv/rvv/base/binop_vx_constraint-25.c | 2 ++ .../gcc.target/riscv/rvv/base/binop_vx_constraint-27.c | 2 ++ .../gcc.target/riscv/rvv/base/binop_vx_constraint-29.c | 2 ++ .../gcc.target/riscv/rvv/base/binop_vx_constraint-31.c | 2 ++ .../gcc.target/riscv/rvv/base/binop_vx_constraint-33.c | 2 ++ .../gcc.target/riscv/rvv/base/binop_vx_constraint-35.c | 2 ++ gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-4.c | 2 ++ .../gcc.target/riscv/rvv/base/binop_vx_constraint-40.c | 2 ++ .../gcc.target/riscv/rvv/base/binop_vx_constraint-44.c | 2 ++ .../gcc.target/riscv/rvv/base/binop_vx_constraint-50.c | 2 ++ .../gcc.target/riscv/rvv/base/binop_vx_constraint-56.c | 2 ++ .../gcc.target/riscv/rvv/base/binop_vx_constraint-62.c | 2 ++ .../gcc.target/riscv/rvv/base/binop_vx_constraint-68.c | 2 ++ .../gcc.target/riscv/rvv/base/binop_vx_constraint-74.c | 2 ++ .../gcc.target/riscv/rvv/base/binop_vx_constraint-79.c | 2 ++ gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-8.c | 2 ++ .../gcc.target/riscv/rvv/base/binop_vx_constraint-84.c | 2 ++ .../gcc.target/riscv/rvv/base/binop_vx_constraint-90.c | 2 ++ .../gcc.target/riscv/rvv/base/binop_vx_constraint-96.c | 2 ++ .../gcc.target/riscv/rvv/base/float-point-dynamic-frm-30.c | 2 ++ gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-1.c | 2 ++ gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-2.c | 2 ++ gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-3.c | 2 ++ gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-4.c | 2 ++ gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-5.c | 2 ++ gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-6.c | 2 ++ gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-7.c | 2 ++ gcc/testsuite/gcc.target/riscv/rvv/base/shift_vx_constraint-1.c | 2 ++ gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr111037-3.c | 2 ++ gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-28.c | 2 ++ gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-29.c | 2 ++ gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-32.c | 2 ++ gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-33.c | 2 ++ .../gcc.target/riscv/rvv/vsetvl/vlmax_single_block-17.c | 2 ++ .../gcc.target/riscv/rvv/vsetvl/vlmax_single_block-18.c | 2 ++ .../gcc.target/riscv/rvv/vsetvl/vlmax_single_block-19.c | 2 ++ .../gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-10.c | 2 ++ .../gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-11.c | 2 ++ .../gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-12.c | 2 ++ .../gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-4.c | 2 ++ .../gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-5.c | 2 ++ .../gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-6.c | 2 ++ .../gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-7.c | 2 ++ .../gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-8.c | 2 ++ .../gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-9.c | 2 ++ gcc/testsuite/gfortran.dg/vect/vect-8.f90 | 2 ++ 58 files changed, 116 insertions(+) diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/bug-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/bug-1.C index c1070f9eb16..6f62a64224d 100644 --- a/gcc/testsuite/g++.target/riscv/rvv/base/bug-1.C +++ b/gcc/testsuite/g++.target/riscv/rvv/base/bug-1.C @@ -1,5 +1,7 @@ /* { dg-do compile } */ /* { dg-options "-march=rv32gcv -mabi=ilp32d -O3" } */ +// PR113249 +/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */ #include "riscv_vector.h" template < class T > diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_call-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_call-2.c index 7be22d60bf2..17a6b6f27fd 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_call-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_call-2.c @@ -1,5 +1,7 @@ /* { dg-do compile } */ /* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */ +// PR113249 +/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */ #include "reduc_call-1.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-102.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-102.c index 4b24b971cba..8386b42e9b5 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-102.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-102.c @@ -1,5 +1,7 @@ /* { dg-do compile } */ /* { dg-options "-march=rv32gcv -mabi=ilp32 -O3" } */ +// PR113249 +/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */ #include "riscv_vector.h" void f (void * in, void *out, int32_t x, int n) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-108.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-108.c index 99acc51b4ff..e2ed4b76a16 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-108.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-108.c @@ -1,5 +1,7 @@ /* { dg-do compile } */ /* { dg-options "-march=rv32gcv -mabi=ilp32 -O3" } */ +// PR113249 +/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */ #include "riscv_vector.h" void f (void * in, void *out, int32_t x, int n) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-114.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-114.c index d595c446503..61340be8362 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-114.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-114.c @@ -1,5 +1,7 @@ /* { dg-do compile } */ /* { dg-options "-march=rv32gcv -mabi=ilp32 -O3" } */ +// PR113249 +/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */ #include "riscv_vector.h" void f (void * in, void *out, int32_t x, int n) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-119.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-119.c index 0b51175f66c..0f1485e3c0a 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-119.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-119.c @@ -1,5 +1,7 @@ /* { dg-do compile } */ /* { dg-options "-march=rv32gcv -mabi=ilp32 -O3" } */ +// PR113249 +/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */ #include "riscv_vector.h" void f (void * in, void *out, uint64_t x, int n) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-12.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-12.c index 634c12a4c0e..173ac625ada 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-12.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-12.c @@ -1,5 +1,7 @@ /* { dg-do compile } */ /* { dg-options "-march=rv32gcv -mabi=ilp32d -O3" } */ +// PR113249 +/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */ /* { dg-final { check-function-bodies "**" "" } } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-16.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-16.c index 651d61001c1..1edba8980b4 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-16.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-16.c @@ -1,5 +1,7 @@ /* { dg-do compile } */ /* { dg-options "-march=rv32gcv -mabi=ilp32d -O3" } */ +// PR113249 +/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */ /* { dg-final { check-function-bodies "**" "" } } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-17.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-17.c index d19a9fda235..75340c3da6c 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-17.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-17.c @@ -1,5 +1,7 @@ /* { dg-do compile } */ /* { dg-options "-march=rv32gcv -mabi=ilp32d -O3" } */ +// PR113249 +/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */ /* { dg-final { check-function-bodies "**" "" } } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-19.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-19.c index 16f431542d8..7e4aedc1cdc 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-19.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-19.c @@ -1,5 +1,7 @@ /* { dg-do compile } */ /* { dg-options "-march=rv32gcv -mabi=ilp32d -O3" } */ +// PR113249 +/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */ /* { dg-final { check-function-bodies "**" "" } } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-21.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-21.c index 347c846dcbb..755e92a9cd7 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-21.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-21.c @@ -1,5 +1,7 @@ /* { dg-do compile } */ /* { dg-options "-march=rv32gcv -mabi=ilp32d -O3" } */ +// PR113249 +/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */ /* { dg-final { check-function-bodies "**" "" } } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-23.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-23.c index bc414440ba2..2c82dc0688a 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-23.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-23.c @@ -1,5 +1,7 @@ /* { dg-do compile } */ /* { dg-options "-march=rv32gcv -mabi=ilp32d -O3" } */ +// PR113249 +/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */ /* { dg-final { check-function-bodies "**" "" } } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-25.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-25.c index ce3f3af9c3d..e2ac6a3d9e1 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-25.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-25.c @@ -1,5 +1,7 @@ /* { dg-do compile } */ /* { dg-options "-march=rv32gcv -mabi=ilp32d -O3" } */ +// PR113249 +/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */ /* { dg-final { check-function-bodies "**" "" } } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-27.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-27.c index 4946f84b916..436a0e85f3d 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-27.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-27.c @@ -1,5 +1,7 @@ /* { dg-do compile } */ /* { dg-options "-march=rv32gcv -mabi=ilp32d -O3" } */ +// PR113249 +/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */ /* { dg-final { check-function-bodies "**" "" } } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-29.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-29.c index 5f2eede0422..72b321607c3 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-29.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-29.c @@ -1,5 +1,7 @@ /* { dg-do compile } */ /* { dg-options "-march=rv32gcv -mabi=ilp32d -O3" } */ +// PR113249 +/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */ /* { dg-final { check-function-bodies "**" "" } } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-31.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-31.c index 5f2eede0422..72b321607c3 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-31.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-31.c @@ -1,5 +1,7 @@ /* { dg-do compile } */ /* { dg-options "-march=rv32gcv -mabi=ilp32d -O3" } */ +// PR113249 +/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */ /* { dg-final { check-function-bodies "**" "" } } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-33.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-33.c index 88fcba60345..6908c78e19b 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-33.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-33.c @@ -1,5 +1,7 @@ /* { dg-do compile } */ /* { dg-options "-march=rv32gcv -mabi=ilp32d -O3" } */ +// PR113249 +/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */ /* { dg-final { check-function-bodies "**" "" } } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-35.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-35.c index 88fcba60345..6908c78e19b 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-35.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-35.c @@ -1,5 +1,7 @@ /* { dg-do compile } */ /* { dg-options "-march=rv32gcv -mabi=ilp32d -O3" } */ +// PR113249 +/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */ /* { dg-final { check-function-bodies "**" "" } } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-4.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-4.c index 87a16453fea..ee1db1c41ae 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-4.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-4.c @@ -1,5 +1,7 @@ /* { dg-do compile } */ /* { dg-options "-march=rv32gcv -mabi=ilp32d -O3" } */ +// PR113249 +/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */ /* { dg-final { check-function-bodies "**" "" } } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-40.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-40.c index c0321cefb9a..fb969eb50a2 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-40.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-40.c @@ -1,5 +1,7 @@ /* { dg-do compile } */ /* { dg-options "-march=rv32gcv -mabi=ilp32d -O3" } */ +// PR113249 +/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */ /* { dg-final { check-function-bodies "**" "" } } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-44.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-44.c index ab0f13ba255..542f43eca49 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-44.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-44.c @@ -1,5 +1,7 @@ /* { dg-do compile } */ /* { dg-options "-march=rv32gcv -mabi=ilp32d -O3" } */ +// PR113249 +/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */ /* { dg-final { check-function-bodies "**" "" } } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-50.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-50.c index 3893e17511d..31109a81ec3 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-50.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-50.c @@ -1,5 +1,7 @@ /* { dg-do compile } */ /* { dg-options "-march=rv32gcv -mabi=ilp32 -O3" } */ +// PR113249 +/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */ #include "riscv_vector.h" void f (void * in, void *out, int32_t x, int n) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-56.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-56.c index b0ea553bf89..924f4507ba3 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-56.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-56.c @@ -1,5 +1,7 @@ /* { dg-do compile } */ /* { dg-options "-march=rv32gcv -mabi=ilp32 -O3" } */ +// PR113249 +/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */ #include "riscv_vector.h" void f (void * in, void *out, int64_t x, int n) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-62.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-62.c index 350697d764d..659d8d9e702 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-62.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-62.c @@ -1,5 +1,7 @@ /* { dg-do compile } */ /* { dg-options "-march=rv32gcv -mabi=ilp32 -O3" } */ +// PR113249 +/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */ #include "riscv_vector.h" void f (void * in, void *out, int64_t x, int n) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-68.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-68.c index 0f138c5d3c6..63874605759 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-68.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-68.c @@ -1,5 +1,7 @@ /* { dg-do compile } */ /* { dg-options "-march=rv32gcv -mabi=ilp32 -O3" } */ +// PR113249 +/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */ #include "riscv_vector.h" void f (void * in, void *out, int64_t x, int n) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-74.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-74.c index f4cbf095357..a214d70cb2c 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-74.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-74.c @@ -1,5 +1,7 @@ /* { dg-do compile } */ /* { dg-options "-march=rv32gcv -mabi=ilp32 -O3" } */ +// PR113249 +/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */ #include "riscv_vector.h" void f (void * in, void *out, int64_t x, int n) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-79.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-79.c index d606078e85f..efa659b2752 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-79.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-79.c @@ -1,5 +1,7 @@ /* { dg-do compile } */ /* { dg-options "-march=rv32gcv -mabi=ilp32 -O3" } */ +// PR113249 +/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */ #include "riscv_vector.h" void f (void * in, void *out, int64_t x, int n) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-8.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-8.c index 9bf9ff59de7..6a26248096d 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-8.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-8.c @@ -1,5 +1,7 @@ /* { dg-do compile } */ /* { dg-options "-march=rv32gcv -mabi=ilp32d -O3" } */ +// PR113249 +/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */ /* { dg-final { check-function-bodies "**" "" } } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-84.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-84.c index bca55b239f9..429fe129003 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-84.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-84.c @@ -1,5 +1,7 @@ /* { dg-do compile } */ /* { dg-options "-march=rv32gcv -mabi=ilp32 -O3" } */ +// PR113249 +/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */ #include "riscv_vector.h" void f (void * in, void *out, uint64_t x, int n) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-90.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-90.c index 586e26499db..0cd0af76186 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-90.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-90.c @@ -1,5 +1,7 @@ /* { dg-do compile } */ /* { dg-options "-march=rv32gcv -mabi=ilp32 -O3" } */ +// PR113249 +/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */ #include "riscv_vector.h" void f (void * in, void *out, int32_t x, int n) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-96.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-96.c index d1bbb78f5ed..bb1690e81e4 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-96.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-96.c @@ -1,5 +1,7 @@ /* { dg-do compile } */ /* { dg-options "-march=rv32gcv -mabi=ilp32 -O3" } */ +// PR113249 +/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */ #include "riscv_vector.h" void f (void * in, void *out, int32_t x, int n) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-30.c b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-30.c index 7e738783974..37ef0f05423 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-30.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-30.c @@ -1,5 +1,7 @@ /* { dg-do compile } */ /* { dg-options "-march=rv64gcv -mabi=lp64 -O3" } */ +// PR113249 +/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-1.c index c3d0b10271a..4c6e88e7eed 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-1.c @@ -1,5 +1,7 @@ /* { dg-do compile } */ /* { dg-options "-march=rv64gcv -mabi=lp64 -O3" } */ +// PR113249 +/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-2.c index bd13ba916da..0844e3e8713 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-2.c @@ -1,5 +1,7 @@ /* { dg-do compile } */ /* { dg-options "-march=rv64gcv -mabi=lp64 -O3" } */ +// PR113249 +/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-3.c index 99928f7b1cc..49a574485fe 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-3.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-3.c @@ -1,5 +1,7 @@ /* { dg-do compile } */ /* { dg-options "-march=rv64gcv -mabi=lp64 -O3" } */ +// PR113249 +/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-4.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-4.c index 321cd5c818e..cef0a11b2d4 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-4.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-4.c @@ -1,5 +1,7 @@ /* { dg-do compile } */ /* { dg-options "-march=rv64gc_zve64d -mabi=lp64 -O3" } */ +// PR113249 +/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-5.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-5.c index 575a7842cdf..3f0d67726bc 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-5.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-5.c @@ -1,5 +1,7 @@ /* { dg-do compile } */ /* { dg-options "-march=rv64gcv -mabi=lp64 -O3" } */ +// PR113249 +/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-6.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-6.c index 95a11d37016..4ed658899f4 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-6.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-6.c @@ -1,5 +1,7 @@ /* { dg-do compile } */ /* { dg-options "-march=rv64gcv -mabi=lp64 -O3" } */ +// PR113249 +/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-7.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-7.c index 8f6f0b11f09..95b7ff97666 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-7.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-7.c @@ -1,5 +1,7 @@ /* { dg-do compile } */ /* { dg-options "-march=rv64gcv -mabi=lp64 -O3" } */ +// PR113249 +/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/shift_vx_constraint-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/shift_vx_constraint-1.c index 250e017cc86..9e0b41ccba7 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/shift_vx_constraint-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/shift_vx_constraint-1.c @@ -1,5 +1,7 @@ /* { dg-do compile } */ /* { dg-options "-march=rv32gcv -mabi=ilp32d -O3" } */ +// PR113249 +/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */ /* { dg-final { check-function-bodies "**" "" } } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr111037-3.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr111037-3.c index 110e55b3cbe..5e1859cd13b 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr111037-3.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr111037-3.c @@ -1,5 +1,7 @@ /* { dg-do compile } */ /* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gc_zve64f_zvfh -mabi=ilp32d -O3" } */ +// PR113249 +/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-28.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-28.c index 4583504bd5a..f4f0e52971a 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-28.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-28.c @@ -1,5 +1,7 @@ /* { dg-do compile } */ /* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */ +// PR113249 +/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-29.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-29.c index f16f4b9c37d..7e01b81682b 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-29.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-29.c @@ -1,5 +1,7 @@ /* { dg-do compile } */ /* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */ +// PR113249 +/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-32.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-32.c index 43b443be6cb..5615cb1f97f 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-32.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-32.c @@ -1,5 +1,7 @@ /* { dg-do compile } */ /* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */ +// PR113249 +/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-33.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-33.c index 67855581fb2..c906b153ab8 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-33.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-33.c @@ -1,5 +1,7 @@ /* { dg-do compile } */ /* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */ +// PR113249 +/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-17.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-17.c index 960c9bff765..006df7edf8d 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-17.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-17.c @@ -1,5 +1,7 @@ /* { dg-do compile } */ /* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */ +// PR113249 +/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-18.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-18.c index 5f22e8d0e8e..cc6d8221516 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-18.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-18.c @@ -1,5 +1,7 @@ /* { dg-do compile } */ /* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */ +// PR113249 +/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-19.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-19.c index e5f35c0f018..9704e444d54 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-19.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-19.c @@ -1,5 +1,7 @@ /* { dg-do compile } */ /* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */ +// PR113249 +/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-10.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-10.c index 0532c7d4207..476735dcb2e 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-10.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-10.c @@ -1,5 +1,7 @@ /* { dg-do compile } */ /* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */ +// PR113249 +/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-11.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-11.c index b664c4b67eb..c7b7db33849 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-11.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-11.c @@ -1,5 +1,7 @@ /* { dg-do compile } */ /* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */ +// PR113249 +/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-12.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-12.c index 04c4b886eec..80ff75f6d2a 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-12.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-12.c @@ -1,5 +1,7 @@ /* { dg-do compile } */ /* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */ +// PR113249 +/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-4.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-4.c index 1404c9dc0d5..127dc7ff06d 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-4.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-4.c @@ -1,5 +1,7 @@ /* { dg-do compile } */ /* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */ +// PR113249 +/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-5.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-5.c index 1404c9dc0d5..127dc7ff06d 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-5.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-5.c @@ -1,5 +1,7 @@ /* { dg-do compile } */ /* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */ +// PR113249 +/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-6.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-6.c index 609c68dfcbe..e19e869e241 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-6.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-6.c @@ -1,5 +1,7 @@ /* { dg-do compile } */ /* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */ +// PR113249 +/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-7.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-7.c index 043f17737ae..90eca5b1ae6 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-7.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-7.c @@ -1,5 +1,7 @@ /* { dg-do compile } */ /* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */ +// PR113249 +/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-8.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-8.c index 0bedde84005..17b217bc82c 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-8.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-8.c @@ -1,5 +1,7 @@ /* { dg-do compile } */ /* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */ +// PR113249 +/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-9.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-9.c index 0bedde84005..17b217bc82c 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-9.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-9.c @@ -1,5 +1,7 @@ /* { dg-do compile } */ /* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */ +// PR113249 +/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gfortran.dg/vect/vect-8.f90 b/gcc/testsuite/gfortran.dg/vect/vect-8.f90 index 938dfc29754..f77ec9fb87a 100644 --- a/gcc/testsuite/gfortran.dg/vect/vect-8.f90 +++ b/gcc/testsuite/gfortran.dg/vect/vect-8.f90 @@ -1,6 +1,8 @@ ! { dg-do compile } ! { dg-require-effective-target vect_double } ! { dg-additional-options "-fno-tree-loop-distribute-patterns -finline-matmul-limit=0" } +! PR113249 +! { dg-options "-fno-schedule-insns -fno-schedule-insns2" { target { riscv*-*-* } } } module lfk_prec integer, parameter :: dp=kind(1.d0)