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bh=db3USYvjRD9ek6aK2OHKDpq3rp+Mz/tMJiruY1qhdlc=; b=g03I5DCmLPZn7NXFBZTe22GgLU5N0TYzpEtrX/V+LgUamYuRYmHrpx+7TKbN7b48ja q3TZHF54tcaCOPVhZ6l/UlP6mY/Rl4NLzynQKFAjaBKbsRFYHJWybfgcezVp5mVO7t84 EESvm9fF1elz70XhYS/DVtsNa+clGbZe1IcFXsi28O3QNhGchoPNu1my8NPQLDhxqLuS r9EoqkXoLW+cArxI3mV1D0tE11Ss8UgcDWfdc6C2LeRKqhh1xy0EPpWG0UgxbZJlhnfd 6Gr6TNP5JXAWf7+wsiKFVuheFfL7eDonaxOikUoUEzKYe+q8wfc5K0Ik1YgRydsOdDin sbvA== X-Gm-Message-State: AOJu0Yx5E37g6oriJBYaPlBm+dwZ6w24uZqhJKsOBkYNLBebz/2IqsPW Spc9fQpBwSEk4KkS0JOTsWAuZlV9e2b9c+mNXgl9lBCwMyk1bZietTQHrPkIswTEq79y08p3/AN q X-Received: by 2002:a17:903:48a:b0:1da:2216:f1f8 with SMTP id jj10-20020a170903048a00b001da2216f1f8mr306047plb.39.1707959486717; Wed, 14 Feb 2024 17:11:26 -0800 (PST) Received: from ewlu.ba.rivosinc.com ([64.71.180.162]) by smtp.gmail.com with ESMTPSA id 21-20020a170902c25500b001d8f12b0009sm60611plg.293.2024.02.14.17.11.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 14 Feb 2024 17:11:26 -0800 (PST) From: Edwin Lu To: gcc-patches@gcc.gnu.org Cc: gnu-toolchain@rivosinc.com, Edwin Lu Subject: [PATCH V4 1/5] RISC-V: Add non-vector types to dfa pipelines Date: Wed, 14 Feb 2024 17:11:17 -0800 Message-Id: <20240215011121.2434218-2-ewlu@rivosinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240215011121.2434218-1-ewlu@rivosinc.com> References: <20240215011121.2434218-1-ewlu@rivosinc.com> MIME-Version: 1.0 X-Spam-Status: No, score=-11.8 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, GIT_PATCH_0, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1790925384061393176 X-GMAIL-MSGID: 1790925384061393176 This patch adds non-vector related insn reservations and updates/creates new insn reservations so all non-vector typed instructions have a reservation. gcc/ChangeLog: * config/riscv/generic-ooo.md (generic_ooo_sfb_alu): Add reservation (generic_ooo_branch): ditto * config/riscv/generic.md (generic_sfb_alu): ditto (generic_fmul_half): ditto * config/riscv/riscv.md: Remove cbo, pushpop, and rdfrm types * config/riscv/sifive-7.md (sifive_7_hfma): Add reservation (sifive_7_popcount): ditto * config/riscv/sifive-p400.md (sifive_p400_clmul): ditto * config/riscv/sifive-p600.md (sifive_p600_clmul): ditto * config/riscv/vector.md: change rdfrm to fmove * config/riscv/zc.md: change pushpop to load/store Signed-off-by: Edwin Lu --- V2: - Add insn reservations for HF fmul - Remove/adjust insn types V3: - No changes V4: - Update sifive-p400 and sifive-p600 series --- gcc/config/riscv/generic-ooo.md | 15 +++++- gcc/config/riscv/generic.md | 20 +++++-- gcc/config/riscv/riscv.md | 16 +++--- gcc/config/riscv/sifive-7.md | 17 +++++- gcc/config/riscv/sifive-p400.md | 10 +++- gcc/config/riscv/sifive-p600.md | 10 +++- gcc/config/riscv/vector.md | 2 +- gcc/config/riscv/zc.md | 96 ++++++++++++++++----------------- 8 files changed, 117 insertions(+), 69 deletions(-) diff --git a/gcc/config/riscv/generic-ooo.md b/gcc/config/riscv/generic-ooo.md index a22f8a3e079..83cd06234b3 100644 --- a/gcc/config/riscv/generic-ooo.md +++ b/gcc/config/riscv/generic-ooo.md @@ -115,9 +115,20 @@ (define_insn_reservation "generic_ooo_vec_loadstore_seg" 10 (define_insn_reservation "generic_ooo_alu" 1 (and (eq_attr "tune" "generic_ooo") (eq_attr "type" "unknown,const,arith,shift,slt,multi,auipc,nop,logical,\ - move,bitmanip,min,max,minu,maxu,clz,ctz")) + move,bitmanip,rotate,min,max,minu,maxu,clz,ctz,atomic,\ + condmove,mvpair,zicond")) "generic_ooo_issue,generic_ooo_ixu_alu") +(define_insn_reservation "generic_ooo_sfb_alu" 2 + (and (eq_attr "tune" "generic_ooo") + (eq_attr "type" "sfb_alu")) + "generic_ooo_issue,generic_ooo_ixu_alu") + +;; Branch instructions +(define_insn_reservation "generic_ooo_branch" 1 + (and (eq_attr "tune" "generic_ooo") + (eq_attr "type" "branch,jump,call,jalr,ret,trap")) + "generic_ooo_issue,generic_ooo_ixu_alu") ;; Float move, convert and compare. (define_insn_reservation "generic_ooo_float_move" 3 @@ -184,7 +195,7 @@ (define_insn_reservation "generic_ooo_popcount" 2 (define_insn_reservation "generic_ooo_vec_alu" 3 (and (eq_attr "tune" "generic_ooo") (eq_attr "type" "vialu,viwalu,vext,vicalu,vshift,vnshift,viminmax,vicmp,\ - vimov,vsalu,vaalu,vsshift,vnclip,vmov,vfmov")) + vimov,vsalu,vaalu,vsshift,vnclip,vmov,vfmov,vector")) "generic_ooo_vxu_issue,generic_ooo_vxu_alu") ;; Vector float comparison, conversion etc. diff --git a/gcc/config/riscv/generic.md b/gcc/config/riscv/generic.md index 3f0eaa2ea08..4f6e63bff57 100644 --- a/gcc/config/riscv/generic.md +++ b/gcc/config/riscv/generic.md @@ -27,7 +27,9 @@ (define_cpu_unit "fdivsqrt" "pipe0") (define_insn_reservation "generic_alu" 1 (and (eq_attr "tune" "generic") - (eq_attr "type" "unknown,const,arith,shift,slt,multi,auipc,nop,logical,move,bitmanip,min,max,minu,maxu,clz,ctz,cpop")) + (eq_attr "type" "unknown,const,arith,shift,slt,multi,auipc,nop,logical,\ + move,bitmanip,min,max,minu,maxu,clz,ctz,rotate,atomic,\ + condmove,crypto,mvpair,zicond")) "alu") (define_insn_reservation "generic_load" 3 @@ -47,12 +49,17 @@ (define_insn_reservation "generic_xfer" 3 (define_insn_reservation "generic_branch" 1 (and (eq_attr "tune" "generic") - (eq_attr "type" "branch,jump,call,jalr")) + (eq_attr "type" "branch,jump,call,jalr,ret,trap")) + "alu") + +(define_insn_reservation "generic_sfb_alu" 2 + (and (eq_attr "tune" "generic") + (eq_attr "type" "sfb_alu")) "alu") (define_insn_reservation "generic_imul" 10 (and (eq_attr "tune" "generic") - (eq_attr "type" "imul,clmul")) + (eq_attr "type" "imul,clmul,cpop")) "imuldiv*10") (define_insn_reservation "generic_idivsi" 34 @@ -67,6 +74,12 @@ (define_insn_reservation "generic_idivdi" 66 (eq_attr "mode" "DI"))) "imuldiv*66") +(define_insn_reservation "generic_fmul_half" 5 + (and (eq_attr "tune" "generic") + (and (eq_attr "type" "fadd,fmul,fmadd") + (eq_attr "mode" "HF"))) + "alu") + (define_insn_reservation "generic_fmul_single" 5 (and (eq_attr "tune" "generic") (and (eq_attr "type" "fadd,fmul,fmadd") @@ -88,3 +101,4 @@ (define_insn_reservation "generic_fsqrt" 25 (and (eq_attr "tune" "generic") (eq_attr "type" "fsqrt")) "fdivsqrt*25") + diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md index 39b29795cd6..1d2d24e3aaf 100644 --- a/gcc/config/riscv/riscv.md +++ b/gcc/config/riscv/riscv.md @@ -328,9 +328,7 @@ (define_attr "ext_enabled" "no,yes" ;; rotate rotation instructions ;; atomic atomic instructions ;; condmove conditional moves -;; cbo cache block instructions ;; crypto cryptography instructions -;; pushpop zc push and pop instructions ;; mvpair zc move pair instructions ;; zicond zicond instructions ;; Classification of RVV instructions which will be added to each RVV .md pattern and used by scheduler. @@ -470,7 +468,7 @@ (define_attr "type" mtc,mfc,const,arith,logical,shift,slt,imul,idiv,move,fmove,fadd,fmul, fmadd,fdiv,fcmp,fcvt,fcvt_i2f,fcvt_f2i,fsqrt,multi,auipc,sfb_alu,nop,trap, ghost,bitmanip,rotate,clmul,min,max,minu,maxu,clz,ctz,cpop, - atomic,condmove,cbo,crypto,pushpop,mvpair,zicond,rdvlenb,rdvl,wrvxrm,wrfrm, + atomic,condmove,crypto,mvpair,zicond,rdvlenb,rdvl,wrvxrm,wrfrm, rdfrm,vsetvl,vsetvl_pre,vlde,vste,vldm,vstm,vlds,vsts, vldux,vldox,vstux,vstox,vldff,vldr,vstr, vlsegde,vssegte,vlsegds,vssegts,vlsegdux,vlsegdox,vssegtux,vssegtox,vlsegdff, @@ -3675,7 +3673,7 @@ (define_insn "riscv_clean_" UNSPECV_CLEAN)] "TARGET_ZICBOM" "cbo.clean\t%a0" - [(set_attr "type" "cbo")] + [(set_attr "type" "store")] ) (define_insn "riscv_flush_" @@ -3683,7 +3681,7 @@ (define_insn "riscv_flush_" UNSPECV_FLUSH)] "TARGET_ZICBOM" "cbo.flush\t%a0" - [(set_attr "type" "cbo")] + [(set_attr "type" "store")] ) (define_insn "riscv_inval_" @@ -3691,7 +3689,7 @@ (define_insn "riscv_inval_" UNSPECV_INVAL)] "TARGET_ZICBOM" "cbo.inval\t%a0" - [(set_attr "type" "cbo")] + [(set_attr "type" "store")] ) (define_insn "riscv_zero_" @@ -3699,7 +3697,7 @@ (define_insn "riscv_zero_" UNSPECV_ZERO)] "TARGET_ZICBOZ" "cbo.zero\t%a0" - [(set_attr "type" "cbo")] + [(set_attr "type" "store")] ) (define_insn "prefetch" @@ -3715,7 +3713,7 @@ (define_insn "prefetch" default: gcc_unreachable (); } } - [(set_attr "type" "cbo")]) + [(set_attr "type" "store")]) (define_insn "riscv_prefetchi_" [(unspec_volatile:X [(match_operand:X 0 "address_operand" "r") @@ -3723,7 +3721,7 @@ (define_insn "riscv_prefetchi_" UNSPECV_PREI)] "TARGET_ZICBOP" "prefetch.i\t%a0" - [(set_attr "type" "cbo")]) + [(set_attr "type" "store")]) (define_expand "extv" [(set (match_operand:GPR 0 "register_operand" "=r") diff --git a/gcc/config/riscv/sifive-7.md b/gcc/config/riscv/sifive-7.md index 48bdba48190..c2085410889 100644 --- a/gcc/config/riscv/sifive-7.md +++ b/gcc/config/riscv/sifive-7.md @@ -34,7 +34,7 @@ (define_insn_reservation "sifive_7_fpstore" 1 (define_insn_reservation "sifive_7_branch" 1 (and (eq_attr "tune" "sifive_7") - (eq_attr "type" "branch")) + (eq_attr "type" "branch,ret,trap")) "sifive_7_B") (define_insn_reservation "sifive_7_sfb_alu" 2 @@ -59,7 +59,8 @@ (define_insn_reservation "sifive_7_div" 16 (define_insn_reservation "sifive_7_alu" 2 (and (eq_attr "tune" "sifive_7") - (eq_attr "type" "unknown,arith,shift,slt,multi,logical,move")) + (eq_attr "type" "unknown,arith,shift,slt,multi,logical,move,bitmanip,\ + rotate,min,max,minu,maxu,clz,ctz,atomic,condmove,mvpair,zicond")) "sifive_7_A|sifive_7_B") (define_insn_reservation "sifive_7_load_immediate" 1 @@ -67,6 +68,12 @@ (define_insn_reservation "sifive_7_load_immediate" 1 (eq_attr "type" "nop,const,auipc")) "sifive_7_A|sifive_7_B") +(define_insn_reservation "sifive_7_hfma" 5 + (and (eq_attr "tune" "sifive_7") + (and (eq_attr "type" "fadd,fmul,fmadd") + (eq_attr "mode" "HF"))) + "sifive_7_B") + (define_insn_reservation "sifive_7_sfma" 5 (and (eq_attr "tune" "sifive_7") (and (eq_attr "type" "fadd,fmul,fmadd") @@ -106,6 +113,12 @@ (define_insn_reservation "sifive_7_f2i" 3 (eq_attr "type" "mfc")) "sifive_7_A") +;; Popcount and clmul. +(define_insn_reservation "sifive_7_popcount" 2 + (and (eq_attr "tune" "sifive_7") + (eq_attr "type" "cpop,clmul")) + "sifive_7_A") + (define_bypass 1 "sifive_7_load,sifive_7_alu,sifive_7_mul,sifive_7_f2i,sifive_7_sfb_alu" "sifive_7_alu,sifive_7_branch") diff --git a/gcc/config/riscv/sifive-p400.md b/gcc/config/riscv/sifive-p400.md index cc244d3c3e6..ed8b8ec9da7 100644 --- a/gcc/config/riscv/sifive-p400.md +++ b/gcc/config/riscv/sifive-p400.md @@ -89,7 +89,7 @@ (define_insn_reservation "sifive_p400_fpstore" 1 (define_insn_reservation "sifive_p400_branch" 1 (and (eq_attr "tune" "sifive_p400") - (eq_attr "type" "branch,jump,call")) + (eq_attr "type" "branch,jump,call,jalr,ret,trap")) "sifive_p400_B+sifive_p400_bru") (define_insn_reservation "sifive_p400_sfb_alu" 1 @@ -114,7 +114,8 @@ (define_insn_reservation "sifive_p400_div" 31 (define_insn_reservation "sifive_p400_alu" 1 (and (eq_attr "tune" "sifive_p400") - (eq_attr "type" "unknown,arith,logical,shift,slt,multi,bitmanip,clz,ctz,rotate")) + (eq_attr "type" "unknown,arith,logical,shift,slt,multi,bitmanip,\ + clz,ctz,rotate,min,max,minu,maxu,condmove,mvpair,zicond")) "p400_int_pipe+sifive_p400_ialu") (define_insn_reservation "sifive_p400_cpop" 3 @@ -122,6 +123,11 @@ (define_insn_reservation "sifive_p400_cpop" 3 (eq_attr "type" "cpop")) "p400_int_pipe,sifive_p400_ialu*2") +(define_insn_reservation "sifive_p400_clmul" 3 + (and (eq_attr "tune" "sifive_p400") + (eq_attr "type" "clmul")) + "p400_int_pipe,sifive_p400_ialu*2") + (define_insn_reservation "sifive_p400_load_immediate" 1 (and (eq_attr "tune" "sifive_p400") (eq_attr "type" "nop,const,auipc,move")) diff --git a/gcc/config/riscv/sifive-p600.md b/gcc/config/riscv/sifive-p600.md index c0486491d46..240134976fa 100644 --- a/gcc/config/riscv/sifive-p600.md +++ b/gcc/config/riscv/sifive-p600.md @@ -93,7 +93,7 @@ (define_insn_reservation "sifive_p600_fpstore" 1 (define_insn_reservation "sifive_p600_branch" 1 (and (eq_attr "tune" "sifive_p600") - (eq_attr "type" "branch,jump,call")) + (eq_attr "type" "branch,jump,call,jalr,ret,trap")) "branch_pipe+sifive_p600_bru") (define_insn_reservation "sifive_p600_sfb_alu" 1 @@ -118,7 +118,8 @@ (define_insn_reservation "sifive_p600_div" 16 (define_insn_reservation "sifive_p600_alu" 1 (and (eq_attr "tune" "sifive_p600") - (eq_attr "type" "unknown,arith,logical,shift,slt,multi,bitmanip,clz,ctz,rotate")) + (eq_attr "type" "unknown,arith,logical,shift,slt,multi,bitmanip,\ + clz,ctz,rotate,min,max,minu,maxu,condmove,mvpair,zicond")) "int_pipe+sifive_p600_ialu") (define_insn_reservation "sifive_p600_cpop" 3 @@ -126,6 +127,11 @@ (define_insn_reservation "sifive_p600_cpop" 3 (eq_attr "type" "cpop")) "int_pipe,sifive_p600_ialu*2") +(define_insn_reservation "sifive_p600_clmul" 3 + (and (eq_attr "tune" "sifive_p600") + (eq_attr "type" "clmul")) + "int_pipe,sifive_p600_ialu*2") + (define_insn_reservation "sifive_p600_load_immediate" 1 (and (eq_attr "tune" "sifive_p600") (eq_attr "type" "nop,const,auipc,move")) diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md index ab6e099852d..f89f9c2fa86 100644 --- a/gcc/config/riscv/vector.md +++ b/gcc/config/riscv/vector.md @@ -1054,7 +1054,7 @@ (define_insn "frrmsi" (reg:SI FRM_REGNUM))] "TARGET_VECTOR" "frrm\t%0" - [(set_attr "type" "rdfrm") + [(set_attr "type" "fmove") (set_attr "mode" "SI")] ) diff --git a/gcc/config/riscv/zc.md b/gcc/config/riscv/zc.md index 216232cb9f2..462ab37569e 100644 --- a/gcc/config/riscv/zc.md +++ b/gcc/config/riscv/zc.md @@ -27,7 +27,7 @@ (define_insn "@gpr_multi_pop_up_to_ra_" (const_int ))))] "TARGET_ZCMP" "cm.pop {ra}, %0" -[(set_attr "type" "pushpop")]) +[(set_attr "type" "load")]) (define_insn "@gpr_multi_pop_up_to_s0_" [(set (reg:X SP_REGNUM) @@ -41,7 +41,7 @@ (define_insn "@gpr_multi_pop_up_to_s0_" (const_int ))))] "TARGET_ZCMP" "cm.pop {ra, s0}, %0" -[(set_attr "type" "pushpop")]) +[(set_attr "type" "load")]) (define_insn "@gpr_multi_pop_up_to_s1_" [(set (reg:X SP_REGNUM) @@ -58,7 +58,7 @@ (define_insn "@gpr_multi_pop_up_to_s1_" (const_int ))))] "TARGET_ZCMP" "cm.pop {ra, s0-s1}, %0" -[(set_attr "type" "pushpop")]) +[(set_attr "type" "load")]) (define_insn "@gpr_multi_pop_up_to_s2_" [(set (reg:X SP_REGNUM) @@ -78,7 +78,7 @@ (define_insn "@gpr_multi_pop_up_to_s2_" (const_int ))))] "TARGET_ZCMP" "cm.pop {ra, s0-s2}, %0" -[(set_attr "type" "pushpop")]) +[(set_attr "type" "load")]) (define_insn "@gpr_multi_pop_up_to_s3_" [(set (reg:X SP_REGNUM) @@ -101,7 +101,7 @@ (define_insn "@gpr_multi_pop_up_to_s3_" (const_int ))))] "TARGET_ZCMP" "cm.pop {ra, s0-s3}, %0" -[(set_attr "type" "pushpop")]) +[(set_attr "type" "load")]) (define_insn "@gpr_multi_pop_up_to_s4_" [(set (reg:X SP_REGNUM) @@ -127,7 +127,7 @@ (define_insn "@gpr_multi_pop_up_to_s4_" (const_int ))))] "TARGET_ZCMP" "cm.pop {ra, s0-s4}, %0" -[(set_attr "type" "pushpop")]) +[(set_attr "type" "load")]) (define_insn "@gpr_multi_pop_up_to_s5_" [(set (reg:X SP_REGNUM) @@ -156,7 +156,7 @@ (define_insn "@gpr_multi_pop_up_to_s5_" (const_int ))))] "TARGET_ZCMP" "cm.pop {ra, s0-s5}, %0" -[(set_attr "type" "pushpop")]) +[(set_attr "type" "load")]) (define_insn "@gpr_multi_pop_up_to_s6_" [(set (reg:X SP_REGNUM) @@ -188,7 +188,7 @@ (define_insn "@gpr_multi_pop_up_to_s6_" (const_int ))))] "TARGET_ZCMP" "cm.pop {ra, s0-s6}, %0" -[(set_attr "type" "pushpop")]) +[(set_attr "type" "load")]) (define_insn "@gpr_multi_pop_up_to_s7_" [(set (reg:X SP_REGNUM) @@ -223,7 +223,7 @@ (define_insn "@gpr_multi_pop_up_to_s7_" (const_int ))))] "TARGET_ZCMP" "cm.pop {ra, s0-s7}, %0" -[(set_attr "type" "pushpop")]) +[(set_attr "type" "load")]) (define_insn "@gpr_multi_pop_up_to_s8_" [(set (reg:X SP_REGNUM) @@ -261,7 +261,7 @@ (define_insn "@gpr_multi_pop_up_to_s8_" (const_int ))))] "TARGET_ZCMP" "cm.pop {ra, s0-s8}, %0" -[(set_attr "type" "pushpop")]) +[(set_attr "type" "load")]) (define_insn "@gpr_multi_pop_up_to_s9_" [(set (reg:X SP_REGNUM) @@ -302,7 +302,7 @@ (define_insn "@gpr_multi_pop_up_to_s9_" (const_int ))))] "TARGET_ZCMP" "cm.pop {ra, s0-s9}, %0" -[(set_attr "type" "pushpop")]) +[(set_attr "type" "load")]) (define_insn "@gpr_multi_pop_up_to_s11_" [(set (reg:X SP_REGNUM) @@ -349,7 +349,7 @@ (define_insn "@gpr_multi_pop_up_to_s11_" (const_int ))))] "TARGET_ZCMP" "cm.pop {ra, s0-s11}, %0" -[(set_attr "type" "pushpop")]) +[(set_attr "type" "load")]) (define_insn "@gpr_multi_popret_up_to_ra_" [(set (reg:X SP_REGNUM) @@ -362,7 +362,7 @@ (define_insn "@gpr_multi_popret_up_to_ra_" (use (reg:SI RETURN_ADDR_REGNUM))] "TARGET_ZCMP" "cm.popret {ra}, %0" -[(set_attr "type" "pushpop")]) +[(set_attr "type" "load")]) (define_insn "@gpr_multi_popret_up_to_s0_" [(set (reg:X SP_REGNUM) @@ -378,7 +378,7 @@ (define_insn "@gpr_multi_popret_up_to_s0_" (use (reg:SI RETURN_ADDR_REGNUM))] "TARGET_ZCMP" "cm.popret {ra, s0}, %0" -[(set_attr "type" "pushpop")]) +[(set_attr "type" "load")]) (define_insn "@gpr_multi_popret_up_to_s1_" [(set (reg:X SP_REGNUM) @@ -397,7 +397,7 @@ (define_insn "@gpr_multi_popret_up_to_s1_" (use (reg:SI RETURN_ADDR_REGNUM))] "TARGET_ZCMP" "cm.popret {ra, s0-s1}, %0" -[(set_attr "type" "pushpop")]) +[(set_attr "type" "load")]) (define_insn "@gpr_multi_popret_up_to_s2_" [(set (reg:X SP_REGNUM) @@ -419,7 +419,7 @@ (define_insn "@gpr_multi_popret_up_to_s2_" (use (reg:SI RETURN_ADDR_REGNUM))] "TARGET_ZCMP" "cm.popret {ra, s0-s2}, %0" -[(set_attr "type" "pushpop")]) +[(set_attr "type" "load")]) (define_insn "@gpr_multi_popret_up_to_s3_" [(set (reg:X SP_REGNUM) @@ -444,7 +444,7 @@ (define_insn "@gpr_multi_popret_up_to_s3_" (use (reg:SI RETURN_ADDR_REGNUM))] "TARGET_ZCMP" "cm.popret {ra, s0-s3}, %0" -[(set_attr "type" "pushpop")]) +[(set_attr "type" "load")]) (define_insn "@gpr_multi_popret_up_to_s4_" [(set (reg:X SP_REGNUM) @@ -472,7 +472,7 @@ (define_insn "@gpr_multi_popret_up_to_s4_" (use (reg:SI RETURN_ADDR_REGNUM))] "TARGET_ZCMP" "cm.popret {ra, s0-s4}, %0" -[(set_attr "type" "pushpop")]) +[(set_attr "type" "load")]) (define_insn "@gpr_multi_popret_up_to_s5_" [(set (reg:X SP_REGNUM) @@ -503,7 +503,7 @@ (define_insn "@gpr_multi_popret_up_to_s5_" (use (reg:SI RETURN_ADDR_REGNUM))] "TARGET_ZCMP" "cm.popret {ra, s0-s5}, %0" -[(set_attr "type" "pushpop")]) +[(set_attr "type" "load")]) (define_insn "@gpr_multi_popret_up_to_s6_" [(set (reg:X SP_REGNUM) @@ -537,7 +537,7 @@ (define_insn "@gpr_multi_popret_up_to_s6_" (use (reg:SI RETURN_ADDR_REGNUM))] "TARGET_ZCMP" "cm.popret {ra, s0-s6}, %0" -[(set_attr "type" "pushpop")]) +[(set_attr "type" "load")]) (define_insn "@gpr_multi_popret_up_to_s7_" [(set (reg:X SP_REGNUM) @@ -574,7 +574,7 @@ (define_insn "@gpr_multi_popret_up_to_s7_" (use (reg:SI RETURN_ADDR_REGNUM))] "TARGET_ZCMP" "cm.popret {ra, s0-s7}, %0" -[(set_attr "type" "pushpop")]) +[(set_attr "type" "load")]) (define_insn "@gpr_multi_popret_up_to_s8_" [(set (reg:X SP_REGNUM) @@ -614,7 +614,7 @@ (define_insn "@gpr_multi_popret_up_to_s8_" (use (reg:SI RETURN_ADDR_REGNUM))] "TARGET_ZCMP" "cm.popret {ra, s0-s8}, %0" -[(set_attr "type" "pushpop")]) +[(set_attr "type" "load")]) (define_insn "@gpr_multi_popret_up_to_s9_" [(set (reg:X SP_REGNUM) @@ -657,7 +657,7 @@ (define_insn "@gpr_multi_popret_up_to_s9_" (use (reg:SI RETURN_ADDR_REGNUM))] "TARGET_ZCMP" "cm.popret {ra, s0-s9}, %0" -[(set_attr "type" "pushpop")]) +[(set_attr "type" "load")]) (define_insn "@gpr_multi_popret_up_to_s11_" [(set (reg:X SP_REGNUM) @@ -706,7 +706,7 @@ (define_insn "@gpr_multi_popret_up_to_s11_" (use (reg:SI RETURN_ADDR_REGNUM))] "TARGET_ZCMP" "cm.popret {ra, s0-s11}, %0" -[(set_attr "type" "pushpop")]) +[(set_attr "type" "load")]) (define_insn "@gpr_multi_popretz_up_to_ra_" [(set (reg:X SP_REGNUM) @@ -722,7 +722,7 @@ (define_insn "@gpr_multi_popretz_up_to_ra_" (use (reg:SI RETURN_ADDR_REGNUM))] "TARGET_ZCMP" "cm.popretz {ra}, %0" -[(set_attr "type" "pushpop")]) +[(set_attr "type" "load")]) (define_insn "@gpr_multi_popretz_up_to_s0_" [(set (reg:X SP_REGNUM) @@ -741,7 +741,7 @@ (define_insn "@gpr_multi_popretz_up_to_s0_" (use (reg:SI RETURN_ADDR_REGNUM))] "TARGET_ZCMP" "cm.popretz {ra, s0}, %0" -[(set_attr "type" "pushpop")]) +[(set_attr "type" "load")]) (define_insn "@gpr_multi_popretz_up_to_s1_" [(set (reg:X SP_REGNUM) @@ -763,7 +763,7 @@ (define_insn "@gpr_multi_popretz_up_to_s1_" (use (reg:SI RETURN_ADDR_REGNUM))] "TARGET_ZCMP" "cm.popretz {ra, s0-s1}, %0" -[(set_attr "type" "pushpop")]) +[(set_attr "type" "load")]) (define_insn "@gpr_multi_popretz_up_to_s2_" [(set (reg:X SP_REGNUM) @@ -788,7 +788,7 @@ (define_insn "@gpr_multi_popretz_up_to_s2_" (use (reg:SI RETURN_ADDR_REGNUM))] "TARGET_ZCMP" "cm.popretz {ra, s0-s2}, %0" -[(set_attr "type" "pushpop")]) +[(set_attr "type" "load")]) (define_insn "@gpr_multi_popretz_up_to_s3_" [(set (reg:X SP_REGNUM) @@ -816,7 +816,7 @@ (define_insn "@gpr_multi_popretz_up_to_s3_" (use (reg:SI RETURN_ADDR_REGNUM))] "TARGET_ZCMP" "cm.popretz {ra, s0-s3}, %0" -[(set_attr "type" "pushpop")]) +[(set_attr "type" "load")]) (define_insn "@gpr_multi_popretz_up_to_s4_" [(set (reg:X SP_REGNUM) @@ -847,7 +847,7 @@ (define_insn "@gpr_multi_popretz_up_to_s4_" (use (reg:SI RETURN_ADDR_REGNUM))] "TARGET_ZCMP" "cm.popretz {ra, s0-s4}, %0" -[(set_attr "type" "pushpop")]) +[(set_attr "type" "load")]) (define_insn "@gpr_multi_popretz_up_to_s5_" [(set (reg:X SP_REGNUM) @@ -881,7 +881,7 @@ (define_insn "@gpr_multi_popretz_up_to_s5_" (use (reg:SI RETURN_ADDR_REGNUM))] "TARGET_ZCMP" "cm.popretz {ra, s0-s5}, %0" -[(set_attr "type" "pushpop")]) +[(set_attr "type" "load")]) (define_insn "@gpr_multi_popretz_up_to_s6_" [(set (reg:X SP_REGNUM) @@ -918,7 +918,7 @@ (define_insn "@gpr_multi_popretz_up_to_s6_" (use (reg:SI RETURN_ADDR_REGNUM))] "TARGET_ZCMP" "cm.popretz {ra, s0-s6}, %0" -[(set_attr "type" "pushpop")]) +[(set_attr "type" "load")]) (define_insn "@gpr_multi_popretz_up_to_s7_" [(set (reg:X SP_REGNUM) @@ -958,7 +958,7 @@ (define_insn "@gpr_multi_popretz_up_to_s7_" (use (reg:SI RETURN_ADDR_REGNUM))] "TARGET_ZCMP" "cm.popretz {ra, s0-s7}, %0" -[(set_attr "type" "pushpop")]) +[(set_attr "type" "load")]) (define_insn "@gpr_multi_popretz_up_to_s8_" [(set (reg:X SP_REGNUM) @@ -1001,7 +1001,7 @@ (define_insn "@gpr_multi_popretz_up_to_s8_" (use (reg:SI RETURN_ADDR_REGNUM))] "TARGET_ZCMP" "cm.popretz {ra, s0-s8}, %0" -[(set_attr "type" "pushpop")]) +[(set_attr "type" "load")]) (define_insn "@gpr_multi_popretz_up_to_s9_" [(set (reg:X SP_REGNUM) @@ -1047,7 +1047,7 @@ (define_insn "@gpr_multi_popretz_up_to_s9_" (use (reg:SI RETURN_ADDR_REGNUM))] "TARGET_ZCMP" "cm.popretz {ra, s0-s9}, %0" -[(set_attr "type" "pushpop")]) +[(set_attr "type" "load")]) (define_insn "@gpr_multi_popretz_up_to_s11_" [(set (reg:X SP_REGNUM) @@ -1099,7 +1099,7 @@ (define_insn "@gpr_multi_popretz_up_to_s11_" (use (reg:SI RETURN_ADDR_REGNUM))] "TARGET_ZCMP" "cm.popretz {ra, s0-s11}, %0" -[(set_attr "type" "pushpop")]) +[(set_attr "type" "load")]) (define_insn "@gpr_multi_push_up_to_ra_" [(set (mem:X (plus:X (reg:X SP_REGNUM) @@ -1110,7 +1110,7 @@ (define_insn "@gpr_multi_push_up_to_ra_" (match_operand 0 "stack_push_up_to_ra_operand" "I")))] "TARGET_ZCMP" "cm.push {ra}, %0" -[(set_attr "type" "pushpop")]) +[(set_attr "type" "store")]) (define_insn "@gpr_multi_push_up_to_s0_" [(set (mem:X (plus:X (reg:X SP_REGNUM) @@ -1124,7 +1124,7 @@ (define_insn "@gpr_multi_push_up_to_s0_" (match_operand 0 "stack_push_up_to_s0_operand" "I")))] "TARGET_ZCMP" "cm.push {ra, s0}, %0" -[(set_attr "type" "pushpop")]) +[(set_attr "type" "store")]) (define_insn "@gpr_multi_push_up_to_s1_" [(set (mem:X (plus:X (reg:X SP_REGNUM) @@ -1141,7 +1141,7 @@ (define_insn "@gpr_multi_push_up_to_s1_" (match_operand 0 "stack_push_up_to_s1_operand" "I")))] "TARGET_ZCMP" "cm.push {ra, s0-s1}, %0" -[(set_attr "type" "pushpop")]) +[(set_attr "type" "store")]) (define_insn "@gpr_multi_push_up_to_s2_" [(set (mem:X (plus:X (reg:X SP_REGNUM) @@ -1161,7 +1161,7 @@ (define_insn "@gpr_multi_push_up_to_s2_" (match_operand 0 "stack_push_up_to_s2_operand" "I")))] "TARGET_ZCMP" "cm.push {ra, s0-s2}, %0" -[(set_attr "type" "pushpop")]) +[(set_attr "type" "store")]) (define_insn "@gpr_multi_push_up_to_s3_" [(set (mem:X (plus:X (reg:X SP_REGNUM) @@ -1184,7 +1184,7 @@ (define_insn "@gpr_multi_push_up_to_s3_" (match_operand 0 "stack_push_up_to_s3_operand" "I")))] "TARGET_ZCMP" "cm.push {ra, s0-s3}, %0" -[(set_attr "type" "pushpop")]) +[(set_attr "type" "store")]) (define_insn "@gpr_multi_push_up_to_s4_" [(set (mem:X (plus:X (reg:X SP_REGNUM) @@ -1210,7 +1210,7 @@ (define_insn "@gpr_multi_push_up_to_s4_" (match_operand 0 "stack_push_up_to_s4_operand" "I")))] "TARGET_ZCMP" "cm.push {ra, s0-s4}, %0" -[(set_attr "type" "pushpop")]) +[(set_attr "type" "store")]) (define_insn "@gpr_multi_push_up_to_s5_" [(set (mem:X (plus:X (reg:X SP_REGNUM) @@ -1239,7 +1239,7 @@ (define_insn "@gpr_multi_push_up_to_s5_" (match_operand 0 "stack_push_up_to_s5_operand" "I")))] "TARGET_ZCMP" "cm.push {ra, s0-s5}, %0" -[(set_attr "type" "pushpop")]) +[(set_attr "type" "store")]) (define_insn "@gpr_multi_push_up_to_s6_" [(set (mem:X (plus:X (reg:X SP_REGNUM) @@ -1271,7 +1271,7 @@ (define_insn "@gpr_multi_push_up_to_s6_" (match_operand 0 "stack_push_up_to_s6_operand" "I")))] "TARGET_ZCMP" "cm.push {ra, s0-s6}, %0" -[(set_attr "type" "pushpop")]) +[(set_attr "type" "store")]) (define_insn "@gpr_multi_push_up_to_s7_" [(set (mem:X (plus:X (reg:X SP_REGNUM) @@ -1306,7 +1306,7 @@ (define_insn "@gpr_multi_push_up_to_s7_" (match_operand 0 "stack_push_up_to_s7_operand" "I")))] "TARGET_ZCMP" "cm.push {ra, s0-s7}, %0" -[(set_attr "type" "pushpop")]) +[(set_attr "type" "store")]) (define_insn "@gpr_multi_push_up_to_s8_" [(set (mem:X (plus:X (reg:X SP_REGNUM) @@ -1344,7 +1344,7 @@ (define_insn "@gpr_multi_push_up_to_s8_" (match_operand 0 "stack_push_up_to_s8_operand" "I")))] "TARGET_ZCMP" "cm.push {ra, s0-s8}, %0" -[(set_attr "type" "pushpop")]) +[(set_attr "type" "store")]) (define_insn "@gpr_multi_push_up_to_s9_" [(set (mem:X (plus:X (reg:X SP_REGNUM) @@ -1385,7 +1385,7 @@ (define_insn "@gpr_multi_push_up_to_s9_" (match_operand 0 "stack_push_up_to_s9_operand" "I")))] "TARGET_ZCMP" "cm.push {ra, s0-s9}, %0" -[(set_attr "type" "pushpop")]) +[(set_attr "type" "store")]) (define_insn "@gpr_multi_push_up_to_s11_" [(set (mem:X (plus:X (reg:X SP_REGNUM) @@ -1432,7 +1432,7 @@ (define_insn "@gpr_multi_push_up_to_s11_" (match_operand 0 "stack_push_up_to_s11_operand" "I")))] "TARGET_ZCMP" "cm.push {ra, s0-s11}, %0" -[(set_attr "type" "pushpop")]) +[(set_attr "type" "store")]) ;; ZCMP mv (define_insn "*mva01s"