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[2620:52:3:1:0:246e:9693:128c]) by mx.google.com with ESMTPS id k10-20020a0cebca000000b0068c88fd398dsi767897qvq.2.2024.02.07.01.28.52 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 07 Feb 2024 01:28:52 -0800 (PST) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) client-ip=2620:52:3:1:0:246e:9693:128c; Authentication-Results: mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=IdqEkmQP; arc=pass (i=1); spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 23D653858415 for ; Wed, 7 Feb 2024 09:28:52 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.16]) by sourceware.org (Postfix) with ESMTPS id 87DA73858C53 for ; Wed, 7 Feb 2024 09:28:04 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 87DA73858C53 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=intel.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 87DA73858C53 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=192.198.163.16 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1707298087; cv=none; b=PneolHfdz5k41lJRqDlTRw6ovouftsm1bTHXCXjdUIRWlRlFEdDSCyRilWVBpUKfQeUYUcCPDr6ZSdisxEfNznbHNKtcapeHuW3EmG1gZ1HO4HnWKlwY7JnEfqVwD3aL+WgReC6elxrQJlQJ83UEN4qWS9nNxcICqVOfgoN4gow= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1707298087; c=relaxed/simple; bh=guPL18q9SJgU0Cg2/X6BAieoMukzEe7X3qHMKAqJh5w=; h=DKIM-Signature:From:To:Subject:Date:Message-Id:MIME-Version; b=qiiM4lPDnk0lJqXApLaLDsOmNhCqHLIVxj5RrRwdEhfObvs1HGdmDCSaOpBGb1tS0zeoVs1ADhdWswUhEDuxYKY2Tj1FClU3hRO8N34R6gz8j3UABIIA9AwOYo7KWoPB6X/wFvaz8nHjt+7dTOIFBzHD8kaYaop1GaK8QHpQURI= ARC-Authentication-Results: i=1; server2.sourceware.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1707298084; x=1738834084; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=guPL18q9SJgU0Cg2/X6BAieoMukzEe7X3qHMKAqJh5w=; b=IdqEkmQPAzw2iiHWgCeu1sK7mmojzWqFMS0FBSQel5Ys/cacYBrjR2Cj 9qggS4iTcKlpcfAa4/R9oj1ES/49dshkb02tTbaB6rPjWzsc2Jv88iNtZ XnFsv7xDCncRAnJQlfZrN6HsV1JlCmRxLfCWyqfIt5v+0+zRECBcFhxr3 gonHX/eCVQZjQsQBXiP4GJTyLLyimJbd83ezjaWuaLOu7rGHTkFUkM9Pt 2qSKPaBqibVTjIY5W+K3Eu/5Xi5xeoDSaO3ieD4wmh4tXIDiiQsTPIHbE vqbKhJFDyKjforMDV6GY1eazYalJ3BBw1Dw2z412t/9op9BvParGN8tT4 w==; X-IronPort-AV: E=McAfee;i="6600,9927,10976"; a="1225246" X-IronPort-AV: E=Sophos;i="6.05,250,1701158400"; d="scan'208";a="1225246" Received: from orviesa010.jf.intel.com ([10.64.159.150]) by fmvoesa110.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Feb 2024 01:28:02 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.05,250,1701158400"; d="scan'208";a="1308375" Received: from shvmail02.sh.intel.com ([10.239.244.9]) by orviesa010.jf.intel.com with ESMTP; 07 Feb 2024 01:28:00 -0800 Received: from pli-ubuntu.sh.intel.com (pli-ubuntu.sh.intel.com [10.239.159.47]) by shvmail02.sh.intel.com (Postfix) with ESMTP id BF812100568E; Wed, 7 Feb 2024 17:27:59 +0800 (CST) From: pan2.li@intel.com To: gcc-patches@gcc.gnu.org Cc: juzhe.zhong@rivai.ai, pan2.li@intel.com, yanzhang.wang@intel.com, kito.cheng@gmail.com Subject: [PATCH v1] RISC-V: Bugfix for RVV overloaded intrinsic ICE in function checker Date: Wed, 7 Feb 2024 17:27:56 +0800 Message-Id: <20240207092756.4134886-1-pan2.li@intel.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 X-Spam-Status: No, score=-11.4 required=5.0 tests=BAYES_00, DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, KAM_SHORT, SPF_HELO_NONE, SPF_NONE, TXREP, T_SCC_BODY_TEXT_LINE, WEIRD_PORT autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1790231846279787234 X-GMAIL-MSGID: 1790231846279787234 From: Pan Li There is another corn case when similar as below example: void test (void) { __riscv_vaadd (); } We report error when overloaded function with empty args. For example: test.c: In function 'foo': test.c:8:3: error: no matching function call to '__riscv_vaadd' with empty args 8 | __riscv_vaadd (); | ^~~~~~~~~~~~~~~~~~~~ Unfortunately, it will meet another ICE similar to below after above message. The underlying build function checker will have zero args and break some assumption of the function checker. For example, the count of args is not less than 2. ice.c: In function ‘foo’: ice.c:8:3: internal compiler error: in require_immediate, at config/riscv/riscv-vector-builtins.cc:4252 8 | __riscv_vaadd (); | ^~~~~~~~~~~~~ 0x20b36ac riscv_vector::function_checker::require_immediate(unsigned int, long, long) const .../__RISC-V_BUILD__/../gcc/config/riscv/riscv-vector-builtins.cc:4252 0x20b890c riscv_vector::alu_def::check(riscv_vector::function_checker&) const .../__RISC-V_BUILD__/../gcc/config/riscv/riscv-vector-builtins-shapes.cc:387 0x20b38d7 riscv_vector::function_checker::check() .../__RISC-V_BUILD__/../gcc/config/riscv/riscv-vector-builtins.cc:4315 0x20b4876 riscv_vector::check_builtin_call(unsigned int, vec, .../__RISC-V_BUILD__/../gcc/config/riscv/riscv-vector-builtins.cc:4605 0x2069393 riscv_check_builtin_call .../__RISC-V_BUILD__/../gcc/config/riscv/riscv-c.cc:227 Below test are passed for this patch. * The riscv regression tests. PR target/113766 gcc/ChangeLog: * config/riscv/riscv-vector-builtins-shapes.cc (struct alu_def): Make sure the c.arg_num is >= 2 before checking. (struct build_frm_base): Ditto. (struct narrow_alu_def): Ditto. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/base/pr113766-1.c: Add new cases. Signed-off-by: Pan Li Signed-off-by: Pan Li Signed-off-by: Pan Li Signed-off-by: Pan Li > --- .../riscv/riscv-vector-builtins-shapes.cc | 17 +++++++++++++---- .../gcc.target/riscv/rvv/base/pr113766-1.c | 16 ++++++++++++++++ 2 files changed, 29 insertions(+), 4 deletions(-) diff --git a/gcc/config/riscv/riscv-vector-builtins-shapes.cc b/gcc/config/riscv/riscv-vector-builtins-shapes.cc index 8e90b17a94b..c5ffcc1f2c4 100644 --- a/gcc/config/riscv/riscv-vector-builtins-shapes.cc +++ b/gcc/config/riscv/riscv-vector-builtins-shapes.cc @@ -383,7 +383,10 @@ struct alu_def : public build_base /* Check whether rounding mode argument is a valid immediate. */ if (c.base->has_rounding_mode_operand_p ()) { - if (!c.any_type_float_p ()) + /* Some invalid overload intrinsic like below will have zero for + c.arg_num (). Thus, make sure arg_num is big enough here. + __riscv_vaadd () will make c.arg_num () == 0. */ + if (!c.any_type_float_p () && c.arg_num () >= 2) return c.require_immediate (c.arg_num () - 2, VXRM_RNU, VXRM_ROD); /* TODO: We will support floating-point intrinsic modeling rounding mode in the future. */ @@ -411,8 +414,11 @@ struct build_frm_base : public build_base { gcc_assert (c.any_type_float_p ()); - /* Check whether rounding mode argument is a valid immediate. */ - if (c.base->has_rounding_mode_operand_p ()) + /* Check whether rounding mode argument is a valid immediate. + Some invalid overload intrinsic like below will have zero for + c.arg_num (). Thus, make sure arg_num is big enough here. + __riscv_vaadd () will make c.arg_num () == 0. */ + if (c.base->has_rounding_mode_operand_p () && c.arg_num () >= 2) { unsigned int frm_num = c.arg_num () - 2; @@ -679,7 +685,10 @@ struct narrow_alu_def : public build_base /* Check whether rounding mode argument is a valid immediate. */ if (c.base->has_rounding_mode_operand_p ()) { - if (!c.any_type_float_p ()) + /* Some invalid overload intrinsic like below will have zero for + c.arg_num (). Thus, make sure arg_num is big enough here. + __riscv_vaadd () will make c.arg_num () == 0. */ + if (!c.any_type_float_p () && c.arg_num () >= 2) return c.require_immediate (c.arg_num () - 2, VXRM_RNU, VXRM_ROD); /* TODO: We will support floating-point intrinsic modeling rounding mode in the future. */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr113766-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr113766-1.c index bd4943b0b7e..fd674a8895c 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr113766-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr113766-1.c @@ -82,4 +82,20 @@ test () __riscv_vfredosum (); /* { dg-error {no matching function call to '__riscv_vfredosum' with empty args} } */ __riscv_vfredosum_tu (); /* { dg-error {no matching function call to '__riscv_vfredosum_tu' with empty args} } */ + + __riscv_vaadd (); /* { dg-error {no matching function call to '__riscv_vaadd' with empty args} } */ + + __riscv_vaaddu (); /* { dg-error {no matching function call to '__riscv_vaaddu' with empty args} } */ + + __riscv_vadc (); /* { dg-error {no matching function call to '__riscv_vadc' with empty args} } */ + + __riscv_vnmsac (); /* { dg-error {no matching function call to '__riscv_vnmsac' with empty args} } */ + + __riscv_vnsrl (); /* { dg-error {no matching function call to '__riscv_vnsrl' with empty args} } */ + + __riscv_vfnmadd (); /* { dg-error {no matching function call to '__riscv_vfnmadd' with empty args} } */ + + __riscv_vfwsub_vv (); /* { dg-error {no matching function call to '__riscv_vfwsub_vv' with empty args} } */ + + __riscv_vfwredosum (); /* { dg-error {no matching function call to '__riscv_vfwredosum' with empty args} } */ }