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[8.43.85.97]) by mx.google.com with ESMTPS id vw19-20020a05620a565300b007840b2928e5si6668849qkn.236.2024.02.04.10.02.10 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 04 Feb 2024 10:02:10 -0800 (PST) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) client-ip=8.43.85.97; Authentication-Results: mx.google.com; dkim=pass header.i=@xry111.site header.s=default header.b=gIOl3sMK; arc=pass (i=1); spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org"; dmarc=pass (p=REJECT sp=REJECT dis=NONE) header.from=xry111.site Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id DC4D2385829F for ; Sun, 4 Feb 2024 18:02:09 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from xry111.site (xry111.site [89.208.246.23]) by sourceware.org (Postfix) with ESMTPS id 1D3A73858C41; Sun, 4 Feb 2024 18:01:31 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 1D3A73858C41 Authentication-Results: sourceware.org; dmarc=pass (p=reject dis=none) header.from=xry111.site Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=xry111.site ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 1D3A73858C41 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=89.208.246.23 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1707069692; cv=none; b=eInrS6PiT0czSSTbwvtUTquGd5VQMZapfJs6Um4SQqlVosGYaNCwrEwKmvMsTtYK+3A5vLXjkenC165rNLoFC8HGLKNrhzORrJTbQAZd/FhC0xrd6lAq7g4XilxEoqEETOGadEerq5xwlK7k4t5Lfyh4RYdJSHxf3qwz/oNdCBU= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1707069692; c=relaxed/simple; bh=xoneVYMnudt0sgebgecHS+WkrK+tqCFgUxjENzEkN8s=; h=DKIM-Signature:From:To:Subject:Date:Message-ID:MIME-Version; b=cD0NNQ+8TceDk8QMbJtVtz3k8DIPsZAwofrQ7tOGuFMXgrWlZpwbXVrZQqHLUjCcmLQOVCxly/csDdHGl2F82i27ZRzjto0Qodw6JdJwx69eePUKVUgMDlsQ3+rdzgFi6Ng3Wo5YkWc34DyqBdd6FAPOb/VjwJtzBlIv3205J+0= ARC-Authentication-Results: i=1; server2.sourceware.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=xry111.site; s=default; t=1707069689; bh=xoneVYMnudt0sgebgecHS+WkrK+tqCFgUxjENzEkN8s=; h=From:To:Cc:Subject:Date:From; b=gIOl3sMKKSh5GojugWZidLdarP9a47DEeSljO7nP1UHATfPwOKL615FEzU76KVmNw oA4wysc5EmrkU2orSqPd+3W7ffZfxpnZFnoC6QsctZSibg3PFlmcUyba9twd/VTXhB mZbTfMBgHInY9t1hfIHUn8YFq0ZaQUPeykfbdjSY= Received: from stargazer.. (unknown [IPv6:240e:358:11d0:200:dc73:854d:832e:8]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (P-384) server-digest SHA384) (Client did not present a certificate) (Authenticated sender: xry111@xry111.site) by xry111.site (Postfix) with ESMTPSA id 0760866BE1; Sun, 4 Feb 2024 13:01:26 -0500 (EST) From: Xi Ruoyao To: gcc-patches@gcc.gnu.org Cc: YunQiang Su , Jeff Law , Xi Ruoyao Subject: [PATCH] MIPS: Fix wrong MSA FP vector negation Date: Mon, 5 Feb 2024 02:00:37 +0800 Message-ID: <20240204180106.468674-1-xry111@xry111.site> X-Mailer: git-send-email 2.43.0 MIME-Version: 1.0 X-Spam-Status: No, score=-9.1 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, LIKELY_SPAM_FROM, SPF_HELO_PASS, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1789992349467974653 X-GMAIL-MSGID: 1789992349467974653 We expanded (neg x) to (minus const0 x) for MSA FP vectors, this is wrong because -0.0 is not 0 - 0.0. This causes some Python tests to fail when Python is built with MSA enabled. Use the bnegi.df instructions to simply reverse the sign bit instead. gcc/ChangeLog: * config/mips/mips-msa.md (elmsgnbit): New define_mode_attr. (neg2): Change the mode iterator from MSA to IMSA because in FP arithmetic we cannot use (0 - x) for -x. (neg2): New define_insn to implement FP vector negation, using a bnegi instruction to negate the sign bit. --- Bootstrapped and regtested on mips64el-linux-gnuabi64. Ok for trunk and/or release branches? gcc/config/mips/mips-msa.md | 18 +++++++++++++++--- 1 file changed, 15 insertions(+), 3 deletions(-) diff --git a/gcc/config/mips/mips-msa.md b/gcc/config/mips/mips-msa.md index 83d9a08e360..920161ed1d8 100644 --- a/gcc/config/mips/mips-msa.md +++ b/gcc/config/mips/mips-msa.md @@ -231,6 +231,10 @@ (define_mode_attr bitimm (V4SI "uimm5") (V2DI "uimm6")]) +;; The index of sign bit in FP vector elements. +(define_mode_attr elmsgnbit [(V2DF "63") (V4DF "63") + (V4SF "31") (V8SF "31")]) + (define_expand "vec_init" [(match_operand:MSA 0 "register_operand") (match_operand:MSA 1 "")] @@ -597,9 +601,9 @@ (define_expand "abs2" }) (define_expand "neg2" - [(set (match_operand:MSA 0 "register_operand") - (minus:MSA (match_dup 2) - (match_operand:MSA 1 "register_operand")))] + [(set (match_operand:IMSA 0 "register_operand") + (minus:IMSA (match_dup 2) + (match_operand:IMSA 1 "register_operand")))] "ISA_HAS_MSA" { rtx reg = gen_reg_rtx (mode); @@ -607,6 +611,14 @@ (define_expand "neg2" operands[2] = reg; }) +(define_insn "neg2" + [(set (match_operand:FMSA 0 "register_operand" "=f") + (neg (match_operand:FMSA 1 "register_operand" "f")))] + "ISA_HAS_MSA" + "bnegi.\t%w0,%w1," + [(set_attr "type" "simd_bit") + (set_attr "mode" "")]) + (define_expand "msa_ldi" [(match_operand:IMSA 0 "register_operand") (match_operand 1 "const_imm10_operand")]