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Thu, 01 Feb 2024 00:18:42 +0000 (GMT) Received: from nasanex01c.na.qualcomm.com (nasanex01c.na.qualcomm.com [10.45.79.139]) by NASANPPMTA01.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 4110If1G010565 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT) for ; Thu, 1 Feb 2024 00:18:41 GMT Received: from hu-apinski-lv.qualcomm.com (10.49.16.6) by nasanex01c.na.qualcomm.com (10.45.79.139) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.40; Wed, 31 Jan 2024 16:18:41 -0800 From: Andrew Pinski To: CC: Andrew Pinski Subject: [COMMITTEDv2] aarch64: -mstrict-align vs __arm_data512_t [PR113657] Date: Wed, 31 Jan 2024 16:18:26 -0800 Message-ID: <20240201001826.3648577-1-quic_apinski@quicinc.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 X-Originating-IP: [10.49.16.6] X-ClientProxiedBy: nalasex01c.na.qualcomm.com (10.47.97.35) To nasanex01c.na.qualcomm.com (10.45.79.139) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: wByAAkooltVenZ4jGRx13oG3TIx0gaIo X-Proofpoint-ORIG-GUID: wByAAkooltVenZ4jGRx13oG3TIx0gaIo X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.1011,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2024-01-31_10,2024-01-31_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 mlxscore=0 malwarescore=0 spamscore=0 clxscore=1011 impostorscore=0 bulkscore=0 mlxlogscore=662 suspectscore=0 lowpriorityscore=0 priorityscore=1501 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2401190000 definitions=main-2402010000 X-Spam-Status: No, score=-13.3 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, KAM_SHORT, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1789653722726963131 X-GMAIL-MSGID: 1789653722726963131 After r14-1187-gd6b756447cd58b, simplify_gen_subreg can return NULL for "unaligned" memory subreg. Since V8DI has an alignment of 8 bytes, using TImode causes simplify_gen_subreg to return NULL. This fixes the issue by using DImode instead for the loop. And then we will have later on the STP/LDP pass combine it back into STP/LDP if needed. Since strict align is less important (usually used for firmware and early boot only), not doing LDP/STP here is ok. Built and tested for aarch64-linux-gnu with no regressions. PR target/113657 gcc/ChangeLog: * config/aarch64/aarch64-simd.md (split for movv8di): For strict aligned mode, use DImode instead of TImode. gcc/testsuite/ChangeLog: * gcc.target/aarch64/acle/ls64_strict_align.c: New test. Signed-off-by: Andrew Pinski --- gcc/config/aarch64/aarch64-simd.md | 11 +++++++---- .../gcc.target/aarch64/acle/ls64_strict_align.c | 7 +++++++ 2 files changed, 14 insertions(+), 4 deletions(-) create mode 100644 gcc/testsuite/gcc.target/aarch64/acle/ls64_strict_align.c diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md index 7a6b4430112..4023b918882 100644 --- a/gcc/config/aarch64/aarch64-simd.md +++ b/gcc/config/aarch64/aarch64-simd.md @@ -8221,14 +8221,17 @@ (define_split || (memory_operand (operands[0], V8DImode) && register_operand (operands[1], V8DImode))) { + /* V8DI only guarantees 8-byte alignment, whereas TImode requires 16. */ + auto mode = STRICT_ALIGNMENT ? DImode : TImode; + int increment = GET_MODE_SIZE (mode); std::pair last_pair = {}; - for (int offset = 0; offset < 64; offset += 16) + for (int offset = 0; offset < 64; offset += increment) { std::pair pair = { - simplify_gen_subreg (TImode, operands[0], V8DImode, offset), - simplify_gen_subreg (TImode, operands[1], V8DImode, offset) + simplify_gen_subreg (mode, operands[0], V8DImode, offset), + simplify_gen_subreg (mode, operands[1], V8DImode, offset) }; - if (register_operand (pair.first, TImode) + if (register_operand (pair.first, mode) && reg_overlap_mentioned_p (pair.first, pair.second)) last_pair = pair; else diff --git a/gcc/testsuite/gcc.target/aarch64/acle/ls64_strict_align.c b/gcc/testsuite/gcc.target/aarch64/acle/ls64_strict_align.c new file mode 100644 index 00000000000..bf49ac76f78 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/acle/ls64_strict_align.c @@ -0,0 +1,7 @@ +/* { dg-do compile } */ +/* { dg-options "-mstrict-align" } */ +/* PR target/113657 */ + +#pragma GCC target "+ls64" +#pragma GCC aarch64 "arm_acle.h" +__arm_data512_t foo(__arm_data512_t* ptr) { return *ptr; }