From patchwork Wed Jan 31 19:06:26 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Edwin Lu X-Patchwork-Id: 194909 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7301:2087:b0:106:209c:c626 with SMTP id gs7csp2102215dyb; Wed, 31 Jan 2024 11:07:39 -0800 (PST) X-Google-Smtp-Source: AGHT+IGuxJHJgN6oM/WtJmqB5+Ucds1QjMEkBxjGRwVUR8+OhBGt2d6PmRcy/OrA+i33wkktJeLW X-Received: by 2002:a05:620a:6603:b0:783:fca6:e3de with SMTP id qf3-20020a05620a660300b00783fca6e3demr321099qkn.11.1706728059702; Wed, 31 Jan 2024 11:07:39 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1706728059; cv=pass; d=google.com; s=arc-20160816; b=ZrtXDjUF6HaorNHewYZiLK5rJSTCTAcxEJ+lAI53lW/49OEjxYALNu5jqHq/audPFh CVtpZhEAUYLtAFxoy9mDj5lMkNIdVCoYD9fiOmWBbJIz+kb+YCmR6md2BxybkagvK/Ao FlKORxTWH5lIjn5tGzYQCb9LB++Ki4AL9c57rq2101Gjm7zgBL5EQJnGueNC/r6DtcnB Jiozmd4t9i5kLAYAzhfKd51Q4qdsOZqa7BS8jIOt9PYqszcObGVbBTQnQeZTieilmbFq WBaoFvUVDGx7jZKSkmC7ZvCjeI5NtKzzQ5JGbBgzH2EfOKfXgPW2pS6j2ylB9xlryuMv sZFw== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:message-id:date:subject:cc:to:from:dkim-signature :arc-filter:dmarc-filter:delivered-to; bh=0/F2IhtwQvmvs9sIJkoNHCdKk3ocfiUFkqbYPw2ePLg=; fh=JK0u7av6vTe5DLIOj12NBsFE1WS2ByAg21H3GJnm0es=; b=NtzzAt8w2C8nVFyuFRodwx6+84lEqrqsvYqGomHdKEni+9BOUuFPsFLDhwK4c5QfUz c0LIckQLjNT/AZWzr0MDkVuWvjcNyv5yRAh9IlbP23R1CwbbJTqehS1lXeoKUli6VYRm ZpRt+qe5jI0NN8WAnFtp+KkjL/XecIokcm53bmNKn7XASZCzGLNdQKGHohhBz8W0RzRr 4YUGfhwA9cIdx1ndar4kC0HyPJKttc05xCzlMvmxzlhS98d6822RvxMF1ws9STLxBZhk aUqYBs9V2euq2ralgIgr1ZYkHMoNJ44pi7VYVt0WCUCEJWsOjD3OYPvszQUqlJfm5A3o wOZg==; dara=google.com ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@rivosinc-com.20230601.gappssmtp.com header.s=20230601 header.b=qSbGdho1; arc=pass (i=1); spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org" X-Forwarded-Encrypted: i=1; AJvYcCV3yRenLOfSByYfB7Ef97TQzGzEkL0Jw+LmEJBjRjqPYMpETcY8FHJWDHYKtd46P/1P3usrxpmR5BN4i+nmqkbWBZyKIA== Received: from server2.sourceware.org (server2.sourceware.org. [2620:52:3:1:0:246e:9693:128c]) by mx.google.com with ESMTPS id f29-20020a05620a20dd00b00783f449f594si8955691qka.736.2024.01.31.11.07.39 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 31 Jan 2024 11:07:39 -0800 (PST) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) client-ip=2620:52:3:1:0:246e:9693:128c; Authentication-Results: mx.google.com; dkim=pass header.i=@rivosinc-com.20230601.gappssmtp.com header.s=20230601 header.b=qSbGdho1; arc=pass (i=1); spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org" Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id C79D53858008 for ; Wed, 31 Jan 2024 19:07:38 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mail-pl1-x629.google.com (mail-pl1-x629.google.com [IPv6:2607:f8b0:4864:20::629]) by sourceware.org (Postfix) with ESMTPS id 4FC1C3858C78 for ; Wed, 31 Jan 2024 19:06:43 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 4FC1C3858C78 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=rivosinc.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=rivosinc.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 4FC1C3858C78 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=2607:f8b0:4864:20::629 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1706728008; cv=none; b=abaHwtu5d/ZIuj7OsJSyIoxBRK59+6BhlwAongvVdKqw47EW3+Je7EfNdZPW5xBwk0hqc6sqUOIMlV+PEbuhzxNt7NIM8T9poeIYRCpQ/qx8kZU4/IOHnvtc58B4yfO+cTey9vlZPEmaSqHpPwoI2Z7lrOgbP1XA+2CUrij9Qq8= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1706728008; c=relaxed/simple; bh=lmN+Qw1IdZ6XZVRzRGv+gPL0ssf9gcTZPAXXdT4XJo0=; h=DKIM-Signature:From:To:Subject:Date:Message-Id:MIME-Version; b=EEhngtnf0VaLTFkBOa1Vuxva/OHcooKzm0pF3WJWHWFCQJLDqIrr0FCAdTYxQ9O07tNkY8F0GhlJlBhl4xdO1KOqXIm4jgBYPAaLeauJ+uUGsk3QCflvOzMUxE4nOnO2/b0P7aZW8l0iftnj1ZiIX1S9p4JtqoGmadxcZhgy6CY= ARC-Authentication-Results: i=1; server2.sourceware.org Received: by mail-pl1-x629.google.com with SMTP id d9443c01a7336-1d928a8dee8so8288415ad.1 for ; Wed, 31 Jan 2024 11:06:43 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1706728002; x=1707332802; darn=gcc.gnu.org; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:from:to:cc:subject:date:message-id:reply-to; bh=0/F2IhtwQvmvs9sIJkoNHCdKk3ocfiUFkqbYPw2ePLg=; b=qSbGdho1tXYAzIwPLpy+NbOPjRZFTxqeV5S7N02RKBVYrTOcjdOEr94gky2KCydmGm JQ+iJkmngIL3x31859yu/9rNHcqw/qZ14xv+3cJN9FddSnJ6Tb9ZvQDQsttUsF1U0IzP vsj5wYWNMc7XjuONVpmxRuwVeA4chFSPPRjHc2H5eY1m0Lj6xFXjem0aHMpEW2W00yd3 T5/He2DWlmSmj/A+FivGO2qH+Wly+ZZPXx+Ks8uuIkzzG1JvPN2XMbZfnfh8J/9Qglhx W1sQT5jBU8D8Z6hM0bO4r17gqd5hLJVe2MJk7aYhnZJsMrdfisyIP+cIDNtDtKHFRnze lcJA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1706728002; x=1707332802; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=0/F2IhtwQvmvs9sIJkoNHCdKk3ocfiUFkqbYPw2ePLg=; b=cskhahmhRXImkzqWYBisxp5M9qCHDlkHeQ2iZXK7pg1JTzhNdJEJN679yEfk+GC8GW 1fUiv++wy+mXa0OLQY9hgb2DLsfTNgiiJuYgkSbAMDXZ2ty/DU38OkYgRnyyVESRJTfE U/h2iT3PIqYxGSxfpxrp4wzsla6qYrRiijoo5f5UqeSoQ1/CWGc9VvsL5uloTWWaNqLe djJBwq7Bz3d8WnEdg+JDC/93jnH7F3qcrTf7A90s/S/ZbXGio5qSrXo1kSF5RZJIf5NO jIQrX0sguoCzdYQPfrNxzv5PfrKJNifosq9XcCQAEmo1pVLkA5sZbZImzo5LYmtmW5UQ 88fA== X-Gm-Message-State: AOJu0YzK+e37QtuHsJwn/ctOFFgDdYCLTyHR3J0zcNmzlFUJTtOWiKc1 zIS8swUAtM1S2H5XAw/vU2wWn3/YH55HMp6i+Xkm8d5RoZ5MYLfdQ2K2TEUNUfOCfU9SLlprs7H R X-Received: by 2002:a17:90b:1495:b0:296:96d:afae with SMTP id js21-20020a17090b149500b00296096dafaemr218364pjb.26.1706728001853; Wed, 31 Jan 2024 11:06:41 -0800 (PST) X-Forwarded-Encrypted: i=0; AJvYcCX18+koVbOzpaHQu8TdlVOWcxf69hKtH0YTAyU5L0I8NOBuKVPitQhuXXDdngdTK4FwE+wP1ggocjYm9bUfHBc+VmSwz4S3kBCB4XGeJCmDJ9SifQDJ6g== Received: from ewlu.ba.rivosinc.com ([64.71.180.162]) by smtp.gmail.com with ESMTPSA id r144-20020a632b96000000b005c21943d571sm4176624pgr.55.2024.01.31.11.06.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 31 Jan 2024 11:06:41 -0800 (PST) From: Edwin Lu To: gcc-patches@gcc.gnu.org Cc: gnu-toolchain@rivosinc.com, Edwin Lu , Robin Dapp Subject: [PATCH V4 2/4] RISC-V: Add vector related pipelines Date: Wed, 31 Jan 2024 11:06:26 -0800 Message-Id: <20240131190626.261379-1-ewlu@rivosinc.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 X-Spam-Status: No, score=-12.1 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, GIT_PATCH_0, KAM_SHORT, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1789634081898702621 X-GMAIL-MSGID: 1789634081898702621 Creates new generic vector pipeline file common to all cpu tunes. Moves all vector related pipelines from generic-ooo to generic-vector-ooo. Creates new vector crypto related insn reservations. gcc/ChangeLog: * config/riscv/generic-ooo.md (generic_ooo): Move reservation (generic_ooo_vec_load): ditto (generic_ooo_vec_store): ditto (generic_ooo_vec_loadstore_seg): ditto (generic_ooo_vec_alu): ditto (generic_ooo_vec_fcmp): ditto (generic_ooo_vec_imul): ditto (generic_ooo_vec_fadd): ditto (generic_ooo_vec_fmul): ditto (generic_ooo_crypto): ditto (generic_ooo_perm): ditto (generic_ooo_vec_reduction): ditto (generic_ooo_vec_ordered_reduction): ditto (generic_ooo_vec_idiv): ditto (generic_ooo_vec_float_divsqrt): ditto (generic_ooo_vec_mask): ditto (generic_ooo_vec_vesetvl): ditto (generic_ooo_vec_setrm): ditto (generic_ooo_vec_readlen): ditto * config/riscv/riscv.md: include generic-vector-ooo * config/riscv/generic-vector-ooo.md: New file. to here Signed-off-by: Edwin Lu Co-authored-by: Robin Dapp --- V2: - Remove unnecessary syntax changes in generic-ooo - Add new vector crypto reservations and types to pipelines V3: - Move all vector pipelines into separate file which defines all ooo vector reservations. - Add temporary attribute while cost model changes. V4: - Remove temporary attribute --- gcc/config/riscv/generic-ooo.md | 127 +--------------------- gcc/config/riscv/generic-vector-ooo.md | 143 +++++++++++++++++++++++++ gcc/config/riscv/riscv.md | 1 + 3 files changed, 145 insertions(+), 126 deletions(-) create mode 100644 gcc/config/riscv/generic-vector-ooo.md diff --git a/gcc/config/riscv/generic-ooo.md b/gcc/config/riscv/generic-ooo.md index ef8cb96daf4..4e8297bf96f 100644 --- a/gcc/config/riscv/generic-ooo.md +++ b/gcc/config/riscv/generic-ooo.md @@ -1,5 +1,5 @@ ;; RISC-V generic out-of-order core scheduling model. -;; Copyright (C) 2017-2024 Free Software Foundation, Inc. +;; Copyright (C) 2023-2024 Free Software Foundation, Inc. ;; ;; This file is part of GCC. ;; @@ -48,9 +48,6 @@ (define_automaton "generic_ooo") ;; Integer/float issue queues. (define_cpu_unit "issue0,issue1,issue2,issue3,issue4" "generic_ooo") -;; Separate issue queue for vector instructions. -(define_cpu_unit "generic_ooo_vxu_issue" "generic_ooo") - ;; Integer/float execution units. (define_cpu_unit "ixu0,ixu1,ixu2,ixu3" "generic_ooo") (define_cpu_unit "fxu0,fxu1" "generic_ooo") @@ -58,12 +55,6 @@ (define_cpu_unit "fxu0,fxu1" "generic_ooo") ;; Integer subunit for division. (define_cpu_unit "generic_ooo_div" "generic_ooo") -;; Vector execution unit. -(define_cpu_unit "generic_ooo_vxu_alu" "generic_ooo") - -;; Vector subunit that does mult/div/sqrt. -(define_cpu_unit "generic_ooo_vxu_multicycle" "generic_ooo") - ;; Shortcuts (define_reservation "generic_ooo_issue" "issue0|issue1|issue2|issue3|issue4") (define_reservation "generic_ooo_ixu_alu" "ixu0|ixu1|ixu2|ixu3") @@ -92,25 +83,6 @@ (define_insn_reservation "generic_ooo_float_store" 6 (eq_attr "type" "fpstore")) "generic_ooo_issue,generic_ooo_fxu") -;; Vector load/store -(define_insn_reservation "generic_ooo_vec_load" 6 - (and (eq_attr "tune" "generic_ooo") - (eq_attr "type" "vlde,vldm,vlds,vldux,vldox,vldff,vldr")) - "generic_ooo_vxu_issue,generic_ooo_vxu_alu") - -(define_insn_reservation "generic_ooo_vec_store" 6 - (and (eq_attr "tune" "generic_ooo") - (eq_attr "type" "vste,vstm,vsts,vstux,vstox,vstr")) - "generic_ooo_vxu_issue,generic_ooo_vxu_alu") - -;; Vector segment loads/stores. -(define_insn_reservation "generic_ooo_vec_loadstore_seg" 10 - (and (eq_attr "tune" "generic_ooo") - (eq_attr "type" "vlsegde,vlsegds,vlsegdux,vlsegdox,vlsegdff,\ - vssegte,vssegts,vssegtux,vssegtox")) - "generic_ooo_vxu_issue,generic_ooo_vxu_alu") - - ;; Generic integer instructions. (define_insn_reservation "generic_ooo_alu" 1 (and (eq_attr "tune" "generic_ooo") @@ -191,103 +163,6 @@ (define_insn_reservation "generic_ooo_popcount" 2 (eq_attr "type" "cpop,clmul")) "generic_ooo_issue,generic_ooo_ixu_alu") -;; Regular vector operations and integer comparisons. -(define_insn_reservation "generic_ooo_vec_alu" 3 - (and (eq_attr "tune" "generic_ooo") - (eq_attr "type" "vialu,viwalu,vext,vicalu,vshift,vnshift,viminmax,vicmp,\ - vimov,vsalu,vaalu,vsshift,vnclip,vmov,vfmov,vector")) - "generic_ooo_vxu_issue,generic_ooo_vxu_alu") - -;; Vector float comparison, conversion etc. -(define_insn_reservation "generic_ooo_vec_fcmp" 3 - (and (eq_attr "tune" "generic_ooo") - (eq_attr "type" "vfrecp,vfminmax,vfcmp,vfsgnj,vfclass,vfcvtitof,\ - vfcvtftoi,vfwcvtitof,vfwcvtftoi,vfwcvtftof,vfncvtitof,\ - vfncvtftoi,vfncvtftof")) - "generic_ooo_vxu_issue,generic_ooo_vxu_alu") - -;; Vector integer multiplication. -(define_insn_reservation "generic_ooo_vec_imul" 4 - (and (eq_attr "tune" "generic_ooo") - (eq_attr "type" "vimul,viwmul,vimuladd,viwmuladd,vsmul")) - "generic_ooo_vxu_issue,generic_ooo_vxu_alu") - -;; Vector float addition. -(define_insn_reservation "generic_ooo_vec_fadd" 4 - (and (eq_attr "tune" "generic_ooo") - (eq_attr "type" "vfalu,vfwalu")) - "generic_ooo_vxu_issue,generic_ooo_vxu_alu") - -;; Vector float multiplication and FMA. -(define_insn_reservation "generic_ooo_vec_fmul" 6 - (and (eq_attr "tune" "generic_ooo") - (eq_attr "type" "vfmul,vfwmul,vfmuladd,vfwmuladd")) - "generic_ooo_vxu_issue,generic_ooo_vxu_alu") - -;; Vector crypto, assumed to be a generic operation for now. -(define_insn_reservation "generic_ooo_crypto" 4 - (and (eq_attr "tune" "generic_ooo") - (eq_attr "type" "crypto")) - "generic_ooo_vxu_issue,generic_ooo_vxu_alu") - -;; Vector permute. -(define_insn_reservation "generic_ooo_perm" 3 - (and (eq_attr "tune" "generic_ooo") - (eq_attr "type" "vimerge,vfmerge,vslideup,vslidedown,vislide1up,\ - vislide1down,vfslide1up,vfslide1down,vgather,vcompress")) - "generic_ooo_vxu_issue,generic_ooo_vxu_alu") - -;; Vector reduction. -(define_insn_reservation "generic_ooo_vec_reduction" 8 - (and (eq_attr "tune" "generic_ooo") - (eq_attr "type" "vired,viwred,vfredu,vfwredu")) - "generic_ooo_vxu_issue,generic_ooo_vxu_multicycle") - -;; Vector ordered reduction, assume the latency number is for -;; a 128-bit vector. It is scaled in riscv_sched_adjust_cost -;; for larger vectors. -(define_insn_reservation "generic_ooo_vec_ordered_reduction" 10 - (and (eq_attr "tune" "generic_ooo") - (eq_attr "type" "vfredo,vfwredo")) - "generic_ooo_vxu_issue,generic_ooo_vxu_multicycle*3") - -;; Vector integer division, assume not pipelined. -(define_insn_reservation "generic_ooo_vec_idiv" 16 - (and (eq_attr "tune" "generic_ooo") - (eq_attr "type" "vidiv")) - "generic_ooo_vxu_issue,generic_ooo_vxu_multicycle*3") - -;; Vector float divisions and sqrt, assume not pipelined. -(define_insn_reservation "generic_ooo_vec_float_divsqrt" 16 - (and (eq_attr "tune" "generic_ooo") - (eq_attr "type" "vfdiv,vfsqrt")) - "generic_ooo_vxu_issue,generic_ooo_vxu_multicycle*3") - -;; Vector mask operations. -(define_insn_reservation "generic_ooo_vec_mask" 2 - (and (eq_attr "tune" "generic_ooo") - (eq_attr "type" "vmalu,vmpop,vmffs,vmsfs,vmiota,vmidx,vimovvx,vimovxv,\ - vfmovvf,vfmovfv")) - "generic_ooo_vxu_issue,generic_ooo_vxu_alu") - -;; Vector vsetvl. -(define_insn_reservation "generic_ooo_vec_vesetvl" 1 - (and (eq_attr "tune" "generic_ooo") - (eq_attr "type" "vsetvl,vsetvl_pre")) - "generic_ooo_vxu_issue") - -;; Vector rounding mode setters, assume pipeline barrier. -(define_insn_reservation "generic_ooo_vec_setrm" 20 - (and (eq_attr "tune" "generic_ooo") - (eq_attr "type" "wrvxrm,wrfrm")) - "generic_ooo_vxu_issue,generic_ooo_vxu_issue*3") - -;; Vector read vlen/vlenb. -(define_insn_reservation "generic_ooo_vec_readlen" 4 - (and (eq_attr "tune" "generic_ooo") - (eq_attr "type" "rdvlenb,rdvl")) - "generic_ooo_vxu_issue,generic_ooo_vxu_issue") - ;; Transfer from/to coprocessor. Assume not pipelined. (define_insn_reservation "generic_ooo_xfer" 4 (and (eq_attr "tune" "generic_ooo") diff --git a/gcc/config/riscv/generic-vector-ooo.md b/gcc/config/riscv/generic-vector-ooo.md new file mode 100644 index 00000000000..96cb1a0be29 --- /dev/null +++ b/gcc/config/riscv/generic-vector-ooo.md @@ -0,0 +1,143 @@ +;; Copyright (C) 2024-2024 Free Software Foundation, Inc. + +;; This file is part of GCC. + +;; GCC is free software; you can redistribute it and/or modify it +;; under the terms of the GNU General Public License as published +;; by the Free Software Foundation; either version 3, or (at your +;; option) any later version. + +;; GCC is distributed in the hope that it will be useful, but WITHOUT +;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY +;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public +;; License for more details. + +;; You should have received a copy of the GNU General Public License +;; along with GCC; see the file COPYING3. If not see +;; . +;; Vector load/store + +(define_automaton "vector_ooo") + +;; Separate issue queue for vector instructions. +(define_cpu_unit "vxu_ooo_issue" "vector_ooo") + +;; Vector execution unit. +(define_cpu_unit "vxu_ooo_alu" "vector_ooo") + +;; Vector subunit that does mult/div/sqrt. +(define_cpu_unit "vxu_ooo_multicycle" "vector_ooo") + +(define_insn_reservation "vec_load" 6 + (eq_attr "type" "vlde,vldm,vlds,vldux,vldox,vldff,vldr") + "vxu_ooo_issue,vxu_ooo_alu") + +(define_insn_reservation "vec_store" 6 + (eq_attr "type" "vste,vstm,vsts,vstux,vstox,vstr") + "vxu_ooo_issue,vxu_ooo_alu") + +;; Vector segment loads/stores. +(define_insn_reservation "vec_loadstore_seg" 10 + (eq_attr "type" "vlsegde,vlsegds,vlsegdux,vlsegdox,vlsegdff,\ + vssegte,vssegts,vssegtux,vssegtox") + "vxu_ooo_issue,vxu_ooo_alu") + +;; Regular vector operations and integer comparisons. +(define_insn_reservation "vec_alu" 3 + (eq_attr "type" "vialu,viwalu,vext,vicalu,vshift,vnshift,viminmax,vicmp,\ + vimov,vsalu,vaalu,vsshift,vnclip,vmov,vfmov,vector,\ + vandn,vbrev,vbrev8,vrev8,vclz,vctz,vrol,vror,vwsll") + "vxu_ooo_issue,vxu_ooo_alu") + +;; Vector float comparison, conversion etc. +(define_insn_reservation "vec_fcmp" 3 + (eq_attr "type" "vfrecp,vfminmax,vfcmp,vfsgnj,vfclass,vfcvtitof,\ + vfcvtftoi,vfwcvtitof,vfwcvtftoi,vfwcvtftof,vfncvtitof,\ + vfncvtftoi,vfncvtftof") + "vxu_ooo_issue,vxu_ooo_alu") + +;; Vector integer multiplication. +(define_insn_reservation "vec_imul" 4 + (eq_attr "type" "vimul,viwmul,vimuladd,viwmuladd,vsmul,vclmul,vclmulh,\ + vghsh,vgmul") + "vxu_ooo_issue,vxu_ooo_alu") + +;; Vector float addition. +(define_insn_reservation "vec_fadd" 4 + (eq_attr "type" "vfalu,vfwalu") + "vxu_ooo_issue,vxu_ooo_alu") + +;; Vector float multiplication and FMA. +(define_insn_reservation "vec_fmul" 6 + (eq_attr "type" "vfmul,vfwmul,vfmuladd,vfwmuladd") + "vxu_ooo_issue,vxu_ooo_alu") + +;; Vector crypto, assumed to be a generic operation for now. +(define_insn_reservation "vec_crypto" 4 + (eq_attr "type" "crypto") + "vxu_ooo_issue,vxu_ooo_alu") + +;; Vector crypto, AES +(define_insn_reservation "vec_crypto_aes" 4 + (eq_attr "type" "vaesef,vaesem,vaesdf,vaesdm,vaeskf1,vaeskf2,vaesz") + "vxu_ooo_issue,vxu_ooo_alu") + +;; Vector crypto, sha +(define_insn_reservation "vec_crypto_sha" 4 + (eq_attr "type" "vsha2ms,vsha2ch,vsha2cl") + "vxu_ooo_issue,vxu_ooo_alu") + +;; Vector crypto, SM3/4 +(define_insn_reservation "vec_crypto_sm" 4 + (eq_attr "type" "vsm4k,vsm4r,vsm3me,vsm3c") + "vxu_ooo_issue,vxu_ooo_alu") + +;; Vector permute. +(define_insn_reservation "vec_perm" 3 + (eq_attr "type" "vimerge,vfmerge,vslideup,vslidedown,vislide1up,\ + vislide1down,vfslide1up,vfslide1down,vgather,vcompress") + "vxu_ooo_issue,vxu_ooo_alu") + +;; Vector reduction. +(define_insn_reservation "vec_reduction" 8 + (eq_attr "type" "vired,viwred,vfredu,vfwredu") + "vxu_ooo_issue,vxu_ooo_multicycle") + +;; Vector ordered reduction, assume the latency number is for +;; a 128-bit vector. It is scaled in riscv_sched_adjust_cost +;; for larger vectors. +(define_insn_reservation "vec_ordered_reduction" 10 + (eq_attr "type" "vfredo,vfwredo") + "vxu_ooo_issue,vxu_ooo_multicycle*3") + +;; Vector integer division, assume not pipelined. +(define_insn_reservation "vec_idiv" 16 + (eq_attr "type" "vidiv") + "vxu_ooo_issue,vxu_ooo_multicycle*3") + +;; Vector float divisions and sqrt, assume not pipelined. +(define_insn_reservation "vec_float_divsqrt" 16 + (eq_attr "type" "vfdiv,vfsqrt") + "vxu_ooo_issue,vxu_ooo_multicycle*3") + +;; Vector mask operations. +(define_insn_reservation "vec_mask" 2 + (eq_attr "type" "vmalu,vmpop,vmffs,vmsfs,vmiota,vmidx,vimovvx,vimovxv,\ + vfmovvf,vfmovfv") + "vxu_ooo_issue,vxu_ooo_alu") + +;; Vector vsetvl. +(define_insn_reservation "vec_vesetvl" 1 + (eq_attr "type" "vsetvl,vsetvl_pre") + "vxu_ooo_issue") + +;; Vector rounding mode setters, assume pipeline barrier. +(define_insn_reservation "vec_setrm" 20 + (eq_attr "type" "wrvxrm,wrfrm") + "vxu_ooo_issue,vxu_ooo_issue*3") + +;; Vector read vlen/vlenb. +(define_insn_reservation "vec_readlen" 4 + (eq_attr "type" "rdvlenb,rdvl") + "vxu_ooo_issue,vxu_ooo_issue") + diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md index 474fd37c1e2..02786fccac6 100644 --- a/gcc/config/riscv/riscv.md +++ b/gcc/config/riscv/riscv.md @@ -3847,6 +3847,7 @@ (define_insn "*large_load_address" (include "generic.md") (include "sifive-7.md") (include "thead.md") +(include "generic-vector-ooo.md") (include "generic-ooo.md") (include "vector.md") (include "vector-crypto.md")