diff mbox series

RISC-V: Add require-effective-target to pr113429 testcase

Message ID 20240127025016.246199-1-patrick@rivosinc.com
State Unresolved
Headers
Series RISC-V: Add require-effective-target to pr113429 testcase |

Checks

Context Check Description
snail/gcc-patch-check warning Git am fail log

Commit Message

Patrick O'Neill Jan. 27, 2024, 2:50 a.m. UTC 
  The pr113429 testcase fails with newlib spike runs. Adding
require-effective-target rv64 and riscv_v fixes the issue.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/rvv/vsetvl/pr113429.c: Add
	require-effective-target rv64 and riscv_v

Signed-off-by: Patrick O'Neill <patrick@rivosinc.com>
---
Tested using rv64gc newlib spike.
---
 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr113429.c | 2 ++
 1 file changed, 2 insertions(+)

Comments

juzhe.zhong@rivai.ai Jan. 29, 2024, 3:41 a.m. UTC | #1 
ok




juzhe.zhong@rivai.ai
 
From: Patrick O'Neill
Date: 2024-01-27 10:50
To: gcc-patches
CC: juzhe.zhong; Patrick O'Neill
Subject: [PATCH] RISC-V: Add require-effective-target to pr113429 testcase
The pr113429 testcase fails with newlib spike runs. Adding
require-effective-target rv64 and riscv_v fixes the issue.
 
gcc/testsuite/ChangeLog:
 
* gcc.target/riscv/rvv/vsetvl/pr113429.c: Add
require-effective-target rv64 and riscv_v
 
Signed-off-by: Patrick O'Neill <patrick@rivosinc.com>
---
Tested using rv64gc newlib spike.
---
gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr113429.c | 2 ++
1 file changed, 2 insertions(+)
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr113429.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr113429.c
index 05c3eeecb94..a7f5db616d8 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr113429.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr113429.c
@@ -1,5 +1,7 @@
/* { dg-do run } */
/* { dg-options "-march=rv64gcv_zvl256b -mabi=lp64d -O3" } */
+/* { dg-require-effective-target rv64 } */
+/* { dg-require-effective-target riscv_v } */
long a;
int b, c, d, e, f, g;
-- 
2.34.1
Patrick O'Neill Jan. 29, 2024, 5:51 p.m. UTC | #2 
Committed.

Thanks for catching this.
Patrick

On 1/28/24 19:41, juzhe.zhong@rivai.ai wrote:
> ok
>
>
> ------------------------------------------------------------------------
> juzhe.zhong@rivai.ai
>
>     *From:* Patrick O'Neill <mailto:patrick@rivosinc.com>
>     *Date:* 2024-01-27 10:50
>     *To:* gcc-patches <mailto:gcc-patches@gcc.gnu.org>
>     *CC:* juzhe.zhong <mailto:juzhe.zhong@rivai.ai>; Patrick O'Neill
>     <mailto:patrick@rivosinc.com>
>     *Subject:* [PATCH] RISC-V: Add require-effective-target to
>     pr113429 testcase
>     The pr113429 testcase fails with newlib spike runs. Adding
>     require-effective-target rv64 and riscv_v fixes the issue.
>     gcc/testsuite/ChangeLog:
>     * gcc.target/riscv/rvv/vsetvl/pr113429.c: Add
>     require-effective-target rv64 and riscv_v
>     Signed-off-by: Patrick O'Neill <patrick@rivosinc.com>
>     ---
>     Tested using rv64gc newlib spike.
>     ---
>     gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr113429.c | 2 ++
>     1 file changed, 2 insertions(+)
>     diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr113429.c
>     b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr113429.c
>     index 05c3eeecb94..a7f5db616d8 100644
>     --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr113429.c
>     +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr113429.c
>     @@ -1,5 +1,7 @@
>     /* { dg-do run } */
>     /* { dg-options "-march=rv64gcv_zvl256b -mabi=lp64d -O3" } */
>     +/* { dg-require-effective-target rv64 } */
>     +/* { dg-require-effective-target riscv_v } */
>     long a;
>     int b, c, d, e, f, g;
>     -- 
>     2.34.1
>
diff mbox series

Patch

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr113429.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr113429.c
index 05c3eeecb94..a7f5db616d8 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr113429.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr113429.c
@@ -1,5 +1,7 @@ 
 /* { dg-do run } */
 /* { dg-options "-march=rv64gcv_zvl256b -mabi=lp64d -O3" } */
+/* { dg-require-effective-target rv64 } */
+/* { dg-require-effective-target riscv_v } */
 
 long a;
 int b, c, d, e, f, g;