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[59.124.168.89]) by smtp.gmail.com with ESMTPSA id kj5-20020a17090306c500b001c9db5e2929sm2710477plb.93.2024.01.19.02.08.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 19 Jan 2024 02:08:14 -0800 (PST) From: Kito Cheng To: rep.dot.nop@gmail.com, jeffreyalaw@gmail.com, rdapp.gcc@gmail.com, juzhe.zhong@rivai.ai, gcc-patches@gcc.gnu.org Cc: Kito Cheng Subject: [committed] RISC-V: Update testcase due to message update Date: Fri, 19 Jan 2024 18:08:10 +0800 Message-Id: <20240119100810.2470224-1-kito.cheng@sifive.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 X-Spam-Status: No, score=-12.8 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, KAM_SHORT, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1788513040252385122 X-GMAIL-MSGID: 1788513040252385122 gcc/testsuite/ChangeLog: * gcc.target/riscv/arch-27.c: Update scan message. * gcc.target/riscv/arch-28.c: Ditto. * gcc.target/riscv/attribute-10.c: Ditto. * gcc.target/riscv/rvv/base/big_endian-2.c: Ditto. * gcc.target/riscv/rvv/base/zvl-unimplemented-1.c: Ditto. * gcc.target/riscv/rvv/base/zvl-unimplemented-2.c: Ditto. --- gcc/testsuite/gcc.target/riscv/arch-27.c | 2 +- gcc/testsuite/gcc.target/riscv/arch-28.c | 2 +- gcc/testsuite/gcc.target/riscv/attribute-10.c | 2 +- gcc/testsuite/gcc.target/riscv/rvv/base/big_endian-2.c | 2 +- gcc/testsuite/gcc.target/riscv/rvv/base/zvl-unimplemented-1.c | 2 +- gcc/testsuite/gcc.target/riscv/rvv/base/zvl-unimplemented-2.c | 2 +- 6 files changed, 6 insertions(+), 6 deletions(-) diff --git a/gcc/testsuite/gcc.target/riscv/arch-27.c b/gcc/testsuite/gcc.target/riscv/arch-27.c index 03f07deedd1..95cebc1a2da 100644 --- a/gcc/testsuite/gcc.target/riscv/arch-27.c +++ b/gcc/testsuite/gcc.target/riscv/arch-27.c @@ -4,4 +4,4 @@ int foo() { } -/* { dg-error "'i', 'e' or 'g' must be the first extension" "" { target *-*-* } 0 } */ +/* { dg-error "i, e or g must be the first extension" "" { target *-*-* } 0 } */ diff --git a/gcc/testsuite/gcc.target/riscv/arch-28.c b/gcc/testsuite/gcc.target/riscv/arch-28.c index 0f83c03ad3d..21c748edf5c 100644 --- a/gcc/testsuite/gcc.target/riscv/arch-28.c +++ b/gcc/testsuite/gcc.target/riscv/arch-28.c @@ -4,4 +4,4 @@ int foo() { } -/* { dg-error "'i', 'e' or 'g' must be the first extension" "" { target *-*-* } 0 } */ +/* { dg-error "i, e or g must be the first extension" "" { target *-*-* } 0 } */ diff --git a/gcc/testsuite/gcc.target/riscv/attribute-10.c b/gcc/testsuite/gcc.target/riscv/attribute-10.c index 8a7f0a8ac49..4aaa2bbcd45 100644 --- a/gcc/testsuite/gcc.target/riscv/attribute-10.c +++ b/gcc/testsuite/gcc.target/riscv/attribute-10.c @@ -5,4 +5,4 @@ int foo() } /* { dg-error "extension 'u' is unsupported standard single letter extension" "" { target { "riscv*-*-*" } } 0 } */ /* { dg-error "extension 'n' is unsupported standard single letter extension" "" { target { "riscv*-*-*" } } 0 } */ -/* { dg-error "'i', 'e' or 'g' must be the first extension" "" { target { "riscv*-*-*" } } 0 } */ +/* { dg-error "i, e or g must be the first extension" "" { target { "riscv*-*-*" } } 0 } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/big_endian-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/big_endian-2.c index 86cf58370bf..45cc97e1f01 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/big_endian-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/big_endian-2.c @@ -2,4 +2,4 @@ /* { dg-options "-march=rv64gc_zve32x -mabi=lp64d -mbig-endian -O3" } */ #pragma riscv intrinsic "vector" -vint32m1_t foo (vint32m1_t) {} // { dg-excess-errors "sorry, unimplemented: Current RISC-V GCC cannot support RVV in big-endian mode" } +vint32m1_t foo (vint32m1_t) {} // { dg-excess-errors "sorry, unimplemented: Current RISC-V GCC does not support RVV in big-endian mode" } diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/zvl-unimplemented-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/zvl-unimplemented-1.c index 03f67035ca4..1912a2457c7 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/zvl-unimplemented-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/zvl-unimplemented-1.c @@ -1,4 +1,4 @@ /* { dg-do compile } */ /* { dg-options "-O3 -march=rv64gcv_zvl8192b -mabi=lp64d --param riscv-autovec-preference=fixed-vlmax" } */ -void foo () {} // { dg-excess-errors "sorry, unimplemented: Current RISC-V GCC can not support VLEN > 4096bit for 'V' Extension" } +void foo () {} // { dg-excess-errors "sorry, unimplemented: Current RISC-V GCC does not support VLEN > 4096bit for 'V' Extension" } diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/zvl-unimplemented-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/zvl-unimplemented-2.c index 075112f2f81..884e834fb90 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/zvl-unimplemented-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/zvl-unimplemented-2.c @@ -1,4 +1,4 @@ /* { dg-do compile } */ /* { dg-options "-O3 -march=rv64gcv_zvl8192b -mabi=lp64d --param riscv-autovec-preference=scalable" } */ -void foo () {} // { dg-excess-errors "sorry, unimplemented: Current RISC-V GCC can not support VLEN > 4096bit for 'V' Extension" } +void foo () {} // { dg-excess-errors "sorry, unimplemented: Current RISC-V GCC does not support VLEN > 4096bit for 'V' Extension" }