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[8.43.85.97]) by mx.google.com with ESMTPS id l14-20020a05622a050e00b00429d470ea36si12862818qtx.592.2024.01.18.23.47.45 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 18 Jan 2024 23:47:45 -0800 (PST) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) client-ip=8.43.85.97; Authentication-Results: mx.google.com; arc=pass (i=1); spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org" Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 257033858413 for ; Fri, 19 Jan 2024 07:47:45 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from azure-sdnproxy.icoremail.net (azure-sdnproxy.icoremail.net [20.231.56.155]) by sourceware.org (Postfix) with ESMTP id 708B63858C42 for ; Fri, 19 Jan 2024 07:46:58 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 708B63858C42 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=eswincomputing.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=eswincomputing.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 708B63858C42 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=20.231.56.155 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1705650420; cv=none; b=IlWzk16i79tw6sMik7DYLgnmyRtz63xMILe9f9aR+/RumN71K5Hd4ZnXpWXCSFkiKM+HSCcTTM0T6ec/G3RX6WzGUQ9+WdGSNubDXytnJRZ29+VpKnNcGgNWc/FGrgU19rrFQmTk1qxie89RCLxfijBOKgTeNZ9hGkQbnvLZC2k= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1705650420; c=relaxed/simple; bh=VhGZ+KSF/tdjyY22Y/1DBK0A/SEBJDXqSPaWg8pAHDg=; h=From:To:Subject:Date:Message-Id; b=YOUKYF8C8cxV4C4viW/Pnd2SKXCv7Se65W28GYxWKdaMPjXwtYi6pe4Iiuzn/cJpgvWE8J3Of4iQgiMeX2vkdD8o844kxVhPHs6tp+UIpZdvQ3BBw1xar8mSw1OPfmW2HGZoztuG/MK0r32RHgKXGreMBWNw2MUeI570SkaZOF0= ARC-Authentication-Results: i=1; server2.sourceware.org Received: from host014-ubuntu-1804.lxd (unknown [10.12.130.31]) by app2 (Coremail) with SMTP id TQJkCgBX5dNrKKplnNkGAA--.52517S4; Fri, 19 Jan 2024 15:44:44 +0800 (CST) From: Li Xu To: gcc-patches@gcc.gnu.org Cc: kito.cheng@gmail.com, palmer@dabbelt.com, juzhe.zhong@rivai.ai, zhengyu@eswincomputing.com, pan2.li@intel.com, xuli Subject: [PATCH] RISC-V: Bugfix for resolve_overloaded_builtin[PR113420] Date: Fri, 19 Jan 2024 07:44:59 +0000 Message-Id: <20240119074459.28976-1-xuli1@eswincomputing.com> X-Mailer: git-send-email 2.17.1 X-CM-TRANSID: TQJkCgBX5dNrKKplnNkGAA--.52517S4 X-Coremail-Antispam: 1UD129KBjvJXoWxKF1kGF13Cry3Gry8Xw1xGrg_yoWxtFyrpa 43G3y7Jr48JF43Xr1UJF48Gr1UGw4kG345J3yxJ34xAF42y3y2yF4DtFyxJFyUGry5WF1U JFyUAw4UZr4UJF7anT9S1TB71UUUUUUqnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnRJUUUk214x267AKxVW8JVW5JwAFc2x0x2IEx4CE42xK8VAvwI8IcIk0 rVWrJVCq3wAFIxvE14AKwVWUJVWUGwA2ocxC64kIII0Yj41l84x0c7CEw4AK67xGY2AK02 1l84ACjcxK6xIIjxv20xvE14v26w1j6s0DM28EF7xvwVC0I7IYx2IY6xkF7I0E14v26r4U JVWxJr1l84ACjcxK6I8E87Iv67AKxVW0oVCq3wA2z4x0Y4vEx4A2jsIEc7CjxVAFwI0_Gc CE3s1le2I262IYc4CY6c8Ij28IcVAaY2xG8wAqx4xG64xvF2IEw4CE5I8CrVC2j2WlYx0E 2Ix0cI8IcVAFwI0_Jr0_Jr4lYx0Ex4A2jsIE14v26r1j6r4UMcvjeVCFs4IE7xkEbVWUJV W8JwACjcxG0xvY0x0EwIxGrwACjI8F5VA0II8E6IAqYI8I648v4I1lc2xSY4AK6svPMxAI w28IcxkI7VAKI48JMxC20s026xCaFVCjc4AY6r1j6r4UMI8I3I0E5I8CrVAFwI0_Jr0_Jr 4lx2IqxVCjr7xvwVAFwI0_JrI_JrWlx4CE17CEb7AF67AKxVWUAVWUtwCIc40Y0x0EwIxG rwCI42IY6xIIjxv20xvE14v26r1j6r1xMIIF0xvE2Ix0cI8IcVCY1x0267AKxVWUJVW8Jw CI42IY6xAIw20EY4v20xvaj40_Jr0_JF4lIxAIcVC2z280aVAFwI0_Jr0_Gr1lIxAIcVC2 z280aVCY1x0267AKxVWUJVW8JbIYCTnIWIevJa73UjIFyTuYvjfUoOJ5UUUUU X-CM-SenderInfo: 50xoxi46hv4xpqfrz1xxwl0woofrz/ X-Spam-Status: No, score=-12.7 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_ASCII_DIVIDERS, KAM_DMARC_STATUS, KAM_SHORT, RCVD_IN_DNSWL_LOW, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1788504142785874109 X-GMAIL-MSGID: 1788504142785874109 From: xuli Change the hash value of overloaded intrinsic from considering all parameter types to: 1. Encoding vector data type 2. In order to distinguish vle8_v_i8mf8_m(vbool64_t vm, const int8_t *rs1, size_t vl) and vle8_v_u8mf8_m(vbool64_t vm, const uint8_t *rs1, size_t vl), encode the pointer type 3. In order to distinguish vfadd_vv_f32mf2_rm(vfloat32mf2_t vs2, vfloat32mf2_t vs1, size_t vl) and vfadd_vv_f32mf2(vfloat32mf2_t vs2, vfloat32mf2_t vs1, size_t vl), encode the number of parameters. The same goes for the vxrm intrinsics. PR target/113420 gcc/ChangeLog: * config/riscv/riscv-vector-builtins.cc (has_vxrm_or_frm_p): remove. (registered_function::overloaded_hash): refactor. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/base/pr113420.c: New test. --- gcc/config/riscv/riscv-vector-builtins.cc | 88 +++---------------- .../gcc.target/riscv/rvv/base/pr113420.c | 30 +++++++ 2 files changed, 43 insertions(+), 75 deletions(-) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/pr113420.c diff --git a/gcc/config/riscv/riscv-vector-builtins.cc b/gcc/config/riscv/riscv-vector-builtins.cc index 25e0b6e56de..5240f9e1f02 100644 --- a/gcc/config/riscv/riscv-vector-builtins.cc +++ b/gcc/config/riscv/riscv-vector-builtins.cc @@ -4271,24 +4271,22 @@ registered_function::overloaded_hash () const : TYPE_UNSIGNED (type); mode_p = POINTER_TYPE_P (type) ? TYPE_MODE (TREE_TYPE (type)) : TYPE_MODE (type); - h.add_int (unsigned_p); - h.add_int (mode_p); + if (POINTER_TYPE_P (type) || lookup_vector_type_attribute (type)) + { + h.add_int (unsigned_p); + h.add_int (mode_p); + } + else if (instance.base->may_require_vxrm_p () + || instance.base->may_require_frm_p ()) + { + h.add_int (argument_types.length ()); + break; + } } return h.end (); } -bool -has_vxrm_or_frm_p (function_instance &instance, const vec &arglist) -{ - if (instance.base->may_require_vxrm_p () - || (instance.base->may_require_frm_p () - && (TREE_CODE (TREE_TYPE (arglist[arglist.length () - 2])) - == INTEGER_TYPE))) - return true; - return false; -} - hashval_t registered_function::overloaded_hash (const vec &arglist) { @@ -4296,68 +4294,8 @@ registered_function::overloaded_hash (const vec &arglist) unsigned int len = arglist.length (); for (unsigned int i = 0; i < len; i++) - { - /* vint8m1_t __riscv_vget_i8m1(vint8m2_t src, size_t index); - When the user calls vget intrinsic, the __riscv_vget_i8m1(src, 1) - form is used. The compiler recognizes that the parameter index is signed - int, which is inconsistent with size_t, so the index is converted to - size_t type in order to get correct hash value. vint8m2_t - __riscv_vset(vint8m2_t dest, size_t index, vint8m1_t value); The reason - is the same as above. */ - if ((instance.base == bases::vget && (i == (len - 1))) - || ((instance.base == bases::vset - || instance.shape == shapes::crypto_vi) - && (i == (len - 2)))) - argument_types.safe_push (size_type_node); - /* Vector fixed-point arithmetic instructions requiring argument vxrm. - For example: vuint32m4_t __riscv_vaaddu(vuint32m4_t vs2, - vuint32m4_t vs1, unsigned int vxrm, size_t vl); The user calls vaaddu - intrinsic in the form of __riscv_vaaddu(vs2, vs1, 2, vl). The compiler - recognizes that the parameter vxrm is a signed int, which is inconsistent - with the parameter unsigned int vxrm declared by intrinsic, so the - parameter vxrm is converted to an unsigned int type in order to get - correct hash value. - - Vector Floating-Point Instructions requiring argument frm. - DEF_RVV_FUNCTION (vfadd, alu, full_preds, f_vvv_ops) - DEF_RVV_FUNCTION (vfadd_frm, alu_frm, full_preds, f_vvv_ops) - Taking vfadd as an example, theoretically we can add base or shape to the - hash value to distinguish whether the frm parameter is required. - vfloat32m1_t __riscv_vfadd(vfloat32m1_t vs2, float32_t rs1, size_t vl); - vfloat32m1_t __riscv_vfadd(vfloat32m1_t vs2, vfloat32m1_t vs1, unsigned int - frm, size_t vl); - - However, the current registration mechanism of overloaded intinsic for gcc - limits the intrinsic obtained by entering the hook to always be vfadd, not - vfadd_frm. Therefore, the correct hash value cannot be obtained through the - parameter list and overload name, base or shape. - +--------+---------------------------+-------------------+ - | index | name | kind | - +--------+---------------------------+-------------------+ - | 124733 | __riscv_vfadd | Overloaded | <- Hook fun code - +--------+---------------------------+-------------------+ - | 124735 | __riscv_vfadd_vv_f32m1 | Non-overloaded | - +--------+---------------------------+-------------------+ - | 124737 | __riscv_vfadd | Placeholder | - +--------+---------------------------+-------------------+ - | ... | - +--------+---------------------------+-------------------+ - | ... | - +--------+---------------------------+-------------------+ - | 125739 | __riscv_vfadd | Overloaded | - +--------+---------------------------+-------------------+ - | 125741 | __riscv_vfadd_vv_f32m1_rm | Non-overloaded | - +--------+---------------------------+-------------------+ - | 125743 | __riscv_vfadd | Placeholder | - +--------+---------------------------+-------------------+ - - Therefore, the hash value cannot be added with base or shape, and needs - to be distinguished by whether the penultimate parameter is INTEGER_TYPE. */ - else if (has_vxrm_or_frm_p (instance, arglist) && (i == (len - 2))) - argument_types.safe_push (unsigned_type_node); - else - argument_types.safe_push (TREE_TYPE (arglist[i])); - } + argument_types.safe_push (TREE_TYPE (arglist[i])); + return overloaded_hash (); } diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr113420.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr113420.c new file mode 100644 index 00000000000..d17f22804ff --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr113420.c @@ -0,0 +1,30 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3" } */ + +#include "riscv_vector.h" + +void +matrix_transpose_intrinsics (float *dst, float *src, size_t n) +{ + for (size_t row_id = 0; row_id < n; ++row_id) + { // input row-index + size_t avl = n; + // source pointer to row_id-th row + float *row_src = src + row_id * n; + // destination pointer to row_id-th column + float *row_dst = dst + row_id; + while (avl > 0) + { + size_t vl = __riscv_vsetvl_e32m1 (avl); + vfloat32m1_t row = __riscv_vle32_v_f32m1 (row_src, vl); + __riscv_vsse32 (row_dst, sizeof (float) * n, row, vl); + // updating application vector length + avl -= vl; + // updating source and destination pointers + row_src += vl; + row_dst += vl * n; + } + } +} + +/* { dg-final { scan-assembler-times {vsse32\.v} 1 } } */