diff mbox series

[v4,3/3] RISC-V: Add C intrinsic for Scalar Bitmanip Extension

Message ID 20240115083135.2120665-4-shihua@iscas.ac.cn
State Unresolved
Headers
Series RISC-V: Add intrinsics for Bitmanip and Scalar Crypto extensions |

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Context Check Description
snail/gcc-patch-check warning Git am fail log

Commit Message

Liao Shihua Jan. 15, 2024, 8:31 a.m. UTC 
  This patch adds C intrinsics for Bitmanip Extension.
RISCV_BUILTIN_NO_PREFIX is a new riscv_builtin_description like RISCV_BUILTIN.
But it uses CODE_FOR_##INSN rather than CODE_FOR_riscv_##INSN.
Changed orcb, clmul, brev8 pattern's mode form X to GPR because orcbsi, clmul_si, 
brev8_si are both included in rv32 and rv64. Test them in scalar_bitmanip_intrinsic-64-emulated.c.

gcc/ChangeLog:

        * config.gcc: Include riscv_bitmanip.h.
        * config/riscv/bitmanip.md: Changed mode form X to GPR in orcb and clmul pattern.
        * config/riscv/crypto.md: Changed mode form X to GPR in brev8 pattern.
        * config/riscv/riscv-builtins.cc (AVAIL): New AVAIL.
        (RISCV_BUILTIN_NO_PREFIX): New riscv_builtin_description.
        * config/riscv/riscv-cmo.def (RISCV_BUILTIN): New builtins.
        * config/riscv/riscv-ftypes.def (2): New ftypes.
        * config/riscv/riscv-scalar-crypto.def (RISCV_BUILTIN): New builtins.
        (RISCV_BUILTIN_NO_PREFIX): Ditto.
        * config/riscv/riscv_bitmanip.h: New file.

gcc/testsuite/ChangeLog:

        * gcc.target/riscv/scalar_bitmanip_intrinsic-32.c: New test.
        * gcc.target/riscv/scalar_bitmanip_intrinsic-64-emulated.c: New test.
        * gcc.target/riscv/scalar_bitmanip_intrinsic-64.c: New test.

---
 gcc/config.gcc                                |   2 +-
 gcc/config/riscv/bitmanip.md                  |  10 +-
 gcc/config/riscv/crypto.md                    |   4 +-
 gcc/config/riscv/riscv-builtins.cc            |  22 ++
 gcc/config/riscv/riscv-cmo.def                |  12 +-
 gcc/config/riscv/riscv-ftypes.def             |   2 +
 gcc/config/riscv/riscv-scalar-crypto.def      |  22 +-
 gcc/config/riscv/riscv_bitmanip.h             | 297 ++++++++++++++++++
 .../riscv/scalar_bitmanip_intrinsic-32.c      |  97 ++++++
 .../scalar_bitmanip_intrinsic-64-emulated.c   |  33 ++
 .../riscv/scalar_bitmanip_intrinsic-64.c      | 115 +++++++
 11 files changed, 600 insertions(+), 16 deletions(-)
 create mode 100644 gcc/config/riscv/riscv_bitmanip.h
 create mode 100644 gcc/testsuite/gcc.target/riscv/scalar_bitmanip_intrinsic-32.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/scalar_bitmanip_intrinsic-64-emulated.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/scalar_bitmanip_intrinsic-64.c
diff mbox series

Patch

diff --git a/gcc/config.gcc b/gcc/config.gcc
index 11c3a647b5e..00355509c92 100644
--- a/gcc/config.gcc
+++ b/gcc/config.gcc
@@ -549,7 +549,7 @@  riscv*)
 	extra_objs="${extra_objs} riscv-vector-builtins.o riscv-vector-builtins-shapes.o riscv-vector-builtins-bases.o"
 	extra_objs="${extra_objs} thead.o riscv-target-attr.o"
 	d_target_objs="riscv-d.o"
-	extra_headers="riscv_vector.h riscv_crypto.h"
+	extra_headers="riscv_vector.h riscv_crypto.h riscv_bitmanip.h"
 	target_gtfiles="$target_gtfiles \$(srcdir)/config/riscv/riscv-vector-builtins.cc"
 	target_gtfiles="$target_gtfiles \$(srcdir)/config/riscv/riscv-vector-builtins.h"
 	;;
diff --git a/gcc/config/riscv/bitmanip.md b/gcc/config/riscv/bitmanip.md
index fdab0017a2b..ccda25c01c1 100644
--- a/gcc/config/riscv/bitmanip.md
+++ b/gcc/config/riscv/bitmanip.md
@@ -443,8 +443,8 @@ 
 ;; orc.b (or-combine) is added as an unspec for the benefit of the support
 ;; for optimized string functions (such as strcmp).
 (define_insn "orcb<mode>2"
-  [(set (match_operand:X 0 "register_operand" "=r")
-	(unspec:X [(match_operand:X 1 "register_operand" "r")] UNSPEC_ORC_B))]
+  [(set (match_operand:GPR 0 "register_operand" "=r")
+	(unspec:GPR [(match_operand:GPR 1 "register_operand" "r")] UNSPEC_ORC_B))]
   "TARGET_ZBB"
   "orc.b\t%0,%1"
   [(set_attr "type" "bitmanip")])
@@ -852,9 +852,9 @@ 
 
 ;; ZBKC or ZBC extension
 (define_insn "riscv_clmul_<mode>"
-  [(set (match_operand:X 0 "register_operand" "=r")
-        (unspec:X [(match_operand:X 1 "register_operand" "r")
-                  (match_operand:X 2 "register_operand" "r")]
+  [(set (match_operand:GPR 0 "register_operand" "=r")
+        (unspec:GPR [(match_operand:GPR 1 "register_operand" "r")
+                  (match_operand:GPR 2 "register_operand" "r")]
                   UNSPEC_CLMUL))]
   "TARGET_ZBKC || TARGET_ZBC"
   "clmul\t%0,%1,%2"
diff --git a/gcc/config/riscv/crypto.md b/gcc/config/riscv/crypto.md
index bf613fca056..dd2bc94ee88 100644
--- a/gcc/config/riscv/crypto.md
+++ b/gcc/config/riscv/crypto.md
@@ -72,8 +72,8 @@ 
 
 ;; ZBKB extension
 (define_insn "riscv_brev8_<mode>"
-  [(set (match_operand:X 0 "register_operand" "=r")
-        (unspec:X [(match_operand:X 1 "register_operand" "r")]
+  [(set (match_operand:GPR 0 "register_operand" "=r")
+        (unspec:GPR [(match_operand:GPR 1 "register_operand" "r")]
                   UNSPEC_BREV8))]
   "TARGET_ZBKB"
   "brev8\t%0,%1"
diff --git a/gcc/config/riscv/riscv-builtins.cc b/gcc/config/riscv/riscv-builtins.cc
index e85169374eb..1932ff069c6 100644
--- a/gcc/config/riscv/riscv-builtins.cc
+++ b/gcc/config/riscv/riscv-builtins.cc
@@ -105,6 +105,7 @@  AVAIL (zero32,  TARGET_ZICBOZ && !TARGET_64BIT)
 AVAIL (zero64,  TARGET_ZICBOZ && TARGET_64BIT)
 AVAIL (prefetchi32, TARGET_ZICBOP && !TARGET_64BIT)
 AVAIL (prefetchi64, TARGET_ZICBOP && TARGET_64BIT)
+AVAIL (crypto_zbkb, TARGET_ZBKB)
 AVAIL (crypto_zbkb32, TARGET_ZBKB && !TARGET_64BIT)
 AVAIL (crypto_zbkb64, TARGET_ZBKB && TARGET_64BIT)
 AVAIL (crypto_zbkx32, TARGET_ZBKX && !TARGET_64BIT)
@@ -119,10 +120,15 @@  AVAIL (crypto_zknh32, TARGET_ZKNH && !TARGET_64BIT)
 AVAIL (crypto_zknh64, TARGET_ZKNH && TARGET_64BIT)
 AVAIL (crypto_zksh, TARGET_ZKSH)
 AVAIL (crypto_zksed, TARGET_ZKSED)
+AVAIL (clmul_zbkc_or_zbc, (TARGET_ZBKC || TARGET_ZBC))
 AVAIL (clmul_zbkc32_or_zbc32, (TARGET_ZBKC || TARGET_ZBC) && !TARGET_64BIT)
 AVAIL (clmul_zbkc64_or_zbc64, (TARGET_ZBKC || TARGET_ZBC) && TARGET_64BIT)
 AVAIL (clmulr_zbc32, TARGET_ZBC && !TARGET_64BIT)
 AVAIL (clmulr_zbc64, TARGET_ZBC && TARGET_64BIT)
+AVAIL (zbb, TARGET_ZBB)
+AVAIL (zbb64, TARGET_ZBB && TARGET_64BIT)
+AVAIL (zbb64_or_zbkb64, (TARGET_ZBKB || TARGET_ZBB) && TARGET_64BIT)
+AVAIL (zbb_or_zbkb, (TARGET_ZBKB || TARGET_ZBB))
 AVAIL (hint_pause, (!0))
 
 // CORE-V AVAIL
@@ -146,6 +152,22 @@  AVAIL (cvelw, TARGET_XCVELW && !TARGET_64BIT)
   { CODE_FOR_riscv_ ## INSN, "__builtin_riscv_" NAME,			\
     BUILTIN_TYPE, FUNCTION_TYPE, riscv_builtin_avail_ ## AVAIL }
 
+/* Construct a riscv_builtin_description from the given arguments like RISCV_BUILTIN.
+
+   INSN is the name of the associated instruction pattern, without the
+   leading CODE_FOR_.
+
+   NAME is the name of the function itself, without the leading
+   "__builtin_riscv_".
+
+   BUILTIN_TYPE and FUNCTION_TYPE are riscv_builtin_description fields.
+
+   AVAIL is the name of the availability predicate, without the leading
+   riscv_builtin_avail_.  */
+#define RISCV_BUILTIN_NO_PREFIX(INSN, NAME, BUILTIN_TYPE,	FUNCTION_TYPE, AVAIL)	\
+  { CODE_FOR_ ## INSN, "__builtin_riscv_" NAME,			\
+    BUILTIN_TYPE, FUNCTION_TYPE, riscv_builtin_avail_ ## AVAIL }
+
 /* Define __builtin_riscv_<INSN>, which is a RISCV_BUILTIN_DIRECT function
    mapped to instruction CODE_FOR_riscv_<INSN>,  FUNCTION_TYPE and AVAIL
    are as for RISCV_BUILTIN.  */
diff --git a/gcc/config/riscv/riscv-cmo.def b/gcc/config/riscv/riscv-cmo.def
index ff713b78e19..78cf1d84070 100644
--- a/gcc/config/riscv/riscv-cmo.def
+++ b/gcc/config/riscv/riscv-cmo.def
@@ -17,11 +17,11 @@  RISCV_BUILTIN (prefetchi_si, "zicbop_cbo_prefetchi", RISCV_BUILTIN_DIRECT, RISCV
 RISCV_BUILTIN (prefetchi_di, "zicbop_cbo_prefetchi", RISCV_BUILTIN_DIRECT, RISCV_UDI_FTYPE_UDI, prefetchi64),
 
 // zbkc or zbc
-RISCV_BUILTIN (clmul_si, "clmul", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_USI, clmul_zbkc32_or_zbc32),
-RISCV_BUILTIN (clmul_di, "clmul", RISCV_BUILTIN_DIRECT, RISCV_UDI_FTYPE_UDI_UDI, clmul_zbkc64_or_zbc64),
-RISCV_BUILTIN (clmulh_si, "clmulh", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_USI, clmul_zbkc32_or_zbc32),
-RISCV_BUILTIN (clmulh_di, "clmulh", RISCV_BUILTIN_DIRECT, RISCV_UDI_FTYPE_UDI_UDI, clmul_zbkc64_or_zbc64),
+RISCV_BUILTIN (clmul_si, "clmul_32", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_USI, clmul_zbkc_or_zbc),
+RISCV_BUILTIN (clmul_di, "clmul_64", RISCV_BUILTIN_DIRECT, RISCV_UDI_FTYPE_UDI_UDI, clmul_zbkc64_or_zbc64),
+RISCV_BUILTIN (clmulh_si, "clmulh_32", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_USI, clmul_zbkc32_or_zbc32),
+RISCV_BUILTIN (clmulh_di, "clmulh_64", RISCV_BUILTIN_DIRECT, RISCV_UDI_FTYPE_UDI_UDI, clmul_zbkc64_or_zbc64),
 
 // zbc
-RISCV_BUILTIN (clmulr_si, "clmulr", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_USI, clmulr_zbc32),
-RISCV_BUILTIN (clmulr_di, "clmulr", RISCV_BUILTIN_DIRECT, RISCV_UDI_FTYPE_UDI_UDI, clmulr_zbc64),
+RISCV_BUILTIN (clmulr_si, "clmulr_32", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_USI, clmulr_zbc32),
+RISCV_BUILTIN (clmulr_di, "clmulr_64", RISCV_BUILTIN_DIRECT, RISCV_UDI_FTYPE_UDI_UDI, clmulr_zbc64),
diff --git a/gcc/config/riscv/riscv-ftypes.def b/gcc/config/riscv/riscv-ftypes.def
index c724f23beeb..5f051df2277 100644
--- a/gcc/config/riscv/riscv-ftypes.def
+++ b/gcc/config/riscv/riscv-ftypes.def
@@ -40,9 +40,11 @@  DEF_RISCV_FTYPE (1, (SI, HI))
 DEF_RISCV_FTYPE (2, (USI, UQI, UQI))
 DEF_RISCV_FTYPE (2, (USI, UHI, UHI))
 DEF_RISCV_FTYPE (2, (USI, USI, USI))
+DEF_RISCV_FTYPE (2, (USI, USI, UQI))
 DEF_RISCV_FTYPE (2, (UDI, UQI, UQI))
 DEF_RISCV_FTYPE (2, (UDI, UHI, UHI))
 DEF_RISCV_FTYPE (2, (UDI, USI, USI))
+DEF_RISCV_FTYPE (2, (UDI, UDI, UQI))
 DEF_RISCV_FTYPE (2, (UDI, UDI, USI))
 DEF_RISCV_FTYPE (2, (UDI, UDI, UDI))
 DEF_RISCV_FTYPE (2, (SI, USI, USI))
diff --git a/gcc/config/riscv/riscv-scalar-crypto.def b/gcc/config/riscv/riscv-scalar-crypto.def
index 959d8f5f80b..d66b0fe5ad4 100644
--- a/gcc/config/riscv/riscv-scalar-crypto.def
+++ b/gcc/config/riscv/riscv-scalar-crypto.def
@@ -29,8 +29,8 @@  RISCV_BUILTIN (packw, "packw", RISCV_BUILTIN_DIRECT, RISCV_UDI_FTYPE_UHI_UHI, cr
 RISCV_BUILTIN (zip, "zip", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI, crypto_zbkb32),
 RISCV_BUILTIN (unzip, "unzip", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI, crypto_zbkb32),
 
-RISCV_BUILTIN (brev8_si, "brev8", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI, crypto_zbkb32),
-RISCV_BUILTIN (brev8_di, "brev8", RISCV_BUILTIN_DIRECT, RISCV_UDI_FTYPE_UDI, crypto_zbkb64),
+RISCV_BUILTIN (brev8_si, "brev8_32", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI, crypto_zbkb),
+RISCV_BUILTIN (brev8_di, "brev8_64", RISCV_BUILTIN_DIRECT, RISCV_UDI_FTYPE_UDI, crypto_zbkb64),
 
 // ZBKX
 RISCV_BUILTIN (xperm4_si, "xperm4", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_USI, crypto_zbkx32),
@@ -78,3 +78,21 @@  RISCV_BUILTIN (sm3p1_si, "sm3p1", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI, cry
 // ZKSED
 RISCV_BUILTIN (sm4ed_si, "sm4ed", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_USI_USI, crypto_zksed),
 RISCV_BUILTIN (sm4ks_si, "sm4ks", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_USI_USI, crypto_zksed),
+
+
+// ZBB
+
+RISCV_BUILTIN_NO_PREFIX (clzsi2,"clz_32",RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI,zbb),
+RISCV_BUILTIN_NO_PREFIX (clzdi2,"clz_64",RISCV_BUILTIN_DIRECT, RISCV_UDI_FTYPE_UDI,zbb64),
+RISCV_BUILTIN_NO_PREFIX (ctzsi2,"ctz_32",RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI,zbb),
+RISCV_BUILTIN_NO_PREFIX (ctzdi2,"ctz_64",RISCV_BUILTIN_DIRECT, RISCV_UDI_FTYPE_UDI,zbb64),
+RISCV_BUILTIN_NO_PREFIX (popcountsi2,"popcount_32",RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI,zbb),
+RISCV_BUILTIN_NO_PREFIX (popcountdi2,"popcount_64",RISCV_BUILTIN_DIRECT, RISCV_UDI_FTYPE_UDI,zbb64),
+RISCV_BUILTIN_NO_PREFIX (orcbsi2,"orc_b_32", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI,zbb),
+RISCV_BUILTIN_NO_PREFIX (orcbdi2,"orc_b_64",RISCV_BUILTIN_DIRECT, RISCV_UDI_FTYPE_UDI,zbb64),
+
+// ZBKB
+RISCV_BUILTIN_NO_PREFIX (rotrsi3,"ror_32",RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_UQI,zbb_or_zbkb),
+RISCV_BUILTIN_NO_PREFIX (rotlsi3,"rol_32",RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_UQI,zbb_or_zbkb),
+RISCV_BUILTIN_NO_PREFIX (rotrdi3,"ror_64",RISCV_BUILTIN_DIRECT, RISCV_UDI_FTYPE_UDI_UQI,zbb64_or_zbkb64),
+RISCV_BUILTIN_NO_PREFIX (rotldi3,"rol_64",RISCV_BUILTIN_DIRECT, RISCV_UDI_FTYPE_UDI_UQI,zbb64_or_zbkb64),
diff --git a/gcc/config/riscv/riscv_bitmanip.h b/gcc/config/riscv/riscv_bitmanip.h
new file mode 100644
index 00000000000..c0cc86b8400
--- /dev/null
+++ b/gcc/config/riscv/riscv_bitmanip.h
@@ -0,0 +1,297 @@ 
+/* RISC-V  Bitmanip Extension intrinsics include file.
+   Copyright (C) 2024 Free Software Foundation, Inc.
+
+   This file is part of GCC.
+
+   GCC is free software; you can redistribute it and/or modify it
+   under the terms of the GNU General Public License as published
+   by the Free Software Foundation; either version 3, or (at your
+   option) any later version.
+
+   GCC is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+   License for more details.
+
+   Under Section 7 of GPL version 3, you are granted additional
+   permissions described in the GCC Runtime Library Exception, version
+   3.1, as published by the Free Software Foundation.
+
+   You should have received a copy of the GNU General Public License and
+   a copy of the GCC Runtime Library Exception along with this program;
+   see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
+   <http://www.gnu.org/licenses/>.  */
+
+#ifndef __RISCV_BITMANIP_H
+#define __RISCV_BITMANIP_H
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#if defined (__riscv_zbb)
+
+extern __inline unsigned
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+__riscv_clz_32 (uint32_t x)
+{
+  return __builtin_riscv_clz_32 (x);
+}
+
+extern __inline unsigned
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+__riscv_ctz_32 (uint32_t x)
+{
+  return __builtin_riscv_ctz_32 (x);
+}
+
+extern __inline unsigned
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+__riscv_cpop_32 (uint32_t x)
+{
+  return __builtin_riscv_popcount_32 (x);
+}
+
+extern __inline uint32_t
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+__riscv_orc_b_32 (uint32_t x)
+{
+  return __builtin_riscv_orc_b_32 (x);
+}
+
+#if __riscv_xlen == 64
+
+extern __inline unsigned
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+__riscv_clz_64 (uint64_t x)
+{
+  return __builtin_riscv_clz_64 (x);
+}
+
+extern __inline unsigned
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+__riscv_ctz_64 (uint64_t x)
+{
+  return __builtin_riscv_ctz_64 (x);
+}
+
+extern __inline unsigned
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+__riscv_cpop_64 (uint64_t x)
+{
+  return __builtin_riscv_popcount_64 (x);
+}
+
+extern __inline uint64_t
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+__riscv_orc_b_64 (uint64_t x)
+{
+  return __builtin_riscv_orc_b_64 (x);
+}
+
+#endif
+
+#endif // __riscv_zbb
+
+#if defined (__riscv_zbb) || defined (__riscv_zbkb)
+
+extern __inline uint32_t
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+__riscv_ror_32 (uint32_t x, uint32_t shamt)
+{
+    return __builtin_riscv_ror_32 (x,shamt);
+}
+
+extern __inline uint32_t
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+__riscv_rol_32 (uint32_t x, uint32_t shamt)
+{
+    return __builtin_riscv_rol_32 (x,shamt);
+}
+
+extern __inline uint32_t
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+__riscv_rev8_32 (uint32_t x)
+{
+    return __builtin_bswap32 (x);
+}
+
+#if __riscv_xlen == 64
+
+extern __inline uint64_t
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+__riscv_ror_64 (uint64_t x, uint32_t shamt)
+{
+    return __builtin_riscv_ror_64 (x,shamt);
+}
+
+extern __inline uint64_t
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+__riscv_rol_64 (uint64_t x, uint32_t shamt)
+{
+    return __builtin_riscv_rol_64 (x,shamt);
+}
+
+extern __inline uint64_t
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+__riscv_rev8_64 (uint64_t x)
+{
+    return __builtin_bswap64 (x);
+}
+
+#endif
+
+#endif // __riscv_zbb || __riscv_zbkb
+
+#if defined (__riscv_zbkb)
+
+extern __inline uint32_t
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+__riscv_brev8_32 (uint32_t x)
+{
+    return __builtin_riscv_brev8_32 (x);
+}
+
+#if __riscv_xlen == 32
+
+extern __inline uint32_t
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+__riscv_zip_32 (uint32_t x)
+{
+    return __builtin_riscv_zip (x);
+}
+
+extern __inline uint32_t
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+__riscv_unzip_32 (uint32_t x)
+{
+    return __builtin_riscv_unzip (x);
+}
+
+#endif
+
+#if __riscv_xlen == 64
+
+extern __inline uint64_t
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+__riscv_brev8_64 (uint64_t x)
+{
+    return __builtin_riscv_brev8_64 (x);
+}
+
+#endif
+
+#endif // __riscv_zbkb
+
+#if defined (__riscv_zbc) || defined (__riscv_zbkc)
+
+extern __inline uint32_t
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+__riscv_clmul_32 (uint32_t rs1, uint32_t rs2)
+{
+    return __builtin_riscv_clmul_32 (rs1,rs2);
+}
+
+#if __riscv_xlen == 32
+
+extern __inline uint32_t
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+__riscv_clmulh_32 (uint32_t rs1, uint32_t rs2)
+{
+    return __builtin_riscv_clmulh_32 (rs1,rs2);
+}
+
+#endif
+
+#if __riscv_xlen == 64
+
+extern __inline uint64_t
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+__riscv_clmul_64 (uint64_t rs1, uint64_t rs2)
+{
+    return __builtin_riscv_clmul_64 (rs1,rs2);
+}
+
+extern __inline uint64_t
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+__riscv_clmulh_64 (uint64_t rs1, uint64_t rs2)
+{
+    return __builtin_riscv_clmulh_64 (rs1,rs2);
+}
+
+#endif
+
+#endif // __riscv_zbc || __riscv_zbkc
+
+#if defined (__riscv_zbc)
+
+#if __riscv_xlen == 32
+
+extern __inline uint32_t
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+__riscv_clmulr_32 (uint32_t rs1, uint32_t rs2)
+{
+    return __builtin_riscv_clmulr_32 (rs1,rs2);
+}
+
+#endif
+
+#if __riscv_xlen == 64
+
+extern __inline uint64_t
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+__riscv_clmulr_64 (uint64_t rs1, uint64_t rs2)
+{
+    return __builtin_riscv_clmulr_64 (rs1,rs2);
+}
+
+#endif
+
+#endif // __riscv_zbc
+
+#if defined (__riscv_zbkx)
+
+#if __riscv_xlen == 32
+
+extern __inline uint32_t
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+__riscv_xperm4_32 (uint32_t rs1, uint32_t rs2)
+{
+    return __builtin_riscv_xperm4 (rs1,rs2);
+}
+
+extern __inline uint32_t
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+__riscv_xperm8_32 (uint32_t rs1, uint32_t rs2)
+{
+    return __builtin_riscv_xperm8 (rs1,rs2);
+}
+
+#endif
+
+#if __riscv_xlen == 64
+
+extern __inline uint64_t
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+__riscv_xperm4_64 (uint64_t rs1, uint64_t rs2)
+{
+    return __builtin_riscv_xperm4 (rs1,rs2);
+}
+
+extern __inline uint64_t
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+__riscv_xperm8_64 (uint64_t rs1, uint64_t rs2)
+{
+    return __builtin_riscv_xperm8 (rs1,rs2);
+}
+
+#endif
+
+#endif // __riscv_zbkx
+
+#if defined (__cplusplus)
+}
+#endif // __cplusplus
+#endif // __RISCV_BITMANIP_H
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/riscv/scalar_bitmanip_intrinsic-32.c b/gcc/testsuite/gcc.target/riscv/scalar_bitmanip_intrinsic-32.c
new file mode 100644
index 00000000000..56878a36fb9
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/scalar_bitmanip_intrinsic-32.c
@@ -0,0 +1,97 @@ 
+/* { dg-do compile } */
+/* { dg-require-effective-target rv32 } */
+/* { dg-options "-march=rv32gc_zbb_zbc_zbkb_zbkc_zbkx -mabi=ilp32d" } */
+/* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */
+
+#include "riscv_bitmanip.h"
+
+unsigned foo1 (uint32_t x)
+{
+    return __riscv_clz_32 (x);
+}
+
+unsigned foo2 (uint32_t x)
+{
+    return __riscv_ctz_32 (x);
+}
+
+unsigned foo3 (uint32_t x)
+{
+    return __riscv_cpop_32 (x);
+}
+
+uint32_t foo4 (uint32_t x)
+{
+    return __riscv_orc_b_32 (x);
+}
+
+uint32_t foo5 (uint32_t x, uint32_t shamt)
+{
+    return __riscv_ror_32 (x,shamt);
+}
+
+uint32_t foo6 (uint32_t x, uint32_t shamt)
+{
+    return __riscv_rol_32 (x,shamt);
+}
+
+uint32_t foo7 (uint32_t x)
+{
+    return __riscv_rev8_32 (x);
+}
+
+uint32_t foo8 (uint32_t x)
+{
+    return __riscv_brev8_32 (x);
+}
+
+uint32_t foo9 (uint32_t x)
+{
+    return __riscv_zip_32 (x);
+}
+
+uint32_t foo10 (uint32_t x)
+{
+    return __riscv_unzip_32 (x);
+}
+
+uint32_t foo11 (uint32_t rs1,uint32_t rs2)
+{
+    return __riscv_clmul_32 (rs1,rs2);
+}
+
+uint32_t foo12 (uint32_t rs1,uint32_t rs2)
+{
+    return __riscv_clmulh_32 (rs1,rs2);
+}
+
+uint32_t foo13 (uint32_t rs1,uint32_t rs2)
+{
+    return __riscv_clmulr_32 (rs1,rs2);
+}
+
+uint32_t foo14 (uint32_t rs1,uint32_t rs2)
+{
+    return __riscv_xperm4_32 (rs1,rs2);
+}
+
+uint32_t foo15 (uint32_t rs1,uint32_t rs2)
+{
+    return __riscv_xperm8_32 (rs1,rs2);
+}
+
+/* { dg-final { scan-assembler-times "clz" 1 } } */
+/* { dg-final { scan-assembler-times "ctz" 1 } } */
+/* { dg-final { scan-assembler-times "cpop" 1 } } */
+/* { dg-final { scan-assembler-times "orc.b" 1 } } */
+/* { dg-final { scan-assembler-times "ror" 1 } } */
+/* { dg-final { scan-assembler-times "rol" 1 } } */
+/* { dg-final { scan-assembler-times {\mrev8} 1 } } */
+/* { dg-final { scan-assembler-times {\mbrev8} 1 } } */
+/* { dg-final { scan-assembler-times {\mzip} 1 } } */
+/* { dg-final { scan-assembler-times {\munzip} 1 } } */
+/* { dg-final { scan-assembler-times "clmul\t" 1 } } */
+/* { dg-final { scan-assembler-times "clmulh" 1 } } */
+/* { dg-final { scan-assembler-times "clmulr" 1 } } */
+/* { dg-final { scan-assembler-times "xperm4" 1 } } */
+/* { dg-final { scan-assembler-times "xperm8" 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/scalar_bitmanip_intrinsic-64-emulated.c b/gcc/testsuite/gcc.target/riscv/scalar_bitmanip_intrinsic-64-emulated.c
new file mode 100644
index 00000000000..739894aebad
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/scalar_bitmanip_intrinsic-64-emulated.c
@@ -0,0 +1,33 @@ 
+/* { dg-do compile } */
+/* { dg-require-effective-target rv64 } */
+/* { dg-options "-march=rv64gc_zbb_zbc_zbkb_zbkc -mabi=lp64d " } */
+/* { dg-skip-if "" { *-*-* } { "-g" "-O0" "-flto"} } */
+
+#include "riscv_bitmanip.h"
+
+uint32_t foo (uint32_t rs1)
+{
+    return __riscv_rev8_32 (rs1);
+}
+
+int32_t foo2(uint32_t rs1)
+{
+    return __riscv_brev8_32 (rs1);
+}
+
+uint32_t foo3 (uint32_t rs1)
+{
+    return __riscv_orc_b_32 (rs1);
+
+}
+
+uint32_t foo4 (uint32_t rs1)
+{
+    return __riscv_clmul_32 (rs1,rs1);
+}
+
+/* { dg-final { scan-assembler-times {\mrev8} 1 } } */
+/* { dg-final { scan-assembler-times "brev8" 1 } } */
+/* { dg-final { scan-assembler-times "clmul" 1 } } */
+/* { dg-final { scan-assembler-times "orc.b" 1 } } */
+/* { dg-final { scan-assembler-times "sext.w" 3 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/scalar_bitmanip_intrinsic-64.c b/gcc/testsuite/gcc.target/riscv/scalar_bitmanip_intrinsic-64.c
new file mode 100644
index 00000000000..e0da9dfda7c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/scalar_bitmanip_intrinsic-64.c
@@ -0,0 +1,115 @@ 
+/* { dg-do compile } */
+/* { dg-require-effective-target rv64 } */
+/* { dg-options "-march=rv64gc_zbb_zbc_zbkb_zbkc_zbkx -mabi=lp64d" } */
+/* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */
+
+#include "riscv_bitmanip.h"
+
+unsigned foo1 (uint32_t x)
+{
+    return __riscv_clz_32 (x);
+}
+
+unsigned foo2 (uint32_t x)
+{
+    return __riscv_ctz_32 (x);
+}
+
+unsigned foo3 (uint32_t x)
+{
+    return __riscv_cpop_32 (x);
+}
+
+uint32_t foo4 (uint32_t x, uint8_t shamt)
+{
+    return __riscv_ror_32 (x,shamt);
+}
+
+uint32_t foo5 (uint32_t x, uint8_t shamt)
+{
+    return __riscv_rol_32 (x,shamt);
+}
+
+unsigned foo6 (uint64_t x)
+{
+    return __riscv_clz_64 (x);
+}
+
+unsigned foo7 (uint64_t x)
+{
+    return __riscv_ctz_64 (x);
+}
+
+unsigned foo8 (uint64_t x)
+{
+    return __riscv_cpop_64 (x);
+}
+
+uint64_t foo9 (uint64_t x)
+{
+    return __riscv_orc_b_64 (x);
+}
+
+uint64_t foo10 (uint64_t rs1, uint8_t rs2)
+{
+    return __riscv_ror_64 (rs1,rs2);
+}
+
+uint64_t foo11 (uint64_t rs1, uint8_t rs2)
+{
+    return __riscv_rol_64 (rs1,rs2);
+}
+
+uint64_t foo12 (uint64_t x)
+{
+    return __riscv_rev8_64 (x);
+}
+
+uint64_t foo13 (uint64_t x)
+{
+    return __riscv_brev8_64 (x);
+}
+
+uint64_t foo14 (uint64_t rs1,uint64_t rs2)
+{
+    return __riscv_clmul_64 (rs1,rs2);
+}
+
+uint64_t foo15 (uint64_t rs1,uint64_t rs2)
+{
+    return __riscv_clmulh_64 (rs1,rs2);
+}
+
+uint64_t foo16 (uint64_t rs1,uint64_t rs2)
+{
+    return __riscv_clmulr_64 (rs1,rs2);
+}
+
+uint64_t foo17 (uint64_t rs1,uint64_t rs2)
+{
+    return __riscv_xperm4_64 (rs1,rs2);
+}
+
+uint64_t foo18 (uint64_t rs1,uint64_t rs2)
+{
+    return __riscv_xperm8_64 (rs1,rs2);
+}
+
+/* { dg-final { scan-assembler-times "clzw" 1 } } */
+/* { dg-final { scan-assembler-times "ctzw" 1 } } */
+/* { dg-final { scan-assembler-times "cpopw" 1 } } */
+/* { dg-final { scan-assembler-times "rorw" 1 } } */
+/* { dg-final { scan-assembler-times "rolw" 1 } } */
+/* { dg-final { scan-assembler-times "clz\t" 1 } } */
+/* { dg-final { scan-assembler-times "ctz\t" 1 } } */
+/* { dg-final { scan-assembler-times "cpop\t" 1 } } */
+/* { dg-final { scan-assembler-times "orc.b" 1 } } */
+/* { dg-final { scan-assembler-times "ror\t" 1 } } */
+/* { dg-final { scan-assembler-times "rol\t" 1 } } */
+/* { dg-final { scan-assembler-times {\mrev8} 1 } } */
+/* { dg-final { scan-assembler-times {\mbrev8} 1 } } */
+/* { dg-final { scan-assembler-times "clmul\t" 1 } } */
+/* { dg-final { scan-assembler-times "clmulh" 1 } } */
+/* { dg-final { scan-assembler-times "clmulr" 1 } } */
+/* { dg-final { scan-assembler-times "xperm4" 1 } } */
+/* { dg-final { scan-assembler-times "xperm8" 1 } } */