From patchwork Thu Jan 11 09:06:09 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kito Cheng X-Patchwork-Id: 187260 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7300:2411:b0:101:2151:f287 with SMTP id m17csp1319280dyi; Thu, 11 Jan 2024 01:07:34 -0800 (PST) X-Google-Smtp-Source: AGHT+IEpqfQEJ/L6j5k9eNYxQTUmUwNzCSK3iPBig2e3oxGbts2L+IdCFHrgz4DVS1soVZRffu8w X-Received: by 2002:ac8:4e4d:0:b0:429:aee6:ba49 with SMTP id e13-20020ac84e4d000000b00429aee6ba49mr365415qtw.32.1704964054230; Thu, 11 Jan 2024 01:07:34 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1704964054; cv=pass; d=google.com; s=arc-20160816; b=tnRovAcqp0ot9DI+U4jsB76SqISL1SNmhI2N623QuMgFWMrlbyEfeP+68UeLzv8aLj 4mord83TKecRlebR+98g/kQvQz7RZt0E+4VH8ntoFFnOtRRXAW56U/cflq+VDqlUCINZ 12tQqHh0t39vjG1JGPv4wpqE3EchhAYpQfvwoDX8Wws8E/xEvFa/J9ZrwjcD//jhDIOs erhe6xu6BzAq/CGw8QAQS9nniR2lcoa69iwW02PMUGrfWAtPwAOqsSrruQQSARgrk0+C j5rzZH88Q9ayh/sAnejaoA0HtpEr4eGyoykFN/iTlfnlQosxwRkvsTbCWzezaIx9qHF/ SsdQ== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:message-id:date:subject:cc:to:from:dkim-signature :arc-filter:dmarc-filter:delivered-to; bh=MiEsqffsGTGTVrIJYg9LTjqP87Ry140yfQdTD0M3/TY=; fh=3Ck16crQUxNabL1wC/NAUZY2nAVZpSKeVH/lwIj1XIE=; b=v4mb42BoNrPAbZ9SDdk0yKrhA+bE7Gm5vUlk9AuFRc5IkjgTVeHw34x9FwB/5YpCLB LJOT1VZByXVP/4EkZfhKeKG5e/eQwuz63MlSbWm26Ca/5jd+oXkyjJaC+6LtuPyHnhrn otDJl53nqHtNW6ZxBpzn99zTq6Zpmfkdd7fgEPCM4XOFND/hO7dS27x2xZgC3m/IKUXg g4KTD8FbR8l3rPsOaT8TLK4YWvQ85XnXDKHbpBnRIbj4IZ8AJQ/RM1YW0dztJ1jppf8c ahaxYqcUxipkIkdaGKAMjdXn+6+vW009k8H5MTSxjLhWJUr/GGSfPu5YsRKHYCO0bNQN X1jA== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@sifive.com header.s=google header.b=RyELrnz5; arc=pass (i=1); spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org"; dmarc=pass (p=REJECT sp=REJECT dis=NONE) header.from=sifive.com Received: from server2.sourceware.org (server2.sourceware.org. [2620:52:3:1:0:246e:9693:128c]) by mx.google.com with ESMTPS id k4-20020ac85fc4000000b00429c82ec191si50689qta.738.2024.01.11.01.07.34 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 11 Jan 2024 01:07:34 -0800 (PST) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) client-ip=2620:52:3:1:0:246e:9693:128c; Authentication-Results: mx.google.com; dkim=pass header.i=@sifive.com header.s=google header.b=RyELrnz5; arc=pass (i=1); spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org"; dmarc=pass (p=REJECT sp=REJECT dis=NONE) header.from=sifive.com Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id E068B385772F for ; Thu, 11 Jan 2024 09:07:33 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mail-pf1-x42b.google.com (mail-pf1-x42b.google.com [IPv6:2607:f8b0:4864:20::42b]) by sourceware.org (Postfix) with ESMTPS id A60DC385800A for ; Thu, 11 Jan 2024 09:06:15 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org A60DC385800A Authentication-Results: sourceware.org; dmarc=pass (p=reject dis=none) header.from=sifive.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=sifive.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org A60DC385800A Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=2607:f8b0:4864:20::42b ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1704963978; cv=none; b=p7JmZvHls/g2pl9AsrO5j7lNZk4O5mA+9FEyDVn7uU50YoguWSlbvc4yEVNUj4DKXZlLR4uc2iAL239vRY3nY6AkZ0ZSlR+tcscm3rVd44Jh4AXPSzhRmmcrJTSCBxWXSy3h5UWJq9QP6+QCP5EWAYKw7ldRtbw8GKHXeN73+W8= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1704963978; c=relaxed/simple; bh=q1l94DDi/QfOt+AFgnpB/ZtRPg7Ev9yMsi6G/fNU8nU=; h=DKIM-Signature:From:To:Subject:Date:Message-Id:MIME-Version; b=kaT0UKyFf3HxoJThe4QL9qR3ILqNrSFYQbYhnOabwJCFeFp2OBlI7svI3Wci/U4Sz7oYdUYCnuc6SCfzzo0mShhceZrXskzVmyYP42XEmY2GzcsJEhyrurGrFJLxKc4if7pGINHZTmtQkAVWWEeXnWZ2BWvCs7aTbVc1jWPUcVU= ARC-Authentication-Results: i=1; server2.sourceware.org Received: by mail-pf1-x42b.google.com with SMTP id d2e1a72fcca58-6daa89a6452so3348715b3a.2 for ; Thu, 11 Jan 2024 01:06:15 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; t=1704963974; x=1705568774; darn=gcc.gnu.org; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:from:to:cc:subject:date:message-id:reply-to; bh=MiEsqffsGTGTVrIJYg9LTjqP87Ry140yfQdTD0M3/TY=; b=RyELrnz5f2lZ5YHVkwP8jw1ARBHJlwefJJGbg/ssQCeMoDOGgyMX9WkRorueL0F66Y 4z/Lc75cbmEerw5s0bmE1XsZBiAXKSOo7V1mn2ttemvHGQvSad2Rgsi5diGTGpFRU2i6 7JUEcFPja6/V0R9KQBzQNlvMi6vQmt8OpflpKmlcPJ1bzXUCxXVvkeKN20Cfmh0x0ksO nKQ4zoShOxb4Fci6PAadqXr5yPosl5JhXf0tEIYHFkVK27nqBlON/txiSFpi4aPlCH1W vSxH6yXJBym6IL46pA85gTwVVu5WOHjpE+NBPWN5tqb5p7K51HzEJP6hmmdzZvU995mh FYZw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1704963974; x=1705568774; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=MiEsqffsGTGTVrIJYg9LTjqP87Ry140yfQdTD0M3/TY=; b=NCceeS764EvCYW4gNP2ihO5CIIEgnIVS9fiXFwPvy0o2a6qAOcINUxnYBq+wzgzspp BU+ULneJ2lTjeiIjL0LZbx04JFeVoaRH6NivRyevp1Yo98tC1uHahqfBx1J+mXhI+ZyE WJOdTxrZ2QwSokl9cyRypuq05CbrqlEXimFu5FeNiB4+FykRnWYPdqed117jBH1VDSaM kdbDy9T5LgFyvzzu0d9Z5T9taRpulRDTrHIwKfHq3eQA+AMK8epsSKL85tib0QrSQlO1 LlHu5Se3CNjgYENdJUkusbz+8F+u7tJyeRVjjQ9ENYMY6HJlh+Nh9KVo/oUdDYJeUyFf AkZQ== X-Gm-Message-State: AOJu0YwQ4OKDbUvATsca9pPzmPrKADBsa7YjS+eHJckVSsF3Aqz1jgtb w6DQPfv7+zvIMp2MYhc+Anen9NZ4s39Z1CJXMhYQfxbgQVWdOUBjF5zZKwOprXhd5AWPv85tLIU kLsmKT6GYXDA2Ph/nDM9AALldpbBp+ySQwoVNK1rl+m3oqLZc7AB39ijMvWVvz01II3QmBazlvJ s7v/QHMr+FQWY= X-Received: by 2002:a05:6a00:4604:b0:6d9:b9af:41cb with SMTP id ko4-20020a056a00460400b006d9b9af41cbmr822388pfb.14.1704963973914; Thu, 11 Jan 2024 01:06:13 -0800 (PST) Received: from hsinchu18.internal.sifive.com (59-124-168-89.hinet-ip.hinet.net. [59.124.168.89]) by smtp.gmail.com with ESMTPSA id d14-20020a056a0010ce00b006d9c7f2840bsm665823pfu.57.2024.01.11.01.06.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 11 Jan 2024 01:06:13 -0800 (PST) From: Kito Cheng To: gcc-patches@gcc.gnu.org, kito.cheng@gmail.com, jim.wilson.gcc@gmail.com, palmer@dabbelt.com, andrew@sifive.com, jeffreyalaw@gmail.com, christoph.muellner@vrull.eu Cc: Kito Cheng Subject: [PATCH] RISC-V: Documnet the list of supported extensions Date: Thu, 11 Jan 2024 17:06:09 +0800 Message-Id: <20240111090609.1043115-1-kito.cheng@sifive.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 X-Spam-Status: No, score=-12.8 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1787784388421527812 X-GMAIL-MSGID: 1787784388421527812 Try to list all supported extensions: name, version and few description for each extension. gcc/ChangeLog: * doc/invoke.texi (RISC-V Options): Add list of supported extensions. --- gcc/doc/invoke.texi | 463 ++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 463 insertions(+) diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index 68d1f364ac0..58271f2f28e 100644 --- a/gcc/doc/invoke.texi +++ b/gcc/doc/invoke.texi @@ -30037,6 +30037,469 @@ Generate code for given RISC-V ISA (e.g.@: @samp{rv64im}). ISA strings must be lower-case. Examples include @samp{rv64i}, @samp{rv32g}, @samp{rv32e}, and @samp{rv32imaf}. +Supported extension are list below: +@multitable @columnfractions .10 .10 .80 +@headitem Extension Name @tab Supported Version @tab Description +@item i +@tab 2.0, 2.1 +@tab Base integer extension. + +@item e +@tab 2.0 +@tab Reduced base integer extension. + +@item g +@tab - +@tab General-purpose computing base extension, @samp{g} will expand to +@samp{i}, @samp{m}, @samp{a}, @samp{f}, @samp{d}, @samp{zicsr} and +@samp{zifencei}. + +@item m +@tab 2.0 +@tab Integer multiplication and division extension. + +@item a +@tab 2.0, 2.1 +@tab Atomic extension. + +@item f +@tab 2.0, 2.2 +@tab Single-precision floating-point extension. + +@item d +@tab 2.0, 2.2 +@tab Double-precision floating-point extension. + +@item c +@tab 2.0 +@tab Compressed extension. + +@item h +@tab 1.0 +@tab Hypervisor extension. + +@item v +@tab 1.0 +@tab Vector extension. + +@item zicsr +@tab 2.0 +@tab Control and status register access extension. + +@item zifencei +@tab 2.0 +@tab Instruction-fetch fence extension. + +@item zicond +@tab 1.0 +@tab Integer conditional operations extension. + +@item zawrs +@tab 1.0 +@tab Wait-on-reservation-set extension. + +@item zba +@tab 1.0 +@tab Address calculation extension. + +@item zbb +@tab 1.0 +@tab Basic bit manipulation extension. + +@item zbc +@tab 1.0 +@tab Carry-less multiplication extension. + +@item zbs +@tab 1.0 +@tab Single-bit operation extension. + +@item zfinx +@tab 1.0 +@tab Single-precision floating-ioint in integer registers extension. + +@item zdinx +@tab 1.0 +@tab Double-precision floating-ioint in integer registers extension. + +@item zhinx +@tab 1.0 +@tab Half-precision floating-ioint in integer registers extension. + +@item zhinxmin +@tab 1.0 +@tab Minimal half-precision floating-ioint in integer registers extension. + +@item zbkb +@tab 1.0 +@tab Cryptography bit-manipulation extension. + +@item zbkc +@tab 1.0 +@tab Cryptography carry-less multiply extension. + +@item zbkx +@tab 1.0 +@tab Cryptography crossbar permutation extension. + +@item zkne +@tab 1.0 +@tab AES Encryption extension. + +@item zknd +@tab 1.0 +@tab AES Decryption extension. + +@item zknh +@tab 1.0 +@tab Hash function extension. + +@item zkr +@tab 1.0 +@tab Entropy source extension. + +@item zksed +@tab 1.0 +@tab SM4 block cipher extension. + +@item zksh +@tab 1.0 +@tab SM3 hash function extension. + +@item zkt +@tab 1.0 +@tab Data independent execution latency extension. + +@item zk +@tab 1.0 +@tab Standard scalar cryptography extension. + +@item zkn +@tab 1.0 +@tab NIST algorithm suite extension. + +@item zks +@tab 1.0 +@tab ShangMi algorithm suite extension. + +@item zihintntl +@tab 1.0 +@tab Non-temporal locality hints extension. + +@item zihintpause +@tab 1.0 +@tab Pause hint extension. + +@item zicboz +@tab 1.0 +@tab Cache-block zero extension. + +@item zicbom +@tab 1.0 +@tab Cache-block management extension. + +@item zicbop +@tab 1.0 +@tab Cache-block prefetch extension. + +@item ztso +@tab 1.0 +@tab Total store ordering extension. + +@item zve32x +@tab 1.0 +@tab Vector extensions for embedded processors. + +@item zve32f +@tab 1.0 +@tab Vector extensions for embedded processors. + +@item zve64x +@tab 1.0 +@tab Vector extensions for embedded processors. + +@item zve64f +@tab 1.0 +@tab Vector extensions for embedded processors. + +@item zve64d +@tab 1.0 +@tab Vector extensions for embedded processors. + +@item zvl32b +@tab 1.0 +@tab Minimum vector length standard extensions + +@item zvl64b +@tab 1.0 +@tab Minimum vector length standard extensions + +@item zvl128b +@tab 1.0 +@tab Minimum vector length standard extensions + +@item zvl256b +@tab 1.0 +@tab Minimum vector length standard extensions + +@item zvl512b +@tab 1.0 +@tab Minimum vector length standard extensions + +@item zvl1024b +@tab 1.0 +@tab Minimum vector length standard extensions + +@item zvl2048b +@tab 1.0 +@tab Minimum vector length standard extensions + +@item zvl4096b +@tab 1.0 +@tab Minimum vector length standard extensions + +@item zvl8192b +@tab 1.0 +@tab Minimum vector length standard extensions + +@item zvl16384b +@tab 1.0 +@tab Minimum vector length standard extensions + +@item zvl32768b +@tab 1.0 +@tab Minimum vector length standard extensions + +@item zvl65536b +@tab 1.0 +@tab Minimum vector length standard extensions + +@item zvbb +@tab 1.0 +@tab Vector basic bit-manipulation extension. + +@item zvbc +@tab 1.0 +@tab Vector carryless multiplication extension. + +@item zvkb +@tab 1.0 +@tab Vector cryptography bit-manipulation extension. + +@item zvkg +@tab 1.0 +@tab Vector GCM/GMAC extension. + +@item zvkned +@tab 1.0 +@tab Vector AES block cipher extension. + +@item zvknha +@tab 1.0 +@tab Vector SHA-2 secure hash extension. + +@item zvknhb +@tab 1.0 +@tab Vector SHA-2 secure hash extension. + +@item zvksed +@tab 1.0 +@tab Vector SM4 Block Cipher extension. + +@item zvksh +@tab 1.0 +@tab Vector SM3 Secure Hash extension. + +@item zvkn +@tab 1.0 +@tab Vector NIST Algorithm Suite extension. + +@item zvknc +@tab 1.0 +@tab Vector NIST Algorithm Suite with carryless multiply extension. + +@item zvkng +@tab 1.0 +@tab Vector NIST Algorithm Suite with GCM extension. + +@item zvks +@tab 1.0 +@tab Vector ShangMi algorithm suite extension. + +@item zvksc +@tab 1.0 +@tab Vector ShangMi algorithm suite with carryless multiplication extension. + +@item zvksg +@tab 1.0 +@tab Vector ShangMi algorithm suite with GCM extension. + +@item zvkt +@tab 1.0 +@tab Vector data independent execution latency extension. + +@item zfh +@tab 1.0 +@tab Half-precision floating-point extension. + +@item zfhmin +@tab 1.0 +@tab Minimal half-precision floating-point extension. + +@item zvfh +@tab 1.0 +@tab Vector half-precision floating-point extension. + +@item zvfhmin +@tab 1.0 +@tab Vector minimal half-precision floating-point extension. + +@item zvfbfmin +@tab 1.0 +@tab Vector BF16 converts extension. + +@item zfa +@tab 1.0 +@tab Additional floating-point extension. + +@item zmmul +@tab 1.0 +@tab Integer multiplication extension. + +@item zca +@tab 1.0 +@tab Integer compressed instruction extension. + +@item zcf +@tab 1.0 +@tab Compressed single-precision floating point loads and stores extension. + +@item zcd +@tab 1.0 +@tab Compressed double-precision floating point loads and stores extension. + +@item zcb +@tab 1.0 +@tab Simple compressed instruction extension. + +@item zce +@tab 1.0 +@tab Compressed instruction extensions for embedded processors. + +@item zcmp +@tab 1.0 +@tab Compressed push pop extension. + +@item zcmt +@tab 1.0 +@tab Table jump instruction extension. + +@item smaia +@tab 1.0 +@tab Advanced interrupt architecture extension. + +@item smepmp +@tab 1.0 +@tab Enchanted PMP extension. + +@item smstateen +@tab 1.0 +@tab State enable extension. + +@item ssaia +@tab 1.0 +@tab Advanced interrupt architecture extension for supervisor-mode. + +@item sscofpmf +@tab 1.0 +@tab Count overflow & filtering extension. + +@item ssstateen +@tab 1.0 +@tab State-enable extension for supervisor-mode. + +@item sstc +@tab 1.0 +@tab Supervisor-mode timer interrupts extension. + +@item svinval +@tab 1.0 +@tab Fine-grained address-translation cache invalidation extension. + +@item svnapot +@tab 1.0 +@tab NAPOT translation contiguity extension. + +@item svpbmt +@tab 1.0 +@tab Page-based memory types extension. + +@item xcvmac +@tab 1.0 +@tab Core-V multiply-accumulate extension. + +@item xcvalu +@tab 1.0 +@tab Core-V miscellaneous ALU extension. + +@item xcvelw +@tab 1.0 +@tab Core-V event load word extension. + +@item xtheadba +@tab 1.0 +@tab T-head address calculation extension. + +@item xtheadbb +@tab 1.0 +@tab T-head basic bit-manipulation extension. + +@item xtheadbs +@tab 1.0 +@tab T-head single-bit instructions extension. + +@item xtheadcmo +@tab 1.0 +@tab T-head cache management operations extension. + +@item xtheadcondmov +@tab 1.0 +@tab T-head conditional move extension. + +@item xtheadfmemidx +@tab 1.0 +@tab T-head indexed memory operations for floating-point registers extension. + +@item xtheadfmv +@tab 1.0 +@tab T-head double floating-point high-bit data transmission extension. + +@item xtheadint +@tab 1.0 +@tab T-head acceleration interruption extension. + +@item xtheadmac +@tab 1.0 +@tab T-head multiply-accumulate extension. + +@item xtheadmemidx +@tab 1.0 +@tab T-haed indexed memory operation extension. + +@item xtheadmempair +@tab 1.0 +@tab T-head two-GPR memory operation extension. + +@item xtheadsync +@tab 1.0 +@tab T-head multi-core synchronization extension. + +@item xventanacondops +@tab 1.0 +@tab Ventana integer conditional operations extension. + +@end multitable + When @option{-march=} is not specified, use the setting from @option{-mcpu}. If both @option{-march} and @option{-mcpu=} are not specified, the default for