From patchwork Wed Jan 10 09:27:36 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: joshua X-Patchwork-Id: 186725 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7300:2411:b0:101:2151:f287 with SMTP id m17csp676687dyi; Wed, 10 Jan 2024 01:28:56 -0800 (PST) X-Google-Smtp-Source: AGHT+IHnwsR4N0ozUDEzMa7RrV2l6du5IW/EVz99p/0RtjQg6vq14RRZzskG/S5qEATcWAkehkSx X-Received: by 2002:a05:622a:1049:b0:429:b948:2f06 with SMTP id f9-20020a05622a104900b00429b9482f06mr260655qte.14.1704878935665; Wed, 10 Jan 2024 01:28:55 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1704878935; cv=pass; d=google.com; s=arc-20160816; b=SzgKEXUc/cpz7FCmeMR9Gjf30BzAfVEm5pOkGrY7IMwFz3m8zD+r5AP5BO5elDMN8b gwKvfrsTnucyQQah8lUyT5F2QAIhgDxUW4WZgMxx3d3BN44gAuux7aFZAmgrLpA8GY/m DezaBFO3ywes8VXzZWlTt1K5tv6US6D2LymSE7F8ejTzBEDT+gYadxgi9FMGEAjBQE1z 553L88g0NnBHn/QyyXzQtKb9uriGJfDOuw2BPEQhNZgAxOga+SFvWW5jPtC6BJEGzOxK PkarrpWWYxeL5ddC2ApVte9qXAo54VnNe0yEIxLb4a8RtHq8U1pcupLf+ekHIs8lY7Zf 0jTA== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:arc-filter:dmarc-filter:delivered-to; bh=gpwj0Xt1kI3RKSI+FnPwp/v2cJiH5gy/XuuwaFs/EBE=; fh=TRVAIDsvPpet1cO/KeaYdiXE7OYydCC57sZbOkt55RI=; b=BrpanFK/W9F9sGaM2WAZfIvjgSq40UTr/r/wcRECXNjRv6OafaZ37u161sgT1w6acy ijzrWmu12KmDKKm893Cfd2xTuzAEWdNAhukP3VNyA8JnQJx/a44JEkfCQwwhVT1LylJN Ny5NR6AvqTkuNN77C7XRSXN7aeCA/ilLMP1+E8G6nQ2mnW0lbHFhXszT/StUjbDMFPPg kRqA0Ym51Kb8Oywp5g8YcQYC1FeHwEsB4LtSCZx3tFv8wAyN48z843f1L1z9QnB2sxRZ DYVtLkzGLAhSCkB35CiRL4cMv22DgoxIriyHbNKo8SZc6xnTSTqSoyod9/JgiArXFi36 gl+w== ARC-Authentication-Results: i=2; mx.google.com; arc=pass (i=1); spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=alibaba.com Received: from server2.sourceware.org (server2.sourceware.org. [8.43.85.97]) by mx.google.com with ESMTPS id v21-20020a05622a189500b004299fb43576si3780359qtc.62.2024.01.10.01.28.55 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 10 Jan 2024 01:28:55 -0800 (PST) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) client-ip=8.43.85.97; Authentication-Results: mx.google.com; arc=pass (i=1); spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=alibaba.com Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 54593385841C for ; Wed, 10 Jan 2024 09:28:55 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from out30-110.freemail.mail.aliyun.com (out30-110.freemail.mail.aliyun.com [115.124.30.110]) by sourceware.org (Postfix) with ESMTPS id 31F1A385840A for ; Wed, 10 Jan 2024 09:27:53 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 31F1A385840A Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=linux.alibaba.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=linux.alibaba.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 31F1A385840A Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=115.124.30.110 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1704878881; cv=none; b=lv+VNeG2BlSqRqZ2DsBmbA6Wb5HrmUJtP0Gb906QJ98Lp0aYQdoBMrYmMIjq3xij2NNbQK2fZJILTKKxhRXgNyRKu1/M6Tiz3QmUHehUW1Ozyp/f3uCbVi4nvC6wWIKkB+jV+QnnYUmie5eocEUufNkr0bagp1unV/jZHrPm/Zs= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1704878881; c=relaxed/simple; bh=tQvb5PbhhlXCujKNDabM653rqp/M5AmTYE1Cg80YVhU=; h=From:To:Subject:Date:Message-Id:MIME-Version; b=B8tyAPywHeEpGi29r8Tq+dHD162AsIiahAc3wEL5W6XZEZ83W7RM3iEUEPsOVXkmw/dY65iTpFi9YSvIGIYqLMjjDaldTDZr4FSLXItfvmBnu0DXGY4q2FmLSTC2LbIRmbY8Bu6ZUs2sSnVgRbXd/MGAtBa1QTejRRYPHqFi5w8= ARC-Authentication-Results: i=1; server2.sourceware.org X-Alimail-AntiSpam: AC=PASS; BC=-1|-1; BR=01201311R191e4; CH=green; DM=||false|; DS=||; FP=0|-1|-1|-1|0|-1|-1|-1; HT=ay29a033018045176; MF=cooper.joshua@linux.alibaba.com; NM=1; PH=DS; RN=11; SR=0; TI=SMTPD_---0W-LegJB_1704878867; Received: from localhost.localdomain(mailfrom:cooper.joshua@linux.alibaba.com fp:SMTPD_---0W-LegJB_1704878867) by smtp.aliyun-inc.com; Wed, 10 Jan 2024 17:27:49 +0800 From: "Jun Sha (Joshua)" To: gcc-patches@gcc.gnu.org Cc: jim.wilson.gcc@gmail.com, palmer@dabbelt.com, andrew@sifive.com, philipp.tomsich@vrull.eu, jeffreyalaw@gmail.com, christoph.muellner@vrull.eu, juzhe.zhong@rivai.ai, "Jun Sha (Joshua)" , Jin Ma , Xianmiao Qu Subject: [PATCH v5] RISC-V: Add support for xtheadvector-specific intrinsics. Date: Wed, 10 Jan 2024 17:27:36 +0800 Message-Id: <20240110092737.1238-1-cooper.joshua@linux.alibaba.com> X-Mailer: git-send-email 2.27.0.windows.1 In-Reply-To: <20240104023407.1949-1-cooper.joshua@linux.alibaba.com> References: <20240104023407.1949-1-cooper.joshua@linux.alibaba.com> MIME-Version: 1.0 X-Spam-Status: No, score=-20.6 required=5.0 tests=BAYES_00, ENV_AND_HDR_SPF_MATCH, GIT_PATCH_0, KAM_DMARC_STATUS, KAM_SHORT, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE, UNPARSEABLE_RELAY, USER_IN_DEF_SPF_WL autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1786588739390704203 X-GMAIL-MSGID: 1787695135125114570 This patch only involves the generation of xtheadvector special load/store instructions and vext instructions. gcc/ChangeLog: * config/riscv/riscv-vector-builtins-bases.cc (class th_loadstore_width): Define new builtin bases. (BASE): Define new builtin bases. * config/riscv/riscv-vector-builtins-bases.h: Define new builtin class. * config/riscv/riscv-vector-builtins-functions.def (vlsegff): Include thead-vector-builtins-functions.def. * config/riscv/riscv-vector-builtins-shapes.cc (struct th_loadstore_width_def): Define new builtin shapes. (struct th_indexed_loadstore_width_def): Define new builtin shapes. (SHAPE): Define new builtin shapes. * config/riscv/riscv-vector-builtins-shapes.h: Define new builtin shapes. * config/riscv/riscv-vector-builtins-types.def (DEF_RVV_I8_OPS): Add datatypes for XTheadVector. (DEF_RVV_I16_OPS): Add datatypes for XTheadVector. (DEF_RVV_I32_OPS): Add datatypes for XTheadVector. (DEF_RVV_U8_OPS): Add datatypes for XTheadVector. (DEF_RVV_U16_OPS): Add datatypes for XTheadVector. (DEF_RVV_U32_OPS): Add datatypes for XTheadVector. (vint8m1_t): Add datatypes for XTheadVector. (vint8m2_t): Likewise. (vint8m4_t): Likewise. (vint8m8_t): Likewise. (vint16m1_t): Likewise. (vint16m2_t): Likewise. (vint16m4_t): Likewise. (vint16m8_t): Likewise. (vint32m1_t): Likewise. (vint32m2_t): Likewise. (vint32m4_t): Likewise. (vint32m8_t): Likewise. (vint64m1_t): Likewise. (vint64m2_t): Likewise. (vint64m4_t): Likewise. (vint64m8_t): Likewise. (vuint8m1_t): Likewise. (vuint8m2_t): Likewise. (vuint8m4_t): Likewise. (vuint8m8_t): Likewise. (vuint16m1_t): Likewise. (vuint16m2_t): Likewise. (vuint16m4_t): Likewise. (vuint16m8_t): Likewise. (vuint32m1_t): Likewise. (vuint32m2_t): Likewise. (vuint32m4_t): Likewise. (vuint32m8_t): Likewise. (vuint64m1_t): Likewise. (vuint64m2_t): Likewise. (vuint64m4_t): Likewise. (vuint64m8_t): Likewise. * config/riscv/riscv-vector-builtins.cc (DEF_RVV_I8_OPS): Add datatypes for XTheadVector. (DEF_RVV_I16_OPS): Add datatypes for XTheadVector. (DEF_RVV_I32_OPS): Add datatypes for XTheadVector. (DEF_RVV_U8_OPS): Add datatypes for XTheadVector. (DEF_RVV_U16_OPS): Add datatypes for XTheadVector. (DEF_RVV_U32_OPS): Add datatypes for XTheadVector. * config/riscv/thead-vector-builtins-functions.def: New file. * config/riscv/thead-vector.md: Add new patterns. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/xtheadvector/vlb-vsb.c: New test. * gcc.target/riscv/rvv/xtheadvector/vlbu-vsb.c: New test. * gcc.target/riscv/rvv/xtheadvector/vlh-vsh.c: New test. * gcc.target/riscv/rvv/xtheadvector/vlhu-vsh.c: New test. * gcc.target/riscv/rvv/xtheadvector/vlw-vsw.c: New test. * gcc.target/riscv/rvv/xtheadvector/vlwu-vsw.c: New test. Co-authored-by: Jin Ma Co-authored-by: Xianmiao Qu Co-authored-by: Christoph Müllner --- .../riscv/riscv-vector-builtins-bases.cc | 139 ++++++++ .../riscv/riscv-vector-builtins-bases.h | 31 ++ .../riscv/riscv-vector-builtins-shapes.cc | 98 ++++++ .../riscv/riscv-vector-builtins-shapes.h | 3 + .../riscv/riscv-vector-builtins-types.def | 120 +++++++ gcc/config/riscv/riscv-vector-builtins.cc | 311 ++++++++++++++++++ gcc/config/riscv/riscv-vector-builtins.h | 3 + gcc/config/riscv/t-riscv | 1 + .../riscv/thead-vector-builtins-functions.def | 39 +++ gcc/config/riscv/thead-vector.md | 253 ++++++++++++++ .../riscv/rvv/xtheadvector/vlb-vsb.c | 68 ++++ .../riscv/rvv/xtheadvector/vlbu-vsb.c | 68 ++++ .../riscv/rvv/xtheadvector/vlh-vsh.c | 68 ++++ .../riscv/rvv/xtheadvector/vlhu-vsh.c | 68 ++++ .../riscv/rvv/xtheadvector/vlw-vsw.c | 68 ++++ .../riscv/rvv/xtheadvector/vlwu-vsw.c | 68 ++++ 16 files changed, 1406 insertions(+) create mode 100644 gcc/config/riscv/thead-vector-builtins-functions.def create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/vlb-vsb.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/vlbu-vsb.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/vlh-vsh.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/vlhu-vsh.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/vlw-vsw.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/vlwu-vsw.c diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.cc b/gcc/config/riscv/riscv-vector-builtins-bases.cc index 46f1a1da33e..5f44f31a12b 100644 --- a/gcc/config/riscv/riscv-vector-builtins-bases.cc +++ b/gcc/config/riscv/riscv-vector-builtins-bases.cc @@ -2125,6 +2125,83 @@ public: } }; +/* Implements + * th.vl(b/h/w)[u].v/th.vs(b/h/w)[u].v/th.vls(b/h/w)[u].v/th.vss(b/h/w)[u].v/ + * th.vlx(b/h/w)[u].v/th.vs[u]x(b/h/w).v + * codegen. */ +template +class th_loadstore_width : public function_base +{ +public: + bool apply_tail_policy_p () const override { return !STORE_P; } + bool apply_mask_policy_p () const override { return !STORE_P; } + + unsigned int call_properties (const function_instance &) const override + { + if (STORE_P) + return CP_WRITE_MEMORY; + else + return CP_READ_MEMORY; + } + + bool can_be_overloaded_p (enum predication_type_index pred) const override + { + if (STORE_P || LST_TYPE == LST_INDEXED) + return true; + return pred != PRED_TYPE_none; + } + + rtx expand (function_expander &e) const override + { + gcc_assert (TARGET_XTHEADVECTOR); + if (LST_TYPE == LST_INDEXED) + { + if (STORE_P) + return e.use_exact_insn ( + code_for_pred_indexed_store_width (UNSPEC, UNSPEC, + e.vector_mode ())); + else + return e.use_exact_insn ( + code_for_pred_indexed_load_width (UNSPEC, e.vector_mode ())); + } + else if (LST_TYPE == LST_STRIDED) + { + if (STORE_P) + return e.use_contiguous_store_insn ( + code_for_pred_strided_store_width (UNSPEC, e.vector_mode ())); + else + return e.use_contiguous_load_insn ( + code_for_pred_strided_load_width (UNSPEC, e.vector_mode ())); + } + else + { + if (STORE_P) + return e.use_contiguous_store_insn ( + code_for_pred_store_width (UNSPEC, e.vector_mode ())); + else + return e.use_contiguous_load_insn ( + code_for_pred_mov_width (UNSPEC, e.vector_mode ())); + } + } +}; + +/* Implements vext.x.v. */ +class th_extract : public function_base +{ +public: + bool apply_vl_p () const override { return false; } + bool apply_tail_policy_p () const override { return false; } + bool apply_mask_policy_p () const override { return false; } + bool use_mask_predication_p () const override { return false; } + bool has_merge_operand_p () const override { return false; } + + rtx expand (function_expander &e) const override + { + gcc_assert (TARGET_XTHEADVECTOR); + return e.use_exact_insn (code_for_pred_th_extract (e.vector_mode ())); + } +}; + /* Below implements are vector crypto */ /* Implements vandn.[vv,vx] */ class vandn : public function_base @@ -2587,6 +2664,37 @@ static CONSTEXPR const seg_indexed_load vloxseg_obj; static CONSTEXPR const seg_indexed_store vsuxseg_obj; static CONSTEXPR const seg_indexed_store vsoxseg_obj; static CONSTEXPR const vlsegff vlsegff_obj; +static CONSTEXPR const th_loadstore_width th_vlb_obj; +static CONSTEXPR const th_loadstore_width th_vlbu_obj; +static CONSTEXPR const th_loadstore_width th_vlh_obj; +static CONSTEXPR const th_loadstore_width th_vlhu_obj; +static CONSTEXPR const th_loadstore_width th_vlw_obj; +static CONSTEXPR const th_loadstore_width th_vlwu_obj; +static CONSTEXPR const th_loadstore_width th_vsb_obj; +static CONSTEXPR const th_loadstore_width th_vsh_obj; +static CONSTEXPR const th_loadstore_width th_vsw_obj; +static CONSTEXPR const th_loadstore_width th_vlsb_obj; +static CONSTEXPR const th_loadstore_width th_vlsbu_obj; +static CONSTEXPR const th_loadstore_width th_vlsh_obj; +static CONSTEXPR const th_loadstore_width th_vlshu_obj; +static CONSTEXPR const th_loadstore_width th_vlsw_obj; +static CONSTEXPR const th_loadstore_width th_vlswu_obj; +static CONSTEXPR const th_loadstore_width th_vssb_obj; +static CONSTEXPR const th_loadstore_width th_vssh_obj; +static CONSTEXPR const th_loadstore_width th_vssw_obj; +static CONSTEXPR const th_loadstore_width th_vlxb_obj; +static CONSTEXPR const th_loadstore_width th_vlxbu_obj; +static CONSTEXPR const th_loadstore_width th_vlxh_obj; +static CONSTEXPR const th_loadstore_width th_vlxhu_obj; +static CONSTEXPR const th_loadstore_width th_vlxw_obj; +static CONSTEXPR const th_loadstore_width th_vlxwu_obj; +static CONSTEXPR const th_loadstore_width th_vsxb_obj; +static CONSTEXPR const th_loadstore_width th_vsxh_obj; +static CONSTEXPR const th_loadstore_width th_vsxw_obj; +static CONSTEXPR const th_loadstore_width th_vsuxb_obj; +static CONSTEXPR const th_loadstore_width th_vsuxh_obj; +static CONSTEXPR const th_loadstore_width th_vsuxw_obj; +static CONSTEXPR const th_extract th_vext_x_v_obj; /* Crypto Vector */ static CONSTEXPR const vandn vandn_obj; @@ -2878,6 +2986,37 @@ BASE (vloxseg) BASE (vsuxseg) BASE (vsoxseg) BASE (vlsegff) +BASE (th_vlb) +BASE (th_vlh) +BASE (th_vlw) +BASE (th_vlbu) +BASE (th_vlhu) +BASE (th_vlwu) +BASE (th_vsb) +BASE (th_vsh) +BASE (th_vsw) +BASE (th_vlsb) +BASE (th_vlsh) +BASE (th_vlsw) +BASE (th_vlsbu) +BASE (th_vlshu) +BASE (th_vlswu) +BASE (th_vssb) +BASE (th_vssh) +BASE (th_vssw) +BASE (th_vlxb) +BASE (th_vlxh) +BASE (th_vlxw) +BASE (th_vlxbu) +BASE (th_vlxhu) +BASE (th_vlxwu) +BASE (th_vsxb) +BASE (th_vsxh) +BASE (th_vsxw) +BASE (th_vsuxb) +BASE (th_vsuxh) +BASE (th_vsuxw) +BASE (th_vext_x_v) /* Crypto vector */ BASE (vandn) BASE (vbrev) diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.h b/gcc/config/riscv/riscv-vector-builtins-bases.h index 1122e3801a7..df43adf9a17 100644 --- a/gcc/config/riscv/riscv-vector-builtins-bases.h +++ b/gcc/config/riscv/riscv-vector-builtins-bases.h @@ -299,6 +299,37 @@ extern const function_base *const vloxseg; extern const function_base *const vsuxseg; extern const function_base *const vsoxseg; extern const function_base *const vlsegff; +extern const function_base *const th_vlb; +extern const function_base *const th_vlh; +extern const function_base *const th_vlw; +extern const function_base *const th_vlbu; +extern const function_base *const th_vlhu; +extern const function_base *const th_vlwu; +extern const function_base *const th_vsb; +extern const function_base *const th_vsh; +extern const function_base *const th_vsw; +extern const function_base *const th_vlsb; +extern const function_base *const th_vlsh; +extern const function_base *const th_vlsw; +extern const function_base *const th_vlsbu; +extern const function_base *const th_vlshu; +extern const function_base *const th_vlswu; +extern const function_base *const th_vssb; +extern const function_base *const th_vssh; +extern const function_base *const th_vssw; +extern const function_base *const th_vlxb; +extern const function_base *const th_vlxh; +extern const function_base *const th_vlxw; +extern const function_base *const th_vlxbu; +extern const function_base *const th_vlxhu; +extern const function_base *const th_vlxwu; +extern const function_base *const th_vsxb; +extern const function_base *const th_vsxh; +extern const function_base *const th_vsxw; +extern const function_base *const th_vsuxb; +extern const function_base *const th_vsuxh; +extern const function_base *const th_vsuxw; +extern const function_base *const th_vext_x_v; /* Below function_base are Vectro Crypto*/ extern const function_base *const vandn; extern const function_base *const vbrev; diff --git a/gcc/config/riscv/riscv-vector-builtins-shapes.cc b/gcc/config/riscv/riscv-vector-builtins-shapes.cc index 1e4f4d53de6..489a95cf684 100644 --- a/gcc/config/riscv/riscv-vector-builtins-shapes.cc +++ b/gcc/config/riscv/riscv-vector-builtins-shapes.cc @@ -211,6 +211,86 @@ struct indexed_loadstore_def : public function_shape } }; +/* th_loadstore_width_def class. */ +struct th_loadstore_width_def : public build_base +{ + char *get_name (function_builder &b, const function_instance &instance, + bool overloaded_p) const override + { + /* Return nullptr if it can not be overloaded. */ + if (overloaded_p && !instance.base->can_be_overloaded_p (instance.pred)) + return nullptr; + + b.append_base_name (instance.base_name); + + /* vop_v --> vop_v_. */ + if (!overloaded_p) + { + /* vop --> vop_v. */ + b.append_name (operand_suffixes[instance.op_info->op]); + /* vop_v --> vop_v_. */ + b.append_name (type_suffixes[instance.type.index].vector); + } + + /* According to rvv-intrinsic-doc, it does not add "_m" suffix + for vop_m C++ overloaded API. */ + if (overloaded_p && instance.pred == PRED_TYPE_m) + return b.finish_name (); + b.append_name (predication_suffixes[instance.pred]); + return b.finish_name (); + } +}; + + +/* th_indexed_loadstore_width_def class. */ +struct th_indexed_loadstore_width_def : public function_shape +{ + void build (function_builder &b, + const function_group_info &group) const override + { + for (unsigned int pred_idx = 0; group.preds[pred_idx] != NUM_PRED_TYPES; + ++pred_idx) + { + for (unsigned int vec_type_idx = 0; + group.ops_infos.types[vec_type_idx].index != NUM_VECTOR_TYPES; + ++vec_type_idx) + { + tree index_type = group.ops_infos.args[1].get_tree_type ( + group.ops_infos.types[vec_type_idx].index); + if (!index_type) + continue; + build_one (b, group, pred_idx, vec_type_idx); + } + } + } + + char *get_name (function_builder &b, const function_instance &instance, + bool overloaded_p) const override + { + + /* Return nullptr if it can not be overloaded. */ + if (overloaded_p && !instance.base->can_be_overloaded_p (instance.pred)) + return nullptr; + + b.append_base_name (instance.base_name); + /* vop_v --> vop_v_. */ + if (!overloaded_p) + { + /* vop --> vop_v. */ + b.append_name (operand_suffixes[instance.op_info->op]); + /* vop_v --> vop_v_. */ + b.append_name (type_suffixes[instance.type.index].vector); + } + + /* According to rvv-intrinsic-doc, it does not add "_m" suffix + for vop_m C++ overloaded API. */ + if (overloaded_p && instance.pred == PRED_TYPE_m) + return b.finish_name (); + b.append_name (predication_suffixes[instance.pred]); + return b.finish_name (); + } +}; + /* alu_def class. */ struct alu_def : public build_base { @@ -632,6 +712,21 @@ struct reduc_alu_def : public build_base } }; +/* th_extract_def class. */ +struct th_extract_def : public build_base +{ + char *get_name (function_builder &b, const function_instance &instance, + bool overloaded_p) const override + { + b.append_base_name (instance.base_name); + if (overloaded_p) + return b.finish_name (); + b.append_name (type_suffixes[instance.type.index].vector); + b.append_name (type_suffixes[instance.type.index].scalar); + return b.finish_name (); + } +}; + /* scalar_move_def class. */ struct scalar_move_def : public build_base { @@ -1094,6 +1189,8 @@ SHAPE(vsetvl, vsetvl) SHAPE(vsetvl, vsetvlmax) SHAPE(loadstore, loadstore) SHAPE(indexed_loadstore, indexed_loadstore) +SHAPE(th_loadstore_width, th_loadstore_width) +SHAPE(th_indexed_loadstore_width, th_indexed_loadstore_width) SHAPE(alu, alu) SHAPE(alu_frm, alu_frm) SHAPE(widen_alu, widen_alu) @@ -1106,6 +1203,7 @@ SHAPE(move, move) SHAPE(mask_alu, mask_alu) SHAPE(reduc_alu, reduc_alu) SHAPE(reduc_alu_frm, reduc_alu_frm) +SHAPE(th_extract, th_extract) SHAPE(scalar_move, scalar_move) SHAPE(vundefined, vundefined) SHAPE(misc, misc) diff --git a/gcc/config/riscv/riscv-vector-builtins-shapes.h b/gcc/config/riscv/riscv-vector-builtins-shapes.h index ac2a28ce017..a7624d0fabd 100644 --- a/gcc/config/riscv/riscv-vector-builtins-shapes.h +++ b/gcc/config/riscv/riscv-vector-builtins-shapes.h @@ -28,6 +28,8 @@ extern const function_shape *const vsetvl; extern const function_shape *const vsetvlmax; extern const function_shape *const loadstore; extern const function_shape *const indexed_loadstore; +extern const function_shape *const th_loadstore_width; +extern const function_shape *const th_indexed_loadstore_width; extern const function_shape *const alu; extern const function_shape *const alu_frm; extern const function_shape *const widen_alu; @@ -41,6 +43,7 @@ extern const function_shape *const mask_alu; extern const function_shape *const reduc_alu; extern const function_shape *const reduc_alu_frm; extern const function_shape *const scalar_move; +extern const function_shape *const th_extract; extern const function_shape *const vundefined; extern const function_shape *const misc; extern const function_shape *const vset; diff --git a/gcc/config/riscv/riscv-vector-builtins-types.def b/gcc/config/riscv/riscv-vector-builtins-types.def index 61019a56844..abfeb4fcd9b 100644 --- a/gcc/config/riscv/riscv-vector-builtins-types.def +++ b/gcc/config/riscv/riscv-vector-builtins-types.def @@ -24,12 +24,48 @@ along with GCC; see the file COPYING3. If not see #define DEF_RVV_I_OPS(TYPE, REQUIRE) #endif +/* Use "DEF_RVV_I8_OPS" macro include some signed integer (i8/i16/i32/i64) + which will be iterated and registered as intrinsic functions. */ +#ifndef DEF_RVV_I8_OPS +#define DEF_RVV_I8_OPS(TYPE, REQUIRE) +#endif + +/* Use "DEF_RVV_I16_OPS" macro include some signed integer (i16/i32/i64) + which will be iterated and registered as intrinsic functions. */ +#ifndef DEF_RVV_I16_OPS +#define DEF_RVV_I16_OPS(TYPE, REQUIRE) +#endif + +/* Use "DEF_RVV_I32_OPS" macro include some signed integer (i32/i64) + which will be iterated and registered as intrinsic functions. */ +#ifndef DEF_RVV_I32_OPS +#define DEF_RVV_I32_OPS(TYPE, REQUIRE) +#endif + /* Use "DEF_RVV_U_OPS" macro include all unsigned integer which will be iterated and registered as intrinsic functions. */ #ifndef DEF_RVV_U_OPS #define DEF_RVV_U_OPS(TYPE, REQUIRE) #endif +/* Use "DEF_RVV_U8_OPS" macro include some unsigned integer (i8/i16/i32/i64) + which will be iterated and registered as intrinsic functions. */ +#ifndef DEF_RVV_U8_OPS +#define DEF_RVV_U8_OPS(TYPE, REQUIRE) +#endif + +/* Use "DEF_RVV_U16_OPS" macro include some unsigned integer (i16/i32/i64) + which will be iterated and registered as intrinsic functions. */ +#ifndef DEF_RVV_U16_OPS +#define DEF_RVV_U16_OPS(TYPE, REQUIRE) +#endif + +/* Use "DEF_RVV_U32_OPS" macro include some unsigned integer (i32/i64) + which will be iterated and registered as intrinsic functions. */ +#ifndef DEF_RVV_U32_OPS +#define DEF_RVV_U32_OPS(TYPE, REQUIRE) +#endif + /* Use "DEF_RVV_F_OPS" macro include all floating-point which will be iterated and registered as intrinsic functions. */ #ifndef DEF_RVV_F_OPS @@ -374,6 +410,45 @@ DEF_RVV_I_OPS (vint64m2_t, RVV_REQUIRE_ELEN_64) DEF_RVV_I_OPS (vint64m4_t, RVV_REQUIRE_ELEN_64) DEF_RVV_I_OPS (vint64m8_t, RVV_REQUIRE_ELEN_64) +DEF_RVV_I8_OPS (vint8m1_t, 0) +DEF_RVV_I8_OPS (vint8m2_t, 0) +DEF_RVV_I8_OPS (vint8m4_t, 0) +DEF_RVV_I8_OPS (vint8m8_t, 0) +DEF_RVV_I8_OPS (vint16m1_t, 0) +DEF_RVV_I8_OPS (vint16m2_t, 0) +DEF_RVV_I8_OPS (vint16m4_t, 0) +DEF_RVV_I8_OPS (vint16m8_t, 0) +DEF_RVV_I8_OPS (vint32m1_t, 0) +DEF_RVV_I8_OPS (vint32m2_t, 0) +DEF_RVV_I8_OPS (vint32m4_t, 0) +DEF_RVV_I8_OPS (vint32m8_t, 0) +DEF_RVV_I8_OPS (vint64m1_t, RVV_REQUIRE_ELEN_64) +DEF_RVV_I8_OPS (vint64m2_t, RVV_REQUIRE_ELEN_64) +DEF_RVV_I8_OPS (vint64m4_t, RVV_REQUIRE_ELEN_64) +DEF_RVV_I8_OPS (vint64m8_t, RVV_REQUIRE_ELEN_64) + +DEF_RVV_I16_OPS (vint16m1_t, 0) +DEF_RVV_I16_OPS (vint16m2_t, 0) +DEF_RVV_I16_OPS (vint16m4_t, 0) +DEF_RVV_I16_OPS (vint16m8_t, 0) +DEF_RVV_I16_OPS (vint32m1_t, 0) +DEF_RVV_I16_OPS (vint32m2_t, 0) +DEF_RVV_I16_OPS (vint32m4_t, 0) +DEF_RVV_I16_OPS (vint32m8_t, 0) +DEF_RVV_I16_OPS (vint64m1_t, RVV_REQUIRE_ELEN_64) +DEF_RVV_I16_OPS (vint64m2_t, RVV_REQUIRE_ELEN_64) +DEF_RVV_I16_OPS (vint64m4_t, RVV_REQUIRE_ELEN_64) +DEF_RVV_I16_OPS (vint64m8_t, RVV_REQUIRE_ELEN_64) + +DEF_RVV_I32_OPS (vint32m1_t, 0) +DEF_RVV_I32_OPS (vint32m2_t, 0) +DEF_RVV_I32_OPS (vint32m4_t, 0) +DEF_RVV_I32_OPS (vint32m8_t, 0) +DEF_RVV_I32_OPS (vint64m1_t, RVV_REQUIRE_ELEN_64) +DEF_RVV_I32_OPS (vint64m2_t, RVV_REQUIRE_ELEN_64) +DEF_RVV_I32_OPS (vint64m4_t, RVV_REQUIRE_ELEN_64) +DEF_RVV_I32_OPS (vint64m8_t, RVV_REQUIRE_ELEN_64) + DEF_RVV_U_OPS (vuint8mf8_t, RVV_REQUIRE_MIN_VLEN_64) DEF_RVV_U_OPS (vuint8mf4_t, 0) DEF_RVV_U_OPS (vuint8mf2_t, 0) @@ -397,6 +472,45 @@ DEF_RVV_U_OPS (vuint64m2_t, RVV_REQUIRE_ELEN_64) DEF_RVV_U_OPS (vuint64m4_t, RVV_REQUIRE_ELEN_64) DEF_RVV_U_OPS (vuint64m8_t, RVV_REQUIRE_ELEN_64) +DEF_RVV_U8_OPS (vuint8m1_t, 0) +DEF_RVV_U8_OPS (vuint8m2_t, 0) +DEF_RVV_U8_OPS (vuint8m4_t, 0) +DEF_RVV_U8_OPS (vuint8m8_t, 0) +DEF_RVV_U8_OPS (vuint16m1_t, 0) +DEF_RVV_U8_OPS (vuint16m2_t, 0) +DEF_RVV_U8_OPS (vuint16m4_t, 0) +DEF_RVV_U8_OPS (vuint16m8_t, 0) +DEF_RVV_U8_OPS (vuint32m1_t, 0) +DEF_RVV_U8_OPS (vuint32m2_t, 0) +DEF_RVV_U8_OPS (vuint32m4_t, 0) +DEF_RVV_U8_OPS (vuint32m8_t, 0) +DEF_RVV_U8_OPS (vuint64m1_t, RVV_REQUIRE_ELEN_64) +DEF_RVV_U8_OPS (vuint64m2_t, RVV_REQUIRE_ELEN_64) +DEF_RVV_U8_OPS (vuint64m4_t, RVV_REQUIRE_ELEN_64) +DEF_RVV_U8_OPS (vuint64m8_t, RVV_REQUIRE_ELEN_64) + +DEF_RVV_U16_OPS (vuint16m1_t, 0) +DEF_RVV_U16_OPS (vuint16m2_t, 0) +DEF_RVV_U16_OPS (vuint16m4_t, 0) +DEF_RVV_U16_OPS (vuint16m8_t, 0) +DEF_RVV_U16_OPS (vuint32m1_t, 0) +DEF_RVV_U16_OPS (vuint32m2_t, 0) +DEF_RVV_U16_OPS (vuint32m4_t, 0) +DEF_RVV_U16_OPS (vuint32m8_t, 0) +DEF_RVV_U16_OPS (vuint64m1_t, RVV_REQUIRE_ELEN_64) +DEF_RVV_U16_OPS (vuint64m2_t, RVV_REQUIRE_ELEN_64) +DEF_RVV_U16_OPS (vuint64m4_t, RVV_REQUIRE_ELEN_64) +DEF_RVV_U16_OPS (vuint64m8_t, RVV_REQUIRE_ELEN_64) + +DEF_RVV_U32_OPS (vuint32m1_t, 0) +DEF_RVV_U32_OPS (vuint32m2_t, 0) +DEF_RVV_U32_OPS (vuint32m4_t, 0) +DEF_RVV_U32_OPS (vuint32m8_t, 0) +DEF_RVV_U32_OPS (vuint64m1_t, RVV_REQUIRE_ELEN_64) +DEF_RVV_U32_OPS (vuint64m2_t, RVV_REQUIRE_ELEN_64) +DEF_RVV_U32_OPS (vuint64m4_t, RVV_REQUIRE_ELEN_64) +DEF_RVV_U32_OPS (vuint64m8_t, RVV_REQUIRE_ELEN_64) + DEF_RVV_F_OPS (vfloat16mf4_t, RVV_REQUIRE_ELEN_FP_16 | RVV_REQUIRE_MIN_VLEN_64) DEF_RVV_F_OPS (vfloat16mf2_t, RVV_REQUIRE_ELEN_FP_16) DEF_RVV_F_OPS (vfloat16m1_t, RVV_REQUIRE_ELEN_FP_16) @@ -1379,7 +1493,13 @@ DEF_RVV_CRYPTO_SEW64_OPS (vuint64m4_t, RVV_REQUIRE_ELEN_64) DEF_RVV_CRYPTO_SEW64_OPS (vuint64m8_t, RVV_REQUIRE_ELEN_64) #undef DEF_RVV_I_OPS +#undef DEF_RVV_I8_OPS +#undef DEF_RVV_I16_OPS +#undef DEF_RVV_I32_OPS #undef DEF_RVV_U_OPS +#undef DEF_RVV_U8_OPS +#undef DEF_RVV_U16_OPS +#undef DEF_RVV_U32_OPS #undef DEF_RVV_F_OPS #undef DEF_RVV_B_OPS #undef DEF_RVV_WEXTI_OPS diff --git a/gcc/config/riscv/riscv-vector-builtins.cc b/gcc/config/riscv/riscv-vector-builtins.cc index 25e0b6e56de..f429f12dc18 100644 --- a/gcc/config/riscv/riscv-vector-builtins.cc +++ b/gcc/config/riscv/riscv-vector-builtins.cc @@ -246,6 +246,63 @@ static const rvv_type_info iu_ops[] = { #include "riscv-vector-builtins-types.def" {NUM_VECTOR_TYPES, 0}}; +/* A list of all integer will be registered for intrinsic functions. */ +static const rvv_type_info i8_ops[] = { +#define DEF_RVV_I8_OPS(TYPE, REQUIRE) {VECTOR_TYPE_##TYPE, REQUIRE}, +#include "riscv-vector-builtins-types.def" + {NUM_VECTOR_TYPES, 0}}; + +/* A list of all integer will be registered for intrinsic functions. */ +static const rvv_type_info i16_ops[] = { +#define DEF_RVV_I16_OPS(TYPE, REQUIRE) {VECTOR_TYPE_##TYPE, REQUIRE}, +#include "riscv-vector-builtins-types.def" + {NUM_VECTOR_TYPES, 0}}; + +/* A list of all integer will be registered for intrinsic functions. */ +static const rvv_type_info i32_ops[] = { +#define DEF_RVV_I32_OPS(TYPE, REQUIRE) {VECTOR_TYPE_##TYPE, REQUIRE}, +#include "riscv-vector-builtins-types.def" + {NUM_VECTOR_TYPES, 0}}; + +/* A list of all integer will be registered for intrinsic functions. */ +static const rvv_type_info u8_ops[] = { +#define DEF_RVV_U8_OPS(TYPE, REQUIRE) {VECTOR_TYPE_##TYPE, REQUIRE}, +#include "riscv-vector-builtins-types.def" + {NUM_VECTOR_TYPES, 0}}; + +/* A list of all integer will be registered for intrinsic functions. */ +static const rvv_type_info u16_ops[] = { +#define DEF_RVV_U16_OPS(TYPE, REQUIRE) {VECTOR_TYPE_##TYPE, REQUIRE}, +#include "riscv-vector-builtins-types.def" + {NUM_VECTOR_TYPES, 0}}; + +/* A list of all integer will be registered for intrinsic functions. */ +static const rvv_type_info u32_ops[] = { +#define DEF_RVV_U32_OPS(TYPE, REQUIRE) {VECTOR_TYPE_##TYPE, REQUIRE}, +#include "riscv-vector-builtins-types.def" + {NUM_VECTOR_TYPES, 0}}; + +/* A list of all integer will be registered for intrinsic functions. */ +static const rvv_type_info iu8_ops[] = { +#define DEF_RVV_I8_OPS(TYPE, REQUIRE) {VECTOR_TYPE_##TYPE, REQUIRE}, +#define DEF_RVV_U8_OPS(TYPE, REQUIRE) {VECTOR_TYPE_##TYPE, REQUIRE}, +#include "riscv-vector-builtins-types.def" + {NUM_VECTOR_TYPES, 0}}; + +/* A list of all integer will be registered for intrinsic functions. */ +static const rvv_type_info iu16_ops[] = { +#define DEF_RVV_I16_OPS(TYPE, REQUIRE) {VECTOR_TYPE_##TYPE, REQUIRE}, +#define DEF_RVV_U16_OPS(TYPE, REQUIRE) {VECTOR_TYPE_##TYPE, REQUIRE}, +#include "riscv-vector-builtins-types.def" + {NUM_VECTOR_TYPES, 0}}; + +/* A list of all integer will be registered for intrinsic functions. */ +static const rvv_type_info iu32_ops[] = { +#define DEF_RVV_I32_OPS(TYPE, REQUIRE) {VECTOR_TYPE_##TYPE, REQUIRE}, +#define DEF_RVV_U32_OPS(TYPE, REQUIRE) {VECTOR_TYPE_##TYPE, REQUIRE}, +#include "riscv-vector-builtins-types.def" + {NUM_VECTOR_TYPES, 0}}; + /* A list of all types will be registered for intrinsic functions. */ static const rvv_type_info all_ops[] = { #define DEF_RVV_I_OPS(TYPE, REQUIRE) {VECTOR_TYPE_##TYPE, REQUIRE}, @@ -934,6 +991,32 @@ static CONSTEXPR const rvv_arg_type_info ext_vcreate_args[] = {rvv_arg_type_info (RVV_BASE_vector), rvv_arg_type_info_end}; +/* A list of args for vector_type func (const scalar_type *, size_t) + * function. */ +static CONSTEXPR const rvv_arg_type_info scalar_const_ptr_size_args[] + = {rvv_arg_type_info (RVV_BASE_scalar_const_ptr), + rvv_arg_type_info (RVV_BASE_size), rvv_arg_type_info_end}; + +/* A list of args for vector_type func (const scalar_type *, eew8_index_type) + * function. */ +static CONSTEXPR const rvv_arg_type_info scalar_const_ptr_index_args[] + = {rvv_arg_type_info (RVV_BASE_scalar_const_ptr), + rvv_arg_type_info (RVV_BASE_unsigned_vector), rvv_arg_type_info_end}; + +/* A list of args for void func (scalar_type *, eew8_index_type, vector_type) + * function. */ +static CONSTEXPR const rvv_arg_type_info scalar_ptr_index_args[] + = {rvv_arg_type_info (RVV_BASE_scalar_ptr), + rvv_arg_type_info (RVV_BASE_unsigned_vector), + rvv_arg_type_info (RVV_BASE_vector), rvv_arg_type_info_end}; + +/* A list of args for void func (scalar_type *, size_t, vector_type) + * function. */ +static CONSTEXPR const rvv_arg_type_info scalar_ptr_size_args[] + = {rvv_arg_type_info (RVV_BASE_scalar_ptr), + rvv_arg_type_info (RVV_BASE_size), rvv_arg_type_info (RVV_BASE_vector), + rvv_arg_type_info_end}; + /* A list of none preds that will be registered for intrinsic functions. */ static CONSTEXPR const predication_type_index none_preds[] = {PRED_TYPE_none, NUM_PRED_TYPES}; @@ -1455,6 +1538,14 @@ static CONSTEXPR const rvv_op_info iu_shift_vvv_ops rvv_arg_type_info (RVV_BASE_vector), /* Return type */ shift_vv_args /* Args */}; +/* A static operand information for scalar_type func (vector_type, size_t) + * function registration. */ +static CONSTEXPR const rvv_op_info iu_x_s_u_ops + = {iu_ops, /* Types */ + OP_TYPE_vx, /* Suffix */ + rvv_arg_type_info (RVV_BASE_scalar), /* Return type */ + v_size_args /* Args */}; + /* A static operand information for vector_type func (vector_type, size_t) * function registration. */ static CONSTEXPR const rvv_op_info iu_shift_vvx_ops @@ -2638,6 +2729,222 @@ static CONSTEXPR const rvv_op_info all_v_vcreate_lmul4_x2_ops rvv_arg_type_info (RVV_BASE_vlmul_ext_x2), /* Return type */ ext_vcreate_args /* Args */}; +/* A static operand information for vector_type func (const scalar_type *) + * function registration. */ +static CONSTEXPR const rvv_op_info i8_v_scalar_const_ptr_ops + = {i8_ops, /* Types */ + OP_TYPE_v, /* Suffix */ + rvv_arg_type_info (RVV_BASE_vector), /* Return type */ + scalar_const_ptr_args /* Args */}; + +/* A static operand information for vector_type func (const scalar_type *) + * function registration. */ +static CONSTEXPR const rvv_op_info i16_v_scalar_const_ptr_ops + = {i16_ops, /* Types */ + OP_TYPE_v, /* Suffix */ + rvv_arg_type_info (RVV_BASE_vector), /* Return type */ + scalar_const_ptr_args /* Args */}; + +/* A static operand information for vector_type func (const scalar_type *) + * function registration. */ +static CONSTEXPR const rvv_op_info i32_v_scalar_const_ptr_ops + = {i32_ops, /* Types */ + OP_TYPE_v, /* Suffix */ + rvv_arg_type_info (RVV_BASE_vector), /* Return type */ + scalar_const_ptr_args /* Args */}; + +/* A static operand information for vector_type func (const scalar_type *) + * function registration. */ +static CONSTEXPR const rvv_op_info u8_v_scalar_const_ptr_ops + = {u8_ops, /* Types */ + OP_TYPE_v, /* Suffix */ + rvv_arg_type_info (RVV_BASE_vector), /* Return type */ + scalar_const_ptr_args /* Args */}; + +/* A static operand information for vector_type func (const scalar_type *) + * function registration. */ +static CONSTEXPR const rvv_op_info u16_v_scalar_const_ptr_ops + = {u16_ops, /* Types */ + OP_TYPE_v, /* Suffix */ + rvv_arg_type_info (RVV_BASE_vector), /* Return type */ + scalar_const_ptr_args /* Args */}; + +/* A static operand information for vector_type func (const scalar_type *) + * function registration. */ +static CONSTEXPR const rvv_op_info u32_v_scalar_const_ptr_ops + = {u32_ops, /* Types */ + OP_TYPE_v, /* Suffix */ + rvv_arg_type_info (RVV_BASE_vector), /* Return type */ + scalar_const_ptr_args /* Args */}; + +/* A static operand information for vector_type func (const scalar_type *, + * size_t) function registration. */ +static CONSTEXPR const rvv_op_info i8_v_scalar_const_ptr_size_ops + = {i8_ops, /* Types */ + OP_TYPE_v, /* Suffix */ + rvv_arg_type_info (RVV_BASE_vector), /* Return type */ + scalar_const_ptr_size_args /* Args */}; + +/* A static operand information for vector_type func (const scalar_type *, + * size_t) function registration. */ +static CONSTEXPR const rvv_op_info i16_v_scalar_const_ptr_size_ops + = {i16_ops, /* Types */ + OP_TYPE_v, /* Suffix */ + rvv_arg_type_info (RVV_BASE_vector), /* Return type */ + scalar_const_ptr_size_args /* Args */}; + +/* A static operand information for vector_type func (const scalar_type *, + * size_t) function registration. */ +static CONSTEXPR const rvv_op_info i32_v_scalar_const_ptr_size_ops + = {i32_ops, /* Types */ + OP_TYPE_v, /* Suffix */ + rvv_arg_type_info (RVV_BASE_vector), /* Return type */ + scalar_const_ptr_size_args /* Args */}; + +/* A static operand information for vector_type func (const scalar_type *, + * size_t) function registration. */ +static CONSTEXPR const rvv_op_info u8_v_scalar_const_ptr_size_ops + = {u8_ops, /* Types */ + OP_TYPE_v, /* Suffix */ + rvv_arg_type_info (RVV_BASE_vector), /* Return type */ + scalar_const_ptr_size_args /* Args */}; + +/* A static operand information for vector_type func (const scalar_type *, + * size_t) function registration. */ +static CONSTEXPR const rvv_op_info u16_v_scalar_const_ptr_size_ops + = {u16_ops, /* Types */ + OP_TYPE_v, /* Suffix */ + rvv_arg_type_info (RVV_BASE_vector), /* Return type */ + scalar_const_ptr_size_args /* Args */}; + +/* A static operand information for vector_type func (const scalar_type *, + * size_t) function registration. */ +static CONSTEXPR const rvv_op_info u32_v_scalar_const_ptr_size_ops + = {u32_ops, /* Types */ + OP_TYPE_v, /* Suffix */ + rvv_arg_type_info (RVV_BASE_vector), /* Return type */ + scalar_const_ptr_size_args /* Args */}; + +/* A static operand information for vector_type func (const scalar_type *, + * eew8_index_type) function registration. */ +static CONSTEXPR const rvv_op_info i8_v_scalar_const_ptr_index_ops + = {i8_ops, /* Types */ + OP_TYPE_v, /* Suffix */ + rvv_arg_type_info (RVV_BASE_vector), /* Return type */ + scalar_const_ptr_index_args /* Args */}; + +/* A static operand information for vector_type func (const scalar_type *, + * eew8_index_type) function registration. */ +static CONSTEXPR const rvv_op_info u8_v_scalar_const_ptr_index_ops + = {u8_ops, /* Types */ + OP_TYPE_v, /* Suffix */ + rvv_arg_type_info (RVV_BASE_vector), /* Return type */ + scalar_const_ptr_index_args /* Args */}; + +/* A static operand information for vector_type func (const scalar_type *, + * eew8_index_type) function registration. */ +static CONSTEXPR const rvv_op_info i16_v_scalar_const_ptr_index_ops + = {i16_ops, /* Types */ + OP_TYPE_v, /* Suffix */ + rvv_arg_type_info (RVV_BASE_vector), /* Return type */ + scalar_const_ptr_index_args /* Args */}; + +/* A static operand information for vector_type func (const scalar_type *, + * eew8_index_type) function registration. */ +static CONSTEXPR const rvv_op_info u16_v_scalar_const_ptr_index_ops + = {u16_ops, /* Types */ + OP_TYPE_v, /* Suffix */ + rvv_arg_type_info (RVV_BASE_vector), /* Return type */ + scalar_const_ptr_index_args /* Args */}; + +/* A static operand information for vector_type func (const scalar_type *, + * eew8_index_type) function registration. */ +static CONSTEXPR const rvv_op_info i32_v_scalar_const_ptr_index_ops + = {i32_ops, /* Types */ + OP_TYPE_v, /* Suffix */ + rvv_arg_type_info (RVV_BASE_vector), /* Return type */ + scalar_const_ptr_index_args /* Args */}; + +/* A static operand information for vector_type func (const scalar_type *, + * eew8_index_type) function registration. */ +static CONSTEXPR const rvv_op_info u32_v_scalar_const_ptr_index_ops + = {u32_ops, /* Types */ + OP_TYPE_v, /* Suffix */ + rvv_arg_type_info (RVV_BASE_vector), /* Return type */ + scalar_const_ptr_index_args /* Args */}; + +/* A static operand information for void func (scalar_type *, eew8_index_type, + * vector_type) function registration. */ +static CONSTEXPR const rvv_op_info iu8_v_scalar_ptr_index_ops + = {iu8_ops, /* Types */ + OP_TYPE_v, /* Suffix */ + rvv_arg_type_info (RVV_BASE_void), /* Return type */ + scalar_ptr_index_args /* Args */}; + +/* A static operand information for void func (scalar_type *, eew16_index_type, + * vector_type) function registration. */ +static CONSTEXPR const rvv_op_info iu16_v_scalar_ptr_index_ops + = {iu16_ops, /* Types */ + OP_TYPE_v, /* Suffix */ + rvv_arg_type_info (RVV_BASE_void), /* Return type */ + scalar_ptr_index_args /* Args */}; + +/* A static operand information for void func (scalar_type *, eew32_index_type, + * vector_type) function registration. */ +static CONSTEXPR const rvv_op_info iu32_v_scalar_ptr_index_ops + = {iu32_ops, /* Types */ + OP_TYPE_v, /* Suffix */ + rvv_arg_type_info (RVV_BASE_void), /* Return type */ + scalar_ptr_index_args /* Args */}; + +/* A static operand information for void func (scalar_type *, vector_type, + * function registration. */ +static CONSTEXPR const rvv_op_info iu8_v_scalar_ptr_ops + = {iu8_ops, /* Types */ + OP_TYPE_v, /* Suffix */ + rvv_arg_type_info (RVV_BASE_void), /* Return type */ + scalar_ptr_args /* Args */}; + +/* A static operand information for void func (scalar_type *, vector_type) + * function registration. */ +static CONSTEXPR const rvv_op_info iu16_v_scalar_ptr_ops + = {iu16_ops, /* Types */ + OP_TYPE_v, /* Suffix */ + rvv_arg_type_info (RVV_BASE_void), /* Return type */ + scalar_ptr_args /* Args */}; + +/* A static operand information for void func (scalar_type *, vector_type) + * function registration. */ +static CONSTEXPR const rvv_op_info iu32_v_scalar_ptr_ops + = {iu32_ops, /* Types */ + OP_TYPE_v, /* Suffix */ + rvv_arg_type_info (RVV_BASE_void), /* Return type */ + scalar_ptr_args /* Args */}; + +/* A static operand information for void func (scalar_type *, size_t, + * vector_type) function registration. */ +static CONSTEXPR const rvv_op_info iu8_v_scalar_ptr_size_ops + = {iu8_ops, /* Types */ + OP_TYPE_v, /* Suffix */ + rvv_arg_type_info (RVV_BASE_void), /* Return type */ + scalar_ptr_size_args /* Args */}; + +/* A static operand information for void func (scalar_type *, size_t, + * vector_type) function registration. */ +static CONSTEXPR const rvv_op_info iu16_v_scalar_ptr_size_ops + = {iu16_ops, /* Types */ + OP_TYPE_v, /* Suffix */ + rvv_arg_type_info (RVV_BASE_void), /* Return type */ + scalar_ptr_size_args /* Args */}; + +/* A static operand information for void func (scalar_type *, size_t, + * vector_type) function registration. */ +static CONSTEXPR const rvv_op_info iu32_v_scalar_ptr_size_ops + = {iu32_ops, /* Types */ + OP_TYPE_v, /* Suffix */ + rvv_arg_type_info (RVV_BASE_void), /* Return type */ + scalar_ptr_size_args /* Args */}; + /* A static operand information for vector_type func (vector_type). Some ins just supports SEW=32, such as crypto vectol Zvkg extension. * function registration. */ @@ -2816,6 +3123,10 @@ static function_group_info function_groups[] = { #define DEF_RVV_FUNCTION(NAME, SHAPE, PREDS, OPS_INFO) \ {#NAME, &bases::NAME, &shapes::SHAPE, PREDS, OPS_INFO, REQUIRED_EXTENSIONS}, #include "riscv-vector-builtins-functions.def" +#undef DEF_RVV_FUNCTION +#define DEF_RVV_FUNCTION(NAME, SHAPE, PREDS, OPS_INFO) \ + {#NAME, &bases::NAME, &shapes::SHAPE, PREDS, OPS_INFO, REQUIRED_EXTENSIONS}, +#include "thead-vector-builtins-functions.def" }; /* The RVV types, with their built-in diff --git a/gcc/config/riscv/riscv-vector-builtins.h b/gcc/config/riscv/riscv-vector-builtins.h index 54c8824ff92..a8ee39a3cb2 100644 --- a/gcc/config/riscv/riscv-vector-builtins.h +++ b/gcc/config/riscv/riscv-vector-builtins.h @@ -114,6 +114,7 @@ static const unsigned int CP_WRITE_CSR = 1U << 5; enum required_ext { VECTOR_EXT, /* Vector extension */ + XTHEADVECTOR_EXT, /* XTheadVector extension */ ZVBB_EXT, /* Cryto vector Zvbb sub-ext */ ZVBB_OR_ZVKB_EXT, /* Cryto vector Zvbb or zvkb sub-ext */ ZVBC_EXT, /* Crypto vector Zvbc sub-ext */ @@ -234,6 +235,8 @@ struct function_group_info { case VECTOR_EXT: return TARGET_VECTOR; + case XTHEADVECTOR_EXT: + return TARGET_XTHEADVECTOR; case ZVBB_EXT: return TARGET_ZVBB; case ZVBB_OR_ZVKB_EXT: diff --git a/gcc/config/riscv/t-riscv b/gcc/config/riscv/t-riscv index 32de6b851c1..38494320d8b 100644 --- a/gcc/config/riscv/t-riscv +++ b/gcc/config/riscv/t-riscv @@ -1,6 +1,7 @@ RISCV_BUILTINS_H = $(srcdir)/config/riscv/riscv-vector-builtins.h \ $(srcdir)/config/riscv/riscv-vector-builtins.def \ $(srcdir)/config/riscv/riscv-vector-builtins-functions.def \ + $(srcdir)/config/riscv/thead-vector-builtins-functions.def \ riscv-vector-type-indexer.gen.def riscv-builtins.o: $(srcdir)/config/riscv/riscv-builtins.cc $(CONFIG_H) \ diff --git a/gcc/config/riscv/thead-vector-builtins-functions.def b/gcc/config/riscv/thead-vector-builtins-functions.def new file mode 100644 index 00000000000..667820d4c3e --- /dev/null +++ b/gcc/config/riscv/thead-vector-builtins-functions.def @@ -0,0 +1,39 @@ +#ifndef DEF_RVV_FUNCTION +#define DEF_RVV_FUNCTION(NAME, SHAPE, PREDS, OPS_INFO) +#endif + +#define REQUIRED_EXTENSIONS XTHEADVECTOR_EXT +DEF_RVV_FUNCTION (th_vlb, th_loadstore_width, full_preds, i8_v_scalar_const_ptr_ops) +DEF_RVV_FUNCTION (th_vlh, th_loadstore_width, full_preds, i16_v_scalar_const_ptr_ops) +DEF_RVV_FUNCTION (th_vlw, th_loadstore_width, full_preds, i32_v_scalar_const_ptr_ops) +DEF_RVV_FUNCTION (th_vlbu, th_loadstore_width, full_preds, u8_v_scalar_const_ptr_ops) +DEF_RVV_FUNCTION (th_vlhu, th_loadstore_width, full_preds, u16_v_scalar_const_ptr_ops) +DEF_RVV_FUNCTION (th_vlwu, th_loadstore_width, full_preds, u32_v_scalar_const_ptr_ops) +DEF_RVV_FUNCTION (th_vsb, th_loadstore_width, none_m_preds, iu8_v_scalar_ptr_ops) +DEF_RVV_FUNCTION (th_vsh, th_loadstore_width, none_m_preds, iu16_v_scalar_ptr_ops) +DEF_RVV_FUNCTION (th_vsw, th_loadstore_width, none_m_preds, iu32_v_scalar_ptr_ops) +DEF_RVV_FUNCTION (th_vlsb, th_loadstore_width, full_preds, i8_v_scalar_const_ptr_size_ops) +DEF_RVV_FUNCTION (th_vlsh, th_loadstore_width, full_preds, i16_v_scalar_const_ptr_size_ops) +DEF_RVV_FUNCTION (th_vlsw, th_loadstore_width, full_preds, i32_v_scalar_const_ptr_size_ops) +DEF_RVV_FUNCTION (th_vlsbu, th_loadstore_width, full_preds, u8_v_scalar_const_ptr_size_ops) +DEF_RVV_FUNCTION (th_vlshu, th_loadstore_width, full_preds, u16_v_scalar_const_ptr_size_ops) +DEF_RVV_FUNCTION (th_vlswu, th_loadstore_width, full_preds, u32_v_scalar_const_ptr_size_ops) +DEF_RVV_FUNCTION (th_vssb, th_loadstore_width, none_m_preds, iu8_v_scalar_ptr_size_ops) +DEF_RVV_FUNCTION (th_vssh, th_loadstore_width, none_m_preds, iu16_v_scalar_ptr_size_ops) +DEF_RVV_FUNCTION (th_vssw, th_loadstore_width, none_m_preds, iu32_v_scalar_ptr_size_ops) +DEF_RVV_FUNCTION (th_vlxb, th_indexed_loadstore_width, full_preds, i8_v_scalar_const_ptr_index_ops) +DEF_RVV_FUNCTION (th_vlxh, th_indexed_loadstore_width, full_preds, i16_v_scalar_const_ptr_index_ops) +DEF_RVV_FUNCTION (th_vlxw, th_indexed_loadstore_width, full_preds, i32_v_scalar_const_ptr_index_ops) +DEF_RVV_FUNCTION (th_vlxbu, th_indexed_loadstore_width, full_preds, u8_v_scalar_const_ptr_index_ops) +DEF_RVV_FUNCTION (th_vlxhu, th_indexed_loadstore_width, full_preds, u16_v_scalar_const_ptr_index_ops) +DEF_RVV_FUNCTION (th_vlxwu, th_indexed_loadstore_width, full_preds, u32_v_scalar_const_ptr_index_ops) +DEF_RVV_FUNCTION (th_vsxb, th_indexed_loadstore_width, none_m_preds, iu8_v_scalar_ptr_index_ops) +DEF_RVV_FUNCTION (th_vsxh, th_indexed_loadstore_width, none_m_preds, iu16_v_scalar_ptr_index_ops) +DEF_RVV_FUNCTION (th_vsxw, th_indexed_loadstore_width, none_m_preds, iu32_v_scalar_ptr_index_ops) +DEF_RVV_FUNCTION (th_vsuxb, th_indexed_loadstore_width, none_m_preds, iu8_v_scalar_ptr_index_ops) +DEF_RVV_FUNCTION (th_vsuxh, th_indexed_loadstore_width, none_m_preds, iu16_v_scalar_ptr_index_ops) +DEF_RVV_FUNCTION (th_vsuxw, th_indexed_loadstore_width, none_m_preds, iu32_v_scalar_ptr_index_ops) +DEF_RVV_FUNCTION (th_vext_x_v, th_extract, none_preds, iu_x_s_u_ops) +#undef REQUIRED_EXTENSIONS + +#undef DEF_RVV_FUNCTION diff --git a/gcc/config/riscv/thead-vector.md b/gcc/config/riscv/thead-vector.md index 696b815252d..0f3700d9269 100644 --- a/gcc/config/riscv/thead-vector.md +++ b/gcc/config/riscv/thead-vector.md @@ -1,7 +1,95 @@ (define_c_enum "unspec" [ + UNSPEC_TH_VLB + UNSPEC_TH_VLBU + UNSPEC_TH_VLH + UNSPEC_TH_VLHU + UNSPEC_TH_VLW + UNSPEC_TH_VLWU + + UNSPEC_TH_VLSB + UNSPEC_TH_VLSBU + UNSPEC_TH_VLSH + UNSPEC_TH_VLSHU + UNSPEC_TH_VLSW + UNSPEC_TH_VLSWU + + UNSPEC_TH_VLXB + UNSPEC_TH_VLXBU + UNSPEC_TH_VLXH + UNSPEC_TH_VLXHU + UNSPEC_TH_VLXW + UNSPEC_TH_VLXWU + + UNSPEC_TH_VSUXB + UNSPEC_TH_VSUXH + UNSPEC_TH_VSUXW + UNSPEC_TH_VWLDST ]) +(define_int_iterator UNSPEC_TH_VLMEM_OP [ + UNSPEC_TH_VLB UNSPEC_TH_VLBU + UNSPEC_TH_VLH UNSPEC_TH_VLHU + UNSPEC_TH_VLW UNSPEC_TH_VLWU +]) + +(define_int_iterator UNSPEC_TH_VLSMEM_OP [ + UNSPEC_TH_VLSB UNSPEC_TH_VLSBU + UNSPEC_TH_VLSH UNSPEC_TH_VLSHU + UNSPEC_TH_VLSW UNSPEC_TH_VLSWU +]) + +(define_int_iterator UNSPEC_TH_VLXMEM_OP [ + UNSPEC_TH_VLXB UNSPEC_TH_VLXBU + UNSPEC_TH_VLXH UNSPEC_TH_VLXHU + UNSPEC_TH_VLXW UNSPEC_TH_VLXWU +]) + +(define_int_attr vlmem_op_attr [ + (UNSPEC_TH_VLB "b") (UNSPEC_TH_VLBU "bu") + (UNSPEC_TH_VLH "h") (UNSPEC_TH_VLHU "hu") + (UNSPEC_TH_VLW "w") (UNSPEC_TH_VLWU "wu") + (UNSPEC_TH_VLSB "b") (UNSPEC_TH_VLSBU "bu") + (UNSPEC_TH_VLSH "h") (UNSPEC_TH_VLSHU "hu") + (UNSPEC_TH_VLSW "w") (UNSPEC_TH_VLSWU "wu") + (UNSPEC_TH_VLXB "b") (UNSPEC_TH_VLXBU "bu") + (UNSPEC_TH_VLXH "h") (UNSPEC_TH_VLXHU "hu") + (UNSPEC_TH_VLXW "w") (UNSPEC_TH_VLXWU "wu") + (UNSPEC_TH_VSUXB "b") + (UNSPEC_TH_VSUXH "h") + (UNSPEC_TH_VSUXW "w") +]) + +(define_int_attr vlmem_order_attr [ + (UNSPEC_TH_VLXB "") + (UNSPEC_TH_VLXH "") + (UNSPEC_TH_VLXW "") + (UNSPEC_TH_VSUXB "u") + (UNSPEC_TH_VSUXH "u") + (UNSPEC_TH_VSUXW "u") +]) + +(define_int_iterator UNSPEC_TH_VSMEM_OP [ + UNSPEC_TH_VLB + UNSPEC_TH_VLH + UNSPEC_TH_VLW +]) + +(define_int_iterator UNSPEC_TH_VSSMEM_OP [ + UNSPEC_TH_VLSB + UNSPEC_TH_VLSH + UNSPEC_TH_VLSW +]) + +(define_int_iterator UNSPEC_TH_VSXMEM_OP [ + UNSPEC_TH_VLXB + UNSPEC_TH_VLXH + UNSPEC_TH_VLXW + UNSPEC_TH_VSUXB + UNSPEC_TH_VSUXH + UNSPEC_TH_VSUXW +]) + (define_mode_iterator V_VLS_VT [V VLS VT]) (define_mode_iterator V_VB_VLS_VT [V VB VLS VT]) @@ -100,3 +188,168 @@ } [(set_attr "type" "vldm,vstm,vmalu,vmalu,vmalu") (set_attr "mode" "")]) + +(define_expand "@pred_mov_width" + [(set (match_operand:V_VLS 0 "nonimmediate_operand") + (if_then_else:V_VLS + (unspec: + [(match_operand: 1 "vector_mask_operand") + (match_operand 4 "vector_length_operand") + (match_operand 5 "const_int_operand") + (match_operand 6 "const_int_operand") + (match_operand 7 "const_int_operand") + (reg:SI VL_REGNUM) + (reg:SI VTYPE_REGNUM)] UNSPEC_TH_VLMEM_OP) + (match_operand:V_VLS 3 "vector_move_operand") + (match_operand:V_VLS 2 "vector_merge_operand")))] + "TARGET_XTHEADVECTOR" + {}) + +(define_insn_and_split "*pred_mov_width" + [(set (match_operand:V_VLS 0 "nonimmediate_operand" "=vr, vr, vd, m, vr, vr") + (if_then_else:V_VLS + (unspec: + [(match_operand: 1 "vector_mask_operand" "vmWc1, Wc1, vm, vmWc1, Wc1, Wc1") + (match_operand 4 "vector_length_operand" " rK, rK, rK, rK, rK, rK") + (match_operand 5 "const_int_operand" " i, i, i, i, i, i") + (match_operand 6 "const_int_operand" " i, i, i, i, i, i") + (match_operand 7 "const_int_operand" " i, i, i, i, i, i") + (reg:SI VL_REGNUM) + (reg:SI VTYPE_REGNUM)] UNSPEC_TH_VLMEM_OP) + (match_operand:V_VLS 3 "reg_or_mem_operand" " m, m, m, vr, vr, vr") + (match_operand:V_VLS 2 "vector_merge_operand" " 0, vu, vu, vu, vu, 0")))] + "(TARGET_XTHEADVECTOR + && (register_operand (operands[0], mode) + || register_operand (operands[3], mode)))" + "@ + vl.v\t%0,%3%p1 + vl.v\t%0,%3 + vl.v\t%0,%3,%1.t + vs.v\t%3,%0%p1 + vmv.v.v\t%0,%3 + vmv.v.v\t%0,%3" + "&& register_operand (operands[0], mode) + && register_operand (operands[3], mode) + && satisfies_constraint_vu (operands[2]) + && INTVAL (operands[7]) == riscv_vector::VLMAX" + [(set (match_dup 0) (match_dup 3))] + "" + [(set_attr "type" "vlde,vlde,vlde,vste,vimov,vimov") + (set_attr "mode" "")]) + +(define_insn "@pred_store_width" + [(set (match_operand:VI 0 "memory_operand" "+m") + (if_then_else:VI + (unspec: + [(match_operand: 1 "vector_mask_operand" "vmWc1") + (match_operand 3 "vector_length_operand" " rK") + (match_operand 4 "const_int_operand" " i") + (reg:SI VL_REGNUM) + (reg:SI VTYPE_REGNUM)] UNSPEC_TH_VSMEM_OP) + (match_operand:VI 2 "register_operand" " vr") + (match_dup 0)))] + "TARGET_XTHEADVECTOR" + "vs.v\t%2,%0%p1" + [(set_attr "type" "vste") + (set_attr "mode" "") + (set (attr "avl_type_idx") (const_int 4)) + (set_attr "vl_op_idx" "3")]) + +(define_insn "@pred_strided_load_width" + [(set (match_operand:VI 0 "register_operand" "=vr, vr, vd") + (if_then_else:VI + (unspec: + [(match_operand: 1 "vector_mask_operand" "vmWc1, Wc1, vm") + (match_operand 5 "vector_length_operand" " rK, rK, rK") + (match_operand 6 "const_int_operand" " i, i, i") + (match_operand 7 "const_int_operand" " i, i, i") + (match_operand 8 "const_int_operand" " i, i, i") + (reg:SI VL_REGNUM) + (reg:SI VTYPE_REGNUM)] UNSPEC_TH_VLSMEM_OP) + (unspec:VI + [(match_operand:VI 3 "memory_operand" " m, m, m") + (match_operand 4 "pmode_reg_or_0_operand" " rJ, rJ, rJ")] UNSPEC_TH_VLSMEM_OP) + (match_operand:VI 2 "vector_merge_operand" " 0, vu, vu")))] + "TARGET_XTHEADVECTOR" + "vls.v\t%0,%3,%z4%p1" + [(set_attr "type" "vlds") + (set_attr "mode" "")]) + +(define_insn "@pred_strided_store_width" + [(set (match_operand:VI 0 "memory_operand" "+m") + (if_then_else:VI + (unspec: + [(match_operand: 1 "vector_mask_operand" "vmWc1") + (match_operand 4 "vector_length_operand" " rK") + (match_operand 5 "const_int_operand" " i") + (reg:SI VL_REGNUM) + (reg:SI VTYPE_REGNUM)] UNSPEC_TH_VSSMEM_OP) + (unspec:VI + [(match_operand 2 "pmode_reg_or_0_operand" " rJ") + (match_operand:VI 3 "register_operand" " vr")] UNSPEC_TH_VSSMEM_OP) + (match_dup 0)))] + "TARGET_XTHEADVECTOR" + "vss.v\t%3,%0,%z2%p1" + [(set_attr "type" "vsts") + (set_attr "mode" "") + (set (attr "avl_type_idx") (const_int 5))]) + +(define_insn "@pred_indexed_load_width" + [(set (match_operand:VI 0 "register_operand" "=vd, vr,vd, vr") + (if_then_else:VI + (unspec: + [(match_operand: 1 "vector_mask_operand" " vm,Wc1,vm,Wc1") + (match_operand 5 "vector_length_operand" " rK, rK,rK, rK") + (match_operand 6 "const_int_operand" " i, i, i, i") + (match_operand 7 "const_int_operand" " i, i, i, i") + (match_operand 8 "const_int_operand" " i, i, i, i") + (reg:SI VL_REGNUM) + (reg:SI VTYPE_REGNUM)] UNSPEC_TH_VLXMEM_OP) + (unspec:VI + [(match_operand 3 "pmode_reg_or_0_operand" " rJ, rJ,rJ, rJ") + (mem:BLK (scratch)) + (match_operand:VI 4 "register_operand" " vr, vr,vr, vr")] UNSPEC_TH_VLXMEM_OP) + (match_operand:VI 2 "vector_merge_operand" " vu, vu, 0, 0")))] + "TARGET_XTHEADVECTOR" + "vlx.v\t%0,(%z3),%4%p1" + [(set_attr "type" "vldux") + (set_attr "mode" "")]) + +(define_insn "@pred_indexed_store_width" + [(set (mem:BLK (scratch)) + (unspec:BLK + [(unspec: + [(match_operand: 0 "vector_mask_operand" "vmWc1") + (match_operand 4 "vector_length_operand" " rK") + (match_operand 5 "const_int_operand" " i") + (reg:SI VL_REGNUM) + (reg:SI VTYPE_REGNUM)] UNSPEC_TH_VSXMEM_OP) + (match_operand 1 "pmode_reg_or_0_operand" " rJ") + (match_operand:VI 2 "register_operand" " vr") + (match_operand:VI 3 "register_operand" " vr")] UNSPEC_TH_VSXMEM_OP))] + "TARGET_XTHEADVECTOR" + "vsx.v\t%3,(%z1),%2%p0" + [(set_attr "type" "vstux") + (set_attr "mode" "")]) + +(define_expand "@pred_th_extract" + [(set (match_operand: 0 "register_operand") + (unspec: + [(vec_select: + (match_operand:V_VLSI 1 "register_operand") + (parallel [(match_operand:DI 2 "register_operand" "r")])) + (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE))] + "TARGET_XTHEADVECTOR" +{}) + +(define_insn "*pred_th_extract" + [(set (match_operand: 0 "register_operand" "=r") + (unspec: + [(vec_select: + (match_operand:V_VLSI 1 "register_operand" "vr") + (parallel [(match_operand:DI 2 "register_operand" "r")])) + (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE))] + "TARGET_XTHEADVECTOR" + "vext.x.v\t%0,%1,%2" + [(set_attr "type" "vimovvx") + (set_attr "mode" "")]) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/vlb-vsb.c b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/vlb-vsb.c new file mode 100644 index 00000000000..4e192bbf025 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/vlb-vsb.c @@ -0,0 +1,68 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcxtheadvector -mabi=ilp32d -O3" } */ +/* { dg-final { check-function-bodies "**" "" } } */ +#include "riscv_vector.h" + +/* +** f1: +** th.vsetivli\tzero,4,e32,m1,tu,ma +** th.vlb\.v\tv[0-9]+,0\([a-x0-9]+\) +** th.vlb\.v\tv[0-9]+,0\([a-x0-9]+\) +** th.vadd\.vv\tv[0-9]+,\s*v[0-9]+,\s*v[0-9]+ +** th.vadd\.vv\tv[0-9]+,\s*v[0-9]+,\s*v[0-9]+ +** th.vsb\.v\tv[0-9]+,0\([a-x0-9]+\) +** ret +*/ +void f1 (void * in, void *out) +{ + vint32m1_t v = __riscv_th_vlb_v_i32m1 (in, 4); + vint32m1_t v2 = __riscv_th_vlb_v_i32m1_tu (v, in, 4); + vint32m1_t v3 = __riscv_vadd_vv_i32m1 (v2, v2, 4); + vint32m1_t v4 = __riscv_vadd_vv_i32m1_tu (v3, v2, v2, 4); + __riscv_th_vsb_v_i32m1 (out, v4, 4); +} + +/* +** f2: +** th.vsetvli\t[a-x0-9]+,zero,e8,mf4,ta,ma +** th.vlm.v\tv[0-9]+,0\([a-x0-9]+\) +** th.vsetivli\tzero,4,e32,m1,ta,ma +** th.vlb.v\tv[0-9]+,0\([a-x0-9]+\),v0.t +** th.vadd\.vv\tv[0-9]+,\s*v[0-9]+,\s*v[0-9]+ +** th.vadd\.vv\tv[1-9][0-9]?,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t +** th.vsb.v\tv[0-9]+,0\([a-x0-9]+\) +** ret +*/ +void f2 (void * in, void *out) +{ + vbool32_t mask = *(vbool32_t*)in; + asm volatile ("":::"memory"); + vint32m1_t v = __riscv_th_vlb_v_i32m1 (in, 4); + vint32m1_t v2 = __riscv_th_vlb_v_i32m1_m (mask, in, 4); + vint32m1_t v3 = __riscv_vadd_vv_i32m1 (v2, v2, 4); + vint32m1_t v4 = __riscv_vadd_vv_i32m1_m (mask, v3, v3, 4); + __riscv_th_vsb_v_i32m1 (out, v4, 4); +} + +/* +** f3: +** th.vsetvli\t[a-x0-9]+,zero,e8,mf4,ta,ma +** th.vlm.v\tv[0-9]+,0\([a-x0-9]+\) +** th.vsetivli\tzero,4,e32,m1,tu,mu +** th.vlb\.v\tv[0-9]+,0\([a-x0-9]+\) +** th.vlb.v\tv[0-9]+,0\([a-x0-9]+\),v0.t +** th.vadd\.vv\tv[0-9]+,\s*v[0-9]+,\s*v[0-9]+ +** th.vadd\.vv\tv[1-9][0-9]?,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t +** th.vsb.v\tv[0-9]+,0\([a-x0-9]+\) +** ret +*/ +void f3 (void * in, void *out) +{ + vbool32_t mask = *(vbool32_t*)in; + asm volatile ("":::"memory"); + vint32m1_t v = __riscv_th_vlb_v_i32m1 (in, 4); + vint32m1_t v2 = __riscv_th_vlb_v_i32m1_tumu (mask, v, in, 4); + vint32m1_t v3 = __riscv_vadd_vv_i32m1 (v2, v2, 4); + vint32m1_t v4 = __riscv_vadd_vv_i32m1_tumu (mask, v3, v2, v2, 4); + __riscv_th_vsb_v_i32m1 (out, v4, 4); +} diff --git a/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/vlbu-vsb.c b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/vlbu-vsb.c new file mode 100644 index 00000000000..1538afec68e --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/vlbu-vsb.c @@ -0,0 +1,68 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcxtheadvector -mabi=ilp32d -O3" } */ +/* { dg-final { check-function-bodies "**" "" } } */ +#include "riscv_vector.h" + +/* +** f1: +** th.vsetivli\tzero,4,e32,m1,tu,ma +** th.vlbu\.v\tv[0-9]+,0\([a-x0-9]+\) +** th.vlbu\.v\tv[0-9]+,0\([a-x0-9]+\) +** th.vadd\.vi\tv[0-9]+,\s*v[0-9]+,\s*-16 +** th.vadd\.vi\tv[0-9]+,\s*v[0-9]+,\s*-16 +** th.vsb\.v\tv[0-9]+,0\([a-x0-9]+\) +** ret +*/ +void f1 (void * in, void *out, uint32_t x) +{ + vuint32m1_t v = __riscv_th_vlbu_v_u32m1 (in, 4); + vuint32m1_t v2 = __riscv_th_vlbu_v_u32m1_tu (v, in, 4); + vuint32m1_t v3 = __riscv_vadd_vx_u32m1 (v2, -16, 4); + vuint32m1_t v4 = __riscv_vadd_vx_u32m1_tu (v3, v2, -16, 4); + __riscv_th_vsb_v_u32m1 (out, v4, 4); +} + +/* +** f2: +** th.vsetvli\t[a-x0-9]+,zero,e8,mf4,ta,ma +** th.vlm.v\tv[0-9]+,0\([a-x0-9]+\) +** th.vsetivli\tzero,4,e32,m1,ta,ma +** th.vlbu.v\tv[0-9]+,0\([a-x0-9]+\),v0.t +** th.vadd\.vi\tv[0-9]+,\s*v[0-9]+,\s*-16 +** th.vadd\.vi\tv[1-9][0-9]?,\s*v[0-9]+,\s*-16,\s*v0.t +** th.vsb.v\tv[0-9]+,0\([a-x0-9]+\) +** ret +*/ +void f2 (void * in, void *out, uint32_t x) +{ + vbool32_t mask = *(vbool32_t*)in; + asm volatile ("":::"memory"); + vuint32m1_t v = __riscv_th_vlbu_v_u32m1 (in, 4); + vuint32m1_t v2 = __riscv_th_vlbu_v_u32m1_m (mask, in, 4); + vuint32m1_t v3 = __riscv_vadd_vx_u32m1 (v2, -16, 4); + vuint32m1_t v4 = __riscv_vadd_vx_u32m1_m (mask, v3, -16, 4); + __riscv_th_vsb_v_u32m1 (out, v4, 4); +} + +/* +** f3: +** th.vsetvli\t[a-x0-9]+,zero,e8,mf4,ta,ma +** th.vlm.v\tv[0-9]+,0\([a-x0-9]+\) +** th.vsetivli\tzero,4,e32,m1,tu,mu +** th.vlbu\.v\tv[0-9]+,0\([a-x0-9]+\) +** th.vlbu.v\tv[0-9]+,0\([a-x0-9]+\),v0.t +** th.vadd\.vi\tv[0-9]+,\s*v[0-9]+,\s*-16 +** th.vadd\.vi\tv[1-9][0-9]?,\s*v[0-9]+,\s*-16,\s*v0.t +** th.vsb.v\tv[0-9]+,0\([a-x0-9]+\) +** ret +*/ +void f3 (void * in, void *out, uint32_t x) +{ + vbool32_t mask = *(vbool32_t*)in; + asm volatile ("":::"memory"); + vuint32m1_t v = __riscv_th_vlbu_v_u32m1 (in, 4); + vuint32m1_t v2 = __riscv_th_vlbu_v_u32m1_tumu (mask, v, in, 4); + vuint32m1_t v3 = __riscv_vadd_vx_u32m1 (v2, -16, 4); + vuint32m1_t v4 = __riscv_vadd_vx_u32m1_tumu (mask, v3, v2, -16, 4); + __riscv_th_vsb_v_u32m1 (out, v4, 4); +} \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/vlh-vsh.c b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/vlh-vsh.c new file mode 100644 index 00000000000..bf4924a1d76 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/vlh-vsh.c @@ -0,0 +1,68 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcxtheadvector -mabi=ilp32d -O3" } */ +/* { dg-final { check-function-bodies "**" "" } } */ +#include "riscv_vector.h" + +/* +** f1: +** th.vsetivli\tzero,4,e32,m1,tu,ma +** th.vlh\.v\tv[0-9]+,0\([a-x0-9]+\) +** th.vlh\.v\tv[0-9]+,0\([a-x0-9]+\) +** th.vadd\.vi\tv[0-9]+,\s*v[0-9]+,\s*-16 +** th.vadd\.vi\tv[0-9]+,\s*v[0-9]+,\s*-16 +** th.vsh\.v\tv[0-9]+,0\([a-x0-9]+\) +** ret +*/ +void f1 (void * in, void *out, int32_t x) +{ + vint32m1_t v = __riscv_th_vlh_v_i32m1 (in, 4); + vint32m1_t v2 = __riscv_th_vlh_v_i32m1_tu (v, in, 4); + vint32m1_t v3 = __riscv_vadd_vx_i32m1 (v2, -16, 4); + vint32m1_t v4 = __riscv_vadd_vx_i32m1_tu (v3, v2, -16, 4); + __riscv_th_vsh_v_i32m1 (out, v4, 4); +} + +/* +** f2: +** th.vsetvli\t[a-x0-9]+,zero,e8,mf4,ta,ma +** th.vlm.v\tv[0-9]+,0\([a-x0-9]+\) +** th.vsetivli\tzero,4,e32,m1,ta,ma +** th.vlh.v\tv[0-9]+,0\([a-x0-9]+\),v0.t +** th.vadd\.vi\tv[0-9]+,\s*v[0-9]+,\s*-16 +** th.vadd\.vi\tv[1-9][0-9]?,\s*v[0-9]+,\s*-16,\s*v0.t +** th.vsh.v\tv[0-9]+,0\([a-x0-9]+\) +** ret +*/ +void f2 (void * in, void *out, int32_t x) +{ + vbool32_t mask = *(vbool32_t*)in; + asm volatile ("":::"memory"); + vint32m1_t v = __riscv_th_vlh_v_i32m1 (in, 4); + vint32m1_t v2 = __riscv_th_vlh_v_i32m1_m (mask, in, 4); + vint32m1_t v3 = __riscv_vadd_vx_i32m1 (v2, -16, 4); + vint32m1_t v4 = __riscv_vadd_vx_i32m1_m (mask, v3, -16, 4); + __riscv_th_vsh_v_i32m1 (out, v4, 4); +} + +/* +** f3: +** th.vsetvli\t[a-x0-9]+,zero,e8,mf4,ta,ma +** th.vlm.v\tv[0-9]+,0\([a-x0-9]+\) +** th.vsetivli\tzero,4,e32,m1,tu,mu +** th.vlh\.v\tv[0-9]+,0\([a-x0-9]+\) +** th.vlh.v\tv[0-9]+,0\([a-x0-9]+\),v0.t +** th.vadd\.vi\tv[0-9]+,\s*v[0-9]+,\s*-16 +** th.vadd\.vi\tv[1-9][0-9]?,\s*v[0-9]+,\s*-16,\s*v0.t +** th.vsh.v\tv[0-9]+,0\([a-x0-9]+\) +** ret +*/ +void f3 (void * in, void *out, int32_t x) +{ + vbool32_t mask = *(vbool32_t*)in; + asm volatile ("":::"memory"); + vint32m1_t v = __riscv_th_vlh_v_i32m1 (in, 4); + vint32m1_t v2 = __riscv_th_vlh_v_i32m1_tumu (mask, v, in, 4); + vint32m1_t v3 = __riscv_vadd_vx_i32m1 (v2, -16, 4); + vint32m1_t v4 = __riscv_vadd_vx_i32m1_tumu (mask, v3, v2, -16, 4); + __riscv_th_vsh_v_i32m1 (out, v4, 4); +} \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/vlhu-vsh.c b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/vlhu-vsh.c new file mode 100644 index 00000000000..8c451845175 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/vlhu-vsh.c @@ -0,0 +1,68 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcxtheadvector -mabi=ilp32d -O3" } */ +/* { dg-final { check-function-bodies "**" "" } } */ +#include "riscv_vector.h" + +/* +** f1: +** th.vsetivli\tzero,4,e32,m1,tu,ma +** th.vlhu\.v\tv[0-9]+,0\([a-x0-9]+\) +** th.vlhu\.v\tv[0-9]+,0\([a-x0-9]+\) +** th.vadd\.vi\tv[0-9]+,\s*v[0-9]+,\s*-16 +** th.vadd\.vi\tv[0-9]+,\s*v[0-9]+,\s*-16 +** th.vsh\.v\tv[0-9]+,0\([a-x0-9]+\) +** ret +*/ +void f1 (void * in, void *out, uint32_t x) +{ + vuint32m1_t v = __riscv_th_vlhu_v_u32m1 (in, 4); + vuint32m1_t v2 = __riscv_th_vlhu_v_u32m1_tu (v, in, 4); + vuint32m1_t v3 = __riscv_vadd_vx_u32m1 (v2, -16, 4); + vuint32m1_t v4 = __riscv_vadd_vx_u32m1_tu (v3, v2, -16, 4); + __riscv_th_vsh_v_u32m1 (out, v4, 4); +} + +/* +** f2: +** th.vsetvli\t[a-x0-9]+,zero,e8,mf4,ta,ma +** th.vlm.v\tv[0-9]+,0\([a-x0-9]+\) +** th.vsetivli\tzero,4,e32,m1,ta,ma +** th.vlhu.v\tv[0-9]+,0\([a-x0-9]+\),v0.t +** th.vadd\.vi\tv[0-9]+,\s*v[0-9]+,\s*-16 +** th.vadd\.vi\tv[1-9][0-9]?,\s*v[0-9]+,\s*-16,\s*v0.t +** th.vsh.v\tv[0-9]+,0\([a-x0-9]+\) +** ret +*/ +void f2 (void * in, void *out, uint32_t x) +{ + vbool32_t mask = *(vbool32_t*)in; + asm volatile ("":::"memory"); + vuint32m1_t v = __riscv_th_vlhu_v_u32m1 (in, 4); + vuint32m1_t v2 = __riscv_th_vlhu_v_u32m1_m (mask, in, 4); + vuint32m1_t v3 = __riscv_vadd_vx_u32m1 (v2, -16, 4); + vuint32m1_t v4 = __riscv_vadd_vx_u32m1_m (mask, v3, -16, 4); + __riscv_th_vsh_v_u32m1 (out, v4, 4); +} + +/* +** f3: +** th.vsetvli\t[a-x0-9]+,zero,e8,mf4,ta,ma +** th.vlm.v\tv[0-9]+,0\([a-x0-9]+\) +** th.vsetivli\tzero,4,e32,m1,tu,mu +** th.vlhu\.v\tv[0-9]+,0\([a-x0-9]+\) +** th.vlhu.v\tv[0-9]+,0\([a-x0-9]+\),v0.t +** th.vadd\.vi\tv[0-9]+,\s*v[0-9]+,\s*-16 +** th.vadd\.vi\tv[1-9][0-9]?,\s*v[0-9]+,\s*-16,\s*v0.t +** th.vsh.v\tv[0-9]+,0\([a-x0-9]+\) +** ret +*/ +void f3 (void * in, void *out, uint32_t x) +{ + vbool32_t mask = *(vbool32_t*)in; + asm volatile ("":::"memory"); + vuint32m1_t v = __riscv_th_vlhu_v_u32m1 (in, 4); + vuint32m1_t v2 = __riscv_th_vlhu_v_u32m1_tumu (mask, v, in, 4); + vuint32m1_t v3 = __riscv_vadd_vx_u32m1 (v2, -16, 4); + vuint32m1_t v4 = __riscv_vadd_vx_u32m1_tumu (mask, v3, v2, -16, 4); + __riscv_th_vsh_v_u32m1 (out, v4, 4); +} \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/vlw-vsw.c b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/vlw-vsw.c new file mode 100644 index 00000000000..0f5b09684a5 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/vlw-vsw.c @@ -0,0 +1,68 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcxtheadvector -mabi=ilp32d -O3" } */ +/* { dg-final { check-function-bodies "**" "" } } */ +#include "riscv_vector.h" + +/* +** f1: +** th.vsetivli\tzero,4,e32,m1,tu,ma +** th.vlw\.v\tv[0-9]+,0\([a-x0-9]+\) +** th.vlw\.v\tv[0-9]+,0\([a-x0-9]+\) +** th.vadd\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+ +** th.vadd\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+ +** th.vsw\.v\tv[0-9]+,0\([a-x0-9]+\) +** ret +*/ +void f1 (void * in, void *out, int32_t x) +{ + vint32m1_t v = __riscv_th_vlw_v_i32m1 (in, 4); + vint32m1_t v2 = __riscv_th_vlw_v_i32m1_tu (v, in, 4); + vint32m1_t v3 = __riscv_vadd_vx_i32m1 (v2, x, 4); + vint32m1_t v4 = __riscv_vadd_vx_i32m1_tu (v3, v2, x, 4); + __riscv_th_vsw_v_i32m1 (out, v4, 4); +} + +/* +** f2: +** th.vsetvli\t[a-x0-9]+,zero,e8,mf4,ta,ma +** th.vlm.v\tv[0-9]+,0\([a-x0-9]+\) +** th.vsetivli\tzero,4,e32,m1,ta,ma +** th.vlw.v\tv[0-9]+,0\([a-x0-9]+\),v0.t +** th.vadd\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+ +** th.vadd\.vx\tv[1-9][0-9]?,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t +** th.vsw.v\tv[0-9]+,0\([a-x0-9]+\) +** ret +*/ +void f2 (void * in, void *out, int32_t x) +{ + vbool32_t mask = *(vbool32_t*)in; + asm volatile ("":::"memory"); + vint32m1_t v = __riscv_th_vlw_v_i32m1 (in, 4); + vint32m1_t v2 = __riscv_th_vlw_v_i32m1_m (mask, in, 4); + vint32m1_t v3 = __riscv_vadd_vx_i32m1 (v2, x, 4); + vint32m1_t v4 = __riscv_vadd_vx_i32m1_m (mask, v3, x, 4); + __riscv_th_vsw_v_i32m1 (out, v4, 4); +} + +/* +** f3: +** th.vsetvli\t[a-x0-9]+,zero,e8,mf4,ta,ma +** th.vlm.v\tv[0-9]+,0\([a-x0-9]+\) +** th.vsetivli\tzero,4,e32,m1,tu,mu +** th.vlw\.v\tv[0-9]+,0\([a-x0-9]+\) +** th.vlw.v\tv[0-9]+,0\([a-x0-9]+\),v0.t +** th.vadd\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+ +** th.vadd\.vx\tv[1-9][0-9]?,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t +** th.vsw.v\tv[0-9]+,0\([a-x0-9]+\) +** ret +*/ +void f3 (void * in, void *out, int32_t x) +{ + vbool32_t mask = *(vbool32_t*)in; + asm volatile ("":::"memory"); + vint32m1_t v = __riscv_th_vlw_v_i32m1 (in, 4); + vint32m1_t v2 = __riscv_th_vlw_v_i32m1_tumu (mask, v, in, 4); + vint32m1_t v3 = __riscv_vadd_vx_i32m1 (v2, x, 4); + vint32m1_t v4 = __riscv_vadd_vx_i32m1_tumu (mask, v3, v2, x, 4); + __riscv_th_vsw_v_i32m1 (out, v4, 4); +} \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/vlwu-vsw.c b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/vlwu-vsw.c new file mode 100644 index 00000000000..aaa75be023d --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/vlwu-vsw.c @@ -0,0 +1,68 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcxtheadvector -mabi=ilp32d -O3" } */ +/* { dg-final { check-function-bodies "**" "" } } */ +#include "riscv_vector.h" + +/* +** f1: +** th.vsetivli\tzero,4,e32,m1,tu,ma +** th.vlwu\.v\tv[0-9]+,0\([a-x0-9]+\) +** th.vlwu\.v\tv[0-9]+,0\([a-x0-9]+\) +** th.vadd\.vi\tv[0-9]+,\s*v[0-9]+,\s*-16 +** th.vadd\.vi\tv[0-9]+,\s*v[0-9]+,\s*-16 +** th.vsw\.v\tv[0-9]+,0\([a-x0-9]+\) +** ret +*/ +void f1 (void * in, void *out, uint32_t x) +{ + vuint32m1_t v = __riscv_th_vlwu_v_u32m1 (in, 4); + vuint32m1_t v2 = __riscv_th_vlwu_v_u32m1_tu (v, in, 4); + vuint32m1_t v3 = __riscv_vadd_vx_u32m1 (v2, -16, 4); + vuint32m1_t v4 = __riscv_vadd_vx_u32m1_tu (v3, v2, -16, 4); + __riscv_th_vsw_v_u32m1 (out, v4, 4); +} + +/* +** f2: +** th.vsetvli\t[a-x0-9]+,zero,e8,mf4,ta,ma +** th.vlm.v\tv[0-9]+,0\([a-x0-9]+\) +** th.vsetivli\tzero,4,e32,m1,ta,ma +** th.vlwu.v\tv[0-9]+,0\([a-x0-9]+\),v0.t +** th.vadd\.vi\tv[0-9]+,\s*v[0-9]+,\s*-16 +** th.vadd\.vi\tv[1-9][0-9]?,\s*v[0-9]+,\s*-16,\s*v0.t +** th.vsw.v\tv[0-9]+,0\([a-x0-9]+\) +** ret +*/ +void f2 (void * in, void *out, uint32_t x) +{ + vbool32_t mask = *(vbool32_t*)in; + asm volatile ("":::"memory"); + vuint32m1_t v = __riscv_th_vlwu_v_u32m1 (in, 4); + vuint32m1_t v2 = __riscv_th_vlwu_v_u32m1_m (mask, in, 4); + vuint32m1_t v3 = __riscv_vadd_vx_u32m1 (v2, -16, 4); + vuint32m1_t v4 = __riscv_vadd_vx_u32m1_m (mask, v3, -16, 4); + __riscv_th_vsw_v_u32m1 (out, v4, 4); +} + +/* +** f3: +** th.vsetvli\t[a-x0-9]+,zero,e8,mf4,ta,ma +** th.vlm.v\tv[0-9]+,0\([a-x0-9]+\) +** th.vsetivli\tzero,4,e32,m1,tu,mu +** th.vlwu\.v\tv[0-9]+,0\([a-x0-9]+\) +** th.vlwu.v\tv[0-9]+,0\([a-x0-9]+\),v0.t +** th.vadd\.vi\tv[0-9]+,\s*v[0-9]+,\s*-16 +** th.vadd\.vi\tv[1-9][0-9]?,\s*v[0-9]+,\s*-16,\s*v0.t +** th.vsw.v\tv[0-9]+,0\([a-x0-9]+\) +** ret +*/ +void f3 (void * in, void *out, uint32_t x) +{ + vbool32_t mask = *(vbool32_t*)in; + asm volatile ("":::"memory"); + vuint32m1_t v = __riscv_th_vlwu_v_u32m1 (in, 4); + vuint32m1_t v2 = __riscv_th_vlwu_v_u32m1_tumu (mask, v, in, 4); + vuint32m1_t v3 = __riscv_vadd_vx_u32m1 (v2, -16, 4); + vuint32m1_t v4 = __riscv_vadd_vx_u32m1_tumu (mask, v3, v2, -16, 4); + __riscv_th_vsw_v_u32m1 (out, v4, 4); +} \ No newline at end of file