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[Committed] RISC-V: Fix comments of segment load/store intrinsic[NFC]

Message ID 20240109021054.1095824-1-juzhe.zhong@rivai.ai
State Accepted
Headers
Series [Committed] RISC-V: Fix comments of segment load/store intrinsic[NFC] |

Checks

Context Check Description
snail/gcc-patch-check success Github commit url

Commit Message

juzhe.zhong@rivai.ai Jan. 9, 2024, 2:10 a.m. UTC 
  We have supported segment load/store intrinsics.

Committed as it is obvious.

gcc/ChangeLog:

	* config/riscv/riscv-vector-builtins-functions.def (vleff): Move comments to real place.
	(vcreate): Ditto.

---
 gcc/config/riscv/riscv-vector-builtins-functions.def | 4 +---
 1 file changed, 1 insertion(+), 3 deletions(-)
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Patch

diff --git a/gcc/config/riscv/riscv-vector-builtins-functions.def b/gcc/config/riscv/riscv-vector-builtins-functions.def
index 96dd0d95dec..14560923d11 100644
--- a/gcc/config/riscv/riscv-vector-builtins-functions.def
+++ b/gcc/config/riscv/riscv-vector-builtins-functions.def
@@ -79,8 +79,6 @@  DEF_RVV_FUNCTION (vsoxei64, indexed_loadstore, none_m_preds, all_v_scalar_ptr_ee
 // 7.7. Unit-stride Fault-Only-First Loads
 DEF_RVV_FUNCTION (vleff, fault_load, full_preds, all_v_scalar_const_ptr_size_ptr_ops)
 
-// TODO: 7.8. Vector Load/Store Segment Instructions
-
 /* 11. Vector Integer Arithmetic Instructions.  */
 
 // 11.1. Vector Single-Width Integer Add and Subtract
@@ -625,7 +623,7 @@  DEF_RVV_FUNCTION (vcreate, vcreate, none_preds, all_v_vcreate_lmul2_x2_ops)
 DEF_RVV_FUNCTION (vcreate, vcreate, none_preds, all_v_vcreate_lmul2_x4_ops)
 DEF_RVV_FUNCTION (vcreate, vcreate, none_preds, all_v_vcreate_lmul4_x2_ops)
 
-// Tuple types
+// 7.8. Vector Load/Store Segment Instructions
 DEF_RVV_FUNCTION (vset, vset, none_preds, all_v_vset_tuple_ops)
 DEF_RVV_FUNCTION (vget, vget, none_preds, all_v_vget_tuple_ops)
 DEF_RVV_FUNCTION (vcreate, vcreate, none_preds, all_v_vcreate_tuple_ops)