From patchwork Mon Jan 8 01:14:08 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yang Yujie X-Patchwork-Id: 185783 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7300:37c1:b0:101:2151:f287 with SMTP id y1csp779713dyq; Sun, 7 Jan 2024 17:24:34 -0800 (PST) X-Google-Smtp-Source: AGHT+IHnLvjGoXguOjkWqnLIAm5FyEce9qOg6ncNNe4RC9qM52IjPH5x3IoeZn5pTWuENG3wV/nF X-Received: by 2002:a05:6e02:1a6b:b0:35f:f139:e114 with SMTP id w11-20020a056e021a6b00b0035ff139e114mr3467259ilv.28.1704677073995; Sun, 07 Jan 2024 17:24:33 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1704677073; cv=pass; d=google.com; s=arc-20160816; b=oExglbfoBGUs6AGVPd1wkmJ/aGaESrNZroGE1r74LXQNFOCxeNGxw8C8gn+pZvQmrf KZOC8+Wh5Hcbst9Aq4h1xMZc7ok3/GIUlw9eTS6lKNcoPnD5JPQOPFLJ9hOlJilIgaVL Bh4MnLnGaKAK4xdgDPHMKvuHScoUt74hKaCNGMjIZa3LlcAf9P5fUr6vIwUR+TcOY8dZ 1GQIkDon2CePR2g8ooxuMZUZ5apBPqxA3Oq/7W5KxN8ijqf41gxwyzU5kOCOeQ9+CmsZ SWqozTcMhv9WSfzNldhCjECSohOOKGeWsC/siDUPU2txKu3zuiBlE31OfqCv3bmzakux QlSw== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:arc-filter:dmarc-filter:delivered-to; bh=h6pgO/iTxf1i0G4W6HpPKghdQdGzn43CXfE7rbk5ZVU=; fh=sZLDO+6GrGvmqAJw8D519hskXPb+X/EHcBBRRjfMSEs=; b=xLu94Or2vExKoKM8r9005xHPyTHOYaWYCiHL0YDQmUkKH9NMiSVq28I/GJVbIAofrg SBUmXG1aGydl9BsSenpy00F/fDwz3jICNKya7U5l+W8KNIQaiAzoKkh5Jfb6rspuz0N3 SN4uIEYqchMvo5/HWH7oB57vZuOcvTYTTBtdFW0tSrBL+wNWkMIAMrBEbt6e1XCr5JqF DvhTo0SxF0HlGP1mB/rasmb9YnJpI7YK7am54utuc3aDLKh/oUizqDXrc01bWWdQmfPD X527pYt0MEwVjPin13maXKh1Rf5kd9z2OP9KuZnKWM+tL6Ff5Ajeb7axOPpHhqYSLYbO w/0A== ARC-Authentication-Results: i=2; mx.google.com; arc=pass (i=1); spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org" Received: from server2.sourceware.org (server2.sourceware.org. [8.43.85.97]) by mx.google.com with ESMTPS id m10-20020a05622a118a00b004299a292bfdsi70189qtk.10.2024.01.07.17.24.33 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 07 Jan 2024 17:24:33 -0800 (PST) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) client-ip=8.43.85.97; Authentication-Results: mx.google.com; arc=pass (i=1); spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org" Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 49934386F804 for ; Mon, 8 Jan 2024 01:24:23 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mail.loongson.cn (mail.loongson.cn [114.242.206.163]) by sourceware.org (Postfix) with ESMTP id DBCD538618A3 for ; Mon, 8 Jan 2024 01:20:04 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org DBCD538618A3 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=loongson.cn Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=loongson.cn ARC-Filter: OpenARC Filter v1.0.0 sourceware.org DBCD538618A3 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=114.242.206.163 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1704676815; cv=none; b=gjS27J9SfIHbQEVo4LSb2lWWTDDbY+M0lZqDhiyFPUjp2h4vKmLBDevcDK4UCDFvI82Jp7Y1tMjyYIz8JH2k0XK6YzG1msqK7/Rlx4cHJtLi6SAPKynUz4m8eaTivKUBeCHWNskpCFsS9KCqQoSBifOBSnuVDZE2mE8s4LiMvCA= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1704676815; c=relaxed/simple; bh=/Tz/oiXu6LFTITazDyJP5/9lOUpAnt4KFL4A4Yg3k/s=; h=From:To:Subject:Date:Message-ID:MIME-Version; b=OeDUJlZyuiujBSoM/ijnOmpDww4EcQ61949IkzOyFyrIbg8/luShSN+k23Fh/7UCTRIyMxMTc/lLxUi7X2Cxs4Fw3H8jtQrKmqV6roF27EuF5Wwrsvzzrm161jj3KEB13L8hrZJLEsRMLfirPIiAwAlDg92Dg/DUKA06NbO9A70= ARC-Authentication-Results: i=1; server2.sourceware.org Received: from loongson.cn (unknown [114.243.106.119]) by gateway (Coremail) with SMTP id _____8BxHLvCTZtlx_4CAA--.1546S3; Mon, 08 Jan 2024 09:20:02 +0800 (CST) Received: from localhost.localdomain (unknown [114.243.106.119]) by localhost.localdomain (Coremail) with SMTP id AQAAf8CxTN65TZtlLMEGAA--.838S4; Mon, 08 Jan 2024 09:20:01 +0800 (CST) From: Yang Yujie To: gcc-patches@gcc.gnu.org Cc: xry111@xry111.site, chenglulu@loongson.cn, xuchenghua@loongson.cn, Yang Yujie Subject: [PATCH v2 2/4] LoongArch: Rename ISA_BASE_LA64V100 to ISA_BASE_LA64 Date: Mon, 8 Jan 2024 09:14:08 +0800 Message-ID: <20240108011410.305003-3-yangyujie@loongson.cn> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240108011410.305003-1-yangyujie@loongson.cn> References: <20240108011410.305003-1-yangyujie@loongson.cn> MIME-Version: 1.0 X-CM-TRANSID: AQAAf8CxTN65TZtlLMEGAA--.838S4 X-CM-SenderInfo: 51dqw5pxmlvqxorr0wxvrqhubq/1tbiAQAKAGWbSakAuQABst X-Coremail-Antispam: 1Uk129KBj93XoW3AFW8GFy7ArW5Wr15Kr4rJFc_yoW3urykpF 9ruwsxJr48CrsxWr1Dt3s5Ww4DJ3s7Kr12q3Wftr18Cr47Xr18ZF48GFZxXF1jqa15try2 qrWFka1ava1UK3cCm3ZEXasCq-sJn29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7KY7ZEXa sCq-sGcSsGvfJ3Ic02F40EFcxC0VAKzVAqx4xG6I80ebIjqfuFe4nvWSU5nxnvy29KBjDU 0xBIdaVrnRJUUUkjb4IE77IF4wAFF20E14v26r1j6r4UM7CY07I20VC2zVCF04k26cxKx2 IYs7xG6rWj6s0DM7CIcVAFz4kK6r126r13M28lY4IEw2IIxxk0rwA2F7IY1VAKz4vEj48v e4kI8wA2z4x0Y4vE2Ix0cI8IcVAFwI0_Gr0_Xr1l84ACjcxK6xIIjxv20xvEc7CjxVAFwI 0_Gr0_Cr1l84ACjcxK6I8E87Iv67AKxVW8JVWxJwA2z4x0Y4vEx4A2jsIEc7CjxVAFwI0_ Gr0_Gr1UM2AIxVAIcxkEcVAq07x20xvEncxIr21l57IF6xkI12xvs2x26I8E6xACxx1l5I 8CrVACY4xI64kE6c02F40Ex7xfMcIj6xIIjxv20xvE14v26r126r1DMcIj6I8E87Iv67AK xVWUJVW8JwAm72CE4IkC6x0Yz7v_Jr0_Gr1lF7xvr2IYc2Ij64vIr41l42xK82IYc2Ij64 vIr41l4I8I3I0E4IkC6x0Yz7v_Jr0_Gr1lx2IqxVAqx4xG67AKxVWUJVWUGwC20s026x8G jcxK67AKxVWUGVWUWwC2zVAF1VAY17CE14v26r126r1DMIIYrxkI7VAKI48JMIIF0xvE2I x0cI8IcVAFwI0_Jr0_JF4lIxAIcVC0I7IYx2IY6xkF7I0E14v26r1j6r4UMIIF0xvE42xK 8VAvwI8IcIk0rVWUJVWUCwCI42IY6I8E87Iv67AKxVWUJVW8JwCI42IY6I8E87Iv6xkF7I 0E14v26r1j6r4UYxBIdaVFxhVjvjDU0xZFpf9x07jjpB-UUUUU= X-Spam-Status: No, score=-10.1 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, KAM_NUMSUBJECT, RCVD_IN_BARRACUDACENTRAL, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1787483467795179041 X-GMAIL-MSGID: 1787483467795179041 LoongArch ISA manual v1.10 suggests that software should not depend on the ISA version number for marking processor features. The ISA version number is now defined as a collective name of individual ISA evolutions. Since there is a independent ISA evolution mask now, we can drop the version information from the base ISA. gcc/ChangeLog: * config/loongarch/genopts/loongarch-strings: Rename. * config/loongarch/genopts/loongarch.opt.in: Same. * config/loongarch/loongarch-cpu.cc: Same. * config/loongarch/loongarch-def.cc: Same. * config/loongarch/loongarch-def.h: Same. * config/loongarch/loongarch-opts.cc: Same. * config/loongarch/loongarch-opts.h: Same. * config/loongarch/loongarch-str.h: Same. * config/loongarch/loongarch.opt: Same. --- gcc/config/loongarch/genopts/loongarch-strings | 2 +- gcc/config/loongarch/genopts/loongarch.opt.in | 2 +- gcc/config/loongarch/loongarch-cpu.cc | 2 +- gcc/config/loongarch/loongarch-def.cc | 14 +++++++------- gcc/config/loongarch/loongarch-def.h | 6 +++--- gcc/config/loongarch/loongarch-opts.cc | 10 +++++----- gcc/config/loongarch/loongarch-opts.h | 2 +- gcc/config/loongarch/loongarch-str.h | 2 +- gcc/config/loongarch/loongarch.opt | 2 +- 9 files changed, 21 insertions(+), 21 deletions(-) diff --git a/gcc/config/loongarch/genopts/loongarch-strings b/gcc/config/loongarch/genopts/loongarch-strings index f40b014f017..ba47be31227 100644 --- a/gcc/config/loongarch/genopts/loongarch-strings +++ b/gcc/config/loongarch/genopts/loongarch-strings @@ -29,7 +29,7 @@ STR_CPU_LA464 la464 STR_CPU_LA664 la664 # Base architecture -STR_ISA_BASE_LA64V100 la64 +STR_ISA_BASE_LA64 la64 # -mfpu OPTSTR_ISA_EXT_FPU fpu diff --git a/gcc/config/loongarch/genopts/loongarch.opt.in b/gcc/config/loongarch/genopts/loongarch.opt.in index e643deacd21..38ac347c660 100644 --- a/gcc/config/loongarch/genopts/loongarch.opt.in +++ b/gcc/config/loongarch/genopts/loongarch.opt.in @@ -33,7 +33,7 @@ Name(isa_base) Type(int) Basic ISAs of LoongArch: EnumValue -Enum(isa_base) String(@@STR_ISA_BASE_LA64V100@@) Value(ISA_BASE_LA64V100) +Enum(isa_base) String(@@STR_ISA_BASE_LA64@@) Value(ISA_BASE_LA64) ;; ISA extensions / adjustments Enum diff --git a/gcc/config/loongarch/loongarch-cpu.cc b/gcc/config/loongarch/loongarch-cpu.cc index e1771fc0b4f..97ac5fed9d8 100644 --- a/gcc/config/loongarch/loongarch-cpu.cc +++ b/gcc/config/loongarch/loongarch-cpu.cc @@ -133,7 +133,7 @@ fill_native_cpu_config (struct loongarch_target *tgt) switch (cpucfg_cache[1] & 0x3) { case 0x02: - tmp = ISA_BASE_LA64V100; + tmp = ISA_BASE_LA64; break; default: diff --git a/gcc/config/loongarch/loongarch-def.cc b/gcc/config/loongarch/loongarch-def.cc index 48d28315064..e8c129ce643 100644 --- a/gcc/config/loongarch/loongarch-def.cc +++ b/gcc/config/loongarch/loongarch-def.cc @@ -48,16 +48,16 @@ array_arch loongarch_cpu_default_isa = array_arch () .set (CPU_LOONGARCH64, loongarch_isa () - .base_ (ISA_BASE_LA64V100) + .base_ (ISA_BASE_LA64) .fpu_ (ISA_EXT_FPU64)) .set (CPU_LA464, loongarch_isa () - .base_ (ISA_BASE_LA64V100) + .base_ (ISA_BASE_LA64) .fpu_ (ISA_EXT_FPU64) .simd_ (ISA_EXT_SIMD_LASX)) .set (CPU_LA664, loongarch_isa () - .base_ (ISA_BASE_LA64V100) + .base_ (ISA_BASE_LA64) .fpu_ (ISA_EXT_FPU64) .simd_ (ISA_EXT_SIMD_LASX) .evolution_ (OPTION_MASK_ISA_DIV32 | OPTION_MASK_ISA_LD_SEQ_SA @@ -153,7 +153,7 @@ array_tune loongarch_cpu_multipass_dfa_lookahead = array_tune () array loongarch_isa_base_strings = array () - .set (ISA_BASE_LA64V100, STR_ISA_BASE_LA64V100); + .set (ISA_BASE_LA64, STR_ISA_BASE_LA64); array loongarch_isa_ext_strings = array () @@ -189,15 +189,15 @@ array, N_ABI_BASE_TYPES> array () .set (ABI_EXT_BASE, loongarch_isa () - .base_ (ISA_BASE_LA64V100) + .base_ (ISA_BASE_LA64) .fpu_ (ISA_EXT_FPU64))) .set (ABI_BASE_LP64F, array () .set (ABI_EXT_BASE, loongarch_isa () - .base_ (ISA_BASE_LA64V100) + .base_ (ISA_BASE_LA64) .fpu_ (ISA_EXT_FPU32))) .set (ABI_BASE_LP64S, array () .set (ABI_EXT_BASE, - loongarch_isa ().base_ (ISA_BASE_LA64V100))); + loongarch_isa ().base_ (ISA_BASE_LA64))); diff --git a/gcc/config/loongarch/loongarch-def.h b/gcc/config/loongarch/loongarch-def.h index 1fab4f4d315..f8cb3adf509 100644 --- a/gcc/config/loongarch/loongarch-def.h +++ b/gcc/config/loongarch/loongarch-def.h @@ -55,9 +55,9 @@ along with GCC; see the file COPYING3. If not see /* enum isa_base */ -/* LoongArch V1.00. */ -#define ISA_BASE_LA64V100 0 -#define N_ISA_BASE_TYPES 1 +/* LoongArch64 */ +#define ISA_BASE_LA64 0 +#define N_ISA_BASE_TYPES 1 extern loongarch_def_array loongarch_isa_base_strings; diff --git a/gcc/config/loongarch/loongarch-opts.cc b/gcc/config/loongarch/loongarch-opts.cc index 9483060ab62..7eb1f2d4f2e 100644 --- a/gcc/config/loongarch/loongarch-opts.cc +++ b/gcc/config/loongarch/loongarch-opts.cc @@ -567,17 +567,17 @@ isa_default_abi (const struct loongarch_isa *isa) switch (isa->fpu) { case ISA_EXT_FPU64: - if (isa->base >= ISA_BASE_LA64V100) + if (isa->base >= ISA_BASE_LA64) abi.base = ABI_BASE_LP64D; break; case ISA_EXT_FPU32: - if (isa->base >= ISA_BASE_LA64V100) + if (isa->base >= ISA_BASE_LA64) abi.base = ABI_BASE_LP64F; break; case ISA_EXT_NONE: - if (isa->base >= ISA_BASE_LA64V100) + if (isa->base >= ISA_BASE_LA64) abi.base = ABI_BASE_LP64S; break; @@ -596,8 +596,8 @@ isa_base_compat_p (const struct loongarch_isa *set1, { switch (set2->base) { - case ISA_BASE_LA64V100: - return (set1->base >= ISA_BASE_LA64V100); + case ISA_BASE_LA64: + return (set1->base >= ISA_BASE_LA64); default: gcc_unreachable (); diff --git a/gcc/config/loongarch/loongarch-opts.h b/gcc/config/loongarch/loongarch-opts.h index aa0dd32f411..586e67e65ee 100644 --- a/gcc/config/loongarch/loongarch-opts.h +++ b/gcc/config/loongarch/loongarch-opts.h @@ -79,7 +79,7 @@ struct loongarch_flags { #define TARGET_DOUBLE_FLOAT (la_target.isa.fpu == ISA_EXT_FPU64) #define TARGET_DOUBLE_FLOAT_ABI (la_target.abi.base == ABI_BASE_LP64D) -#define TARGET_64BIT (la_target.isa.base == ISA_BASE_LA64V100) +#define TARGET_64BIT (la_target.isa.base == ISA_BASE_LA64) #define TARGET_ABI_LP64 (la_target.abi.base == ABI_BASE_LP64D \ || la_target.abi.base == ABI_BASE_LP64F \ || la_target.abi.base == ABI_BASE_LP64S) diff --git a/gcc/config/loongarch/loongarch-str.h b/gcc/config/loongarch/loongarch-str.h index 2221c57f78e..0a6a36c5783 100644 --- a/gcc/config/loongarch/loongarch-str.h +++ b/gcc/config/loongarch/loongarch-str.h @@ -32,7 +32,7 @@ along with GCC; see the file COPYING3. If not see #define STR_CPU_LA464 "la464" #define STR_CPU_LA664 "la664" -#define STR_ISA_BASE_LA64V100 "la64" +#define STR_ISA_BASE_LA64 "la64" #define OPTSTR_ISA_EXT_FPU "fpu" #define STR_NONE "none" diff --git a/gcc/config/loongarch/loongarch.opt b/gcc/config/loongarch/loongarch.opt index 8b36f1a1495..76b42d51d09 100644 --- a/gcc/config/loongarch/loongarch.opt +++ b/gcc/config/loongarch/loongarch.opt @@ -41,7 +41,7 @@ Name(isa_base) Type(int) Basic ISAs of LoongArch: EnumValue -Enum(isa_base) String(la64) Value(ISA_BASE_LA64V100) +Enum(isa_base) String(la64) Value(ISA_BASE_LA64) ;; ISA extensions / adjustments Enum