diff mbox series

[3/3] LoongArch: Redundant sign extension elimination optimization 2.

Message ID 20240106085409.25985-3-chenglulu@loongson.cn
State Unresolved
Headers
Series [1/3] LoongArch: Optimized some of the symbolic expansion instructions generated during bitwise operations. |

Checks

Context Check Description
snail/gcc-patch-check warning Git am fail log

Commit Message

chenglulu Jan. 6, 2024, 8:54 a.m. UTC 
  From: liwei <liwei@loongson.cn>

Eliminate the redundant sign extension that exists after the conditional
move when the target register is SImode.

gcc/ChangeLog:

	* config/loongarch/loongarch.cc (loongarch_expand_conditional_move):
	Adjust.

gcc/testsuite/ChangeLog:

	* gcc.target/loongarch/sign-extend-2.c: Adjust.
---
 gcc/config/loongarch/loongarch.cc                  | 2 ++
 gcc/testsuite/gcc.target/loongarch/sign-extend-2.c | 2 +-
 2 files changed, 3 insertions(+), 1 deletion(-)

Comments

Xi Ruoyao Jan. 6, 2024, 11:04 a.m. UTC | #1 
On Sat, 2024-01-06 at 16:54 +0800, Lulu Cheng wrote:

/* snip */

> diff --git a/gcc/testsuite/gcc.target/loongarch/sign-extend-2.c b/gcc/testsuite/gcc.target/loongarch/sign-extend-2.c
> index a45dde4f73f..428535cb8e3 100644
> --- a/gcc/testsuite/gcc.target/loongarch/sign-extend-2.c
> +++ b/gcc/testsuite/gcc.target/loongarch/sign-extend-2.c
> @@ -1,6 +1,6 @@
>  /* { dg-do compile } */
>  /* { dg-options "-mabi=lp64d -O2" } */
> -/* { dg-final { scan-assembler-times "slli.w\t\\\$r\[0-9\]+,\\\$r\[0-9\]+,0" 1 } } */
> +/* { dg-final { scan-assembler-times "slli.w\t\\\$r\[0-9\]+,\\\$r\[0-9\]+,0" 0 } } */

Use scan-assembler-not instead of scan-assembler-times ... 0.

Otherwise LGTM.

>  #include <stdint.h>
>  #define my_min(x, y) ((x) < (y) ? (x) : (y))
diff mbox series

Patch

diff --git a/gcc/config/loongarch/loongarch.cc b/gcc/config/loongarch/loongarch.cc
index ec376a7228a..4b757b30b64 100644
--- a/gcc/config/loongarch/loongarch.cc
+++ b/gcc/config/loongarch/loongarch.cc
@@ -5371,6 +5371,8 @@  loongarch_expand_conditional_move (rtx *operands)
 	  rtx temp3 = gen_reg_rtx (mode);
 	  emit_insn (gen_rtx_SET (temp3, gen_rtx_IOR (mode, temp, temp2)));
 	  temp3 = gen_lowpart (GET_MODE (operands[0]), temp3);
+	  SUBREG_PROMOTED_VAR_P (temp3) = 1;
+	  SUBREG_PROMOTED_SET (temp3, SRP_SIGNED);
 	  loongarch_emit_move (operands[0], temp3);
 	}
       else
diff --git a/gcc/testsuite/gcc.target/loongarch/sign-extend-2.c b/gcc/testsuite/gcc.target/loongarch/sign-extend-2.c
index a45dde4f73f..428535cb8e3 100644
--- a/gcc/testsuite/gcc.target/loongarch/sign-extend-2.c
+++ b/gcc/testsuite/gcc.target/loongarch/sign-extend-2.c
@@ -1,6 +1,6 @@ 
 /* { dg-do compile } */
 /* { dg-options "-mabi=lp64d -O2" } */
-/* { dg-final { scan-assembler-times "slli.w\t\\\$r\[0-9\]+,\\\$r\[0-9\]+,0" 1 } } */
+/* { dg-final { scan-assembler-times "slli.w\t\\\$r\[0-9\]+,\\\$r\[0-9\]+,0" 0 } } */
 
 #include <stdint.h>
 #define my_min(x, y) ((x) < (y) ? (x) : (y))