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[2620:52:3:1:0:246e:9693:128c]) by mx.google.com with ESMTPS id h3-20020a05622a170300b004297ea60b58si1552781qtk.270.2024.01.06.00.55.31 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 06 Jan 2024 00:55:31 -0800 (PST) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) client-ip=2620:52:3:1:0:246e:9693:128c; Authentication-Results: mx.google.com; arc=pass (i=1); spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org" Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 5C15F3858403 for ; Sat, 6 Jan 2024 08:55:31 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from eggs.gnu.org (eggs.gnu.org [IPv6:2001:470:142:3::10]) by sourceware.org (Postfix) with ESMTPS id 3823B3858D20 for ; Sat, 6 Jan 2024 08:54:29 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 3823B3858D20 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=loongson.cn Authentication-Results: sourceware.org; spf=fail smtp.mailfrom=loongson.cn ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 3823B3858D20 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=2001:470:142:3::10 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1704531271; cv=none; b=Bibo47SJuX6a5g8/w3KCS+8xC4I0XsnGHiiEHt66BOdvz1UoQZ9zTr3xlW0yzSQNNNfv7eL1zOl8WpuDHUY0hZwUnq5uEoXcqz+bKGXMwhds8H6kNUbowlsCk5fzzVQmDBKjEARcOokkXw6wCn9a8nfY74fDZYnBvh0R2bWXKZ8= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1704531271; c=relaxed/simple; bh=gWG32fh9ttsNyVOAFJ6Y2MX2kDyebNULfVTBoYPmAUE=; h=From:To:Subject:Date:Message-Id:MIME-Version; b=Te6wN/QfXUPMYWqiWKBXbSNPx26Svi/Fv9uoP96Uc1zd5MEWYasHH+q9BKQoxK3lz3njehzYy+BhGxEh5V3XJQN5yXUMgc8pOhXGojZCpsb1kfX0BWzWSifmsR7Sw0VBvUls7phQfkaX2IGF6zH9inM0s6OgfIn3BmSTMcymbRY= ARC-Authentication-Results: i=1; server2.sourceware.org Received: from mail.loongson.cn ([114.242.206.163]) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rM2Rk-0004CK-LZ for gcc-patches@gcc.gnu.org; Sat, 06 Jan 2024 03:54:28 -0500 Received: from loongson.cn (unknown [10.20.4.107]) by gateway (Coremail) with SMTP id _____8BxXbs5FZlloZgCAA--.851S3; Sat, 06 Jan 2024 16:54:17 +0800 (CST) Received: from loongson-pc.loongson.cn (unknown [10.20.4.107]) by localhost.localdomain (Coremail) with SMTP id AQAAf8BxK9w2FZllcWgEAA--.11725S2; Sat, 06 Jan 2024 16:54:15 +0800 (CST) From: Lulu Cheng To: gcc-patches@gcc.gnu.org Cc: xry111@xry111.site, i@xen0n.name, xuchenghua@loongson.cn, chenglulu@loongson.cn Subject: [PATCH 1/3] LoongArch: Optimized some of the symbolic expansion instructions generated during bitwise operations. Date: Sat, 6 Jan 2024 16:54:07 +0800 Message-Id: <20240106085409.25985-1-chenglulu@loongson.cn> X-Mailer: git-send-email 2.20.1 MIME-Version: 1.0 X-CM-TRANSID: AQAAf8BxK9w2FZllcWgEAA--.11725S2 X-CM-SenderInfo: xfkh0wpoxo3qxorr0wxvrqhubq/ X-Coremail-Antispam: 1Uk129KBj93XoWxuFyDtryDuw1DAr15GryxtFc_yoW3CFyUpr WkC3W8GrWUXrZ2g34vkFW2qa15Kr17AFWjvF9Ygr9IkryUW34UJ340kryaqayUCw4Fqr1U Xa1xtw1Uu3y5K3gCm3ZEXasCq-sJn29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7KY7ZEXa sCq-sGcSsGvfJ3Ic02F40EFcxC0VAKzVAqx4xG6I80ebIjqfuFe4nvWSU5nxnvy29KBjDU 0xBIdaVrnRJUUUk0b4IE77IF4wAFF20E14v26r1j6r4UM7CY07I20VC2zVCF04k26cxKx2 IYs7xG6rWj6s0DM7CIcVAFz4kK6r106r15M28lY4IEw2IIxxk0rwA2F7IY1VAKz4vEj48v e4kI8wA2z4x0Y4vE2Ix0cI8IcVAFwI0_JFI_Gr1l84ACjcxK6xIIjxv20xvEc7CjxVAFwI 0_Jr0_Gr1l84ACjcxK6I8E87Iv67AKxVWxJVW8Jr1l84ACjcxK6I8E87Iv6xkF7I0E14v2 6r4j6r4UJwAS0I0E0xvYzxvE52x082IY62kv0487Mc804VCY07AIYIkI8VC2zVCFFI0UMc 02F40EFcxC0VAKzVAqx4xG6I80ewAv7VC0I7IYx2IY67AKxVWUXVWUAwAv7VC2z280aVAF wI0_Jr0_Gr1lOx8S6xCaFVCjc4AY6r1j6r4UM4x0Y48IcxkI7VAKI48JMxAIw28IcxkI7V AKI48JMxC20s026xCaFVCjc4AY6r1j6r4UMI8I3I0E5I8CrVAFwI0_Jr0_Jr4lx2IqxVCj r7xvwVAFwI0_JrI_JrWlx4CE17CEb7AF67AKxVWUAVWUtwCIc40Y0x0EwIxGrwCI42IY6x IIjxv20xvE14v26r1j6r1xMIIF0xvE2Ix0cI8IcVCY1x0267AKxVWUJVW8JwCI42IY6xAI w20EY4v20xvaj40_Jr0_JF4lIxAIcVC2z280aVAFwI0_Jr0_Gr1lIxAIcVC2z280aVCY1x 0267AKxVWUJVW8JbIYCTnIWIevJa73UjIFyTuYvjxU7XTmDUUUU Received-SPF: pass client-ip=114.242.206.163; envelope-from=chenglulu@loongson.cn; helo=mail.loongson.cn X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-Spam-Status: No, score=-13.1 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, KAM_SHORT, SPF_FAIL, SPF_HELO_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1787330646032185859 X-GMAIL-MSGID: 1787330646032185859 There are two mode iterators defined in the loongarch.md: (define_mode_iterator GPR [SI (DI "TARGET_64BIT")]) and (define_mode_iterator X [(SI "!TARGET_64BIT") (DI "TARGET_64BIT")]) Replace the mode in the bit arithmetic from GPR to X. Since the bitwise operation instruction does not distinguish between 64-bit, 32-bit, etc., it is necessary to perform symbolic expansion if the bitwise operation is less than 64 bits. The original definition would have generated a lot of redundant symbolic extension instructions. This problem is optimized with reference to the implementation of RISCV. Add this patch spec2017 500.perlbench performance improvement by 1.8% gcc/ChangeLog: * config/loongarch/loongarch.md (one_cmpl2): Replace GPR with X. (*nor3): Likewise. (nor3): Likewise. (*negsi2_extended): New template. (*si3_internal): Likewise. (*one_cmplsi2_internal): Likewise. (*norsi3_internal): Likewise. (*nsi_internal): Likewise. (bytepick_w__extend): Modify this template according to the modified bit operation to make the optimization work. gcc/testsuite/ChangeLog: * gcc.target/loongarch/sign-extend-bitwise.c: New test. --- gcc/config/loongarch/loongarch.md | 93 ++++++++++++++----- .../loongarch/sign-extend-bitwise.c | 21 +++++ 2 files changed, 90 insertions(+), 24 deletions(-) create mode 100644 gcc/testsuite/gcc.target/loongarch/sign-extend-bitwise.c diff --git a/gcc/config/loongarch/loongarch.md b/gcc/config/loongarch/loongarch.md index d1f5b94f5d6..436b9a93235 100644 --- a/gcc/config/loongarch/loongarch.md +++ b/gcc/config/loongarch/loongarch.md @@ -736,7 +736,7 @@ (define_insn "sub3" (define_insn "sub3" [(set (match_operand:GPR 0 "register_operand" "=r") - (minus:GPR (match_operand:GPR 1 "register_operand" "rJ") + (minus:GPR (match_operand:GPR 1 "register_operand" "r") (match_operand:GPR 2 "register_operand" "r")))] "" "sub.\t%0,%z1,%2" @@ -1412,13 +1412,13 @@ (define_insn "neg2" [(set_attr "alu_type" "sub") (set_attr "mode" "")]) -(define_insn "one_cmpl2" - [(set (match_operand:GPR 0 "register_operand" "=r") - (not:GPR (match_operand:GPR 1 "register_operand" "r")))] - "" - "nor\t%0,%.,%1" - [(set_attr "alu_type" "not") - (set_attr "mode" "")]) +(define_insn "*negsi2_extended" + [(set (match_operand:DI 0 "register_operand" "=r") + (sign_extend:DI (neg:SI (match_operand:SI 1 "register_operand" "r"))))] + "TARGET_64BIT" + "sub.w\t%0,%.,%1" + [(set_attr "alu_type" "sub") + (set_attr "mode" "SI")]) (define_insn "neg2" [(set (match_operand:ANYF 0 "register_operand" "=f") @@ -1438,14 +1438,39 @@ (define_insn "neg2" ;; (define_insn "3" - [(set (match_operand:GPR 0 "register_operand" "=r,r") - (any_bitwise:GPR (match_operand:GPR 1 "register_operand" "%r,r") - (match_operand:GPR 2 "uns_arith_operand" "r,K")))] + [(set (match_operand:X 0 "register_operand" "=r,r") + (any_bitwise:X (match_operand:X 1 "register_operand" "%r,r") + (match_operand:X 2 "uns_arith_operand" "r,K")))] "" "%i2\t%0,%1,%2" [(set_attr "type" "logical") (set_attr "mode" "")]) +(define_insn "*si3_internal" + [(set (match_operand:SI 0 "register_operand" "=r,r") + (any_bitwise:SI (match_operand:SI 1 "register_operand" "%r,r") + (match_operand:SI 2 "uns_arith_operand" " r,K")))] + "TARGET_64BIT" + "%i2\t%0,%1,%2" + [(set_attr "type" "logical") + (set_attr "mode" "SI")]) + +(define_insn "one_cmpl2" + [(set (match_operand:X 0 "register_operand" "=r") + (not:X (match_operand:X 1 "register_operand" "r")))] + "" + "nor\t%0,%.,%1" + [(set_attr "alu_type" "not") + (set_attr "mode" "")]) + +(define_insn "*one_cmplsi2_internal" + [(set (match_operand:SI 0 "register_operand" "=r") + (not:SI (match_operand:SI 1 "register_operand" " r")))] + "TARGET_64BIT" + "nor\t%0,%.,%1" + [(set_attr "type" "logical") + (set_attr "mode" "SI")]) + (define_insn "and3_extended" [(set (match_operand:GPR 0 "register_operand" "=r") (and:GPR (match_operand:GPR 1 "nonimmediate_operand" "r") @@ -1561,25 +1586,43 @@ (define_insn "*iorhi3" [(set_attr "type" "logical") (set_attr "mode" "HI")]) -(define_insn "*nor3" - [(set (match_operand:GPR 0 "register_operand" "=r") - (and:GPR (not:GPR (match_operand:GPR 1 "register_operand" "%r")) - (not:GPR (match_operand:GPR 2 "register_operand" "r"))))] +(define_insn "nor3" + [(set (match_operand:X 0 "register_operand" "=r") + (and:X (not:X (match_operand:X 1 "register_operand" "%r")) + (not:X (match_operand:X 2 "register_operand" "r"))))] "" "nor\t%0,%1,%2" [(set_attr "type" "logical") (set_attr "mode" "")]) +(define_insn "*norsi3_internal" + [(set (match_operand:SI 0 "register_operand" "=r") + (and:SI (not:SI (match_operand:SI 1 "register_operand" "%r")) + (not:SI (match_operand:SI 2 "register_operand" "r"))))] + "TARGET_64BIT" + "nor\t%0,%1,%2" + [(set_attr "type" "logical") + (set_attr "mode" "SI")]) + (define_insn "n" - [(set (match_operand:GPR 0 "register_operand" "=r") - (neg_bitwise:GPR - (not:GPR (match_operand:GPR 1 "register_operand" "r")) - (match_operand:GPR 2 "register_operand" "r")))] + [(set (match_operand:X 0 "register_operand" "=r") + (neg_bitwise:X + (not:X (match_operand:X 1 "register_operand" "r")) + (match_operand:X 2 "register_operand" "r")))] "" "n\t%0,%2,%1" [(set_attr "type" "logical") (set_attr "mode" "")]) +(define_insn "*nsi_internal" + [(set (match_operand:SI 0 "register_operand" "=r") + (neg_bitwise:SI + (not:SI (match_operand:SI 1 "register_operand" "r")) + (match_operand:SI 2 "register_operand" "r")))] + "TARGET_64BIT" + "n\t%0,%2,%1" + [(set_attr "type" "logical") + (set_attr "mode" "SI")]) ;; ;; .................... @@ -3167,7 +3210,6 @@ (define_expand "condjump" (label_ref (match_operand 1)) (pc)))]) - ;; ;; .................... @@ -3967,10 +4009,13 @@ (define_insn "bytepick_w_" (define_insn "bytepick_w__extend" [(set (match_operand:DI 0 "register_operand" "=r") (sign_extend:DI - (ior:SI (lshiftrt (match_operand:SI 1 "register_operand" "r") - (const_int )) - (ashift (match_operand:SI 2 "register_operand" "r") - (const_int bytepick_w_ashift_amount)))))] + (subreg:SI + (ior:DI (subreg:DI (lshiftrt + (match_operand:SI 1 "register_operand" "r") + (const_int )) 0) + (subreg:DI (ashift + (match_operand:SI 2 "register_operand" "r") + (const_int bytepick_w_ashift_amount)) 0)) 0)))] "TARGET_64BIT" "bytepick.w\t%0,%1,%2," [(set_attr "mode" "SI")]) diff --git a/gcc/testsuite/gcc.target/loongarch/sign-extend-bitwise.c b/gcc/testsuite/gcc.target/loongarch/sign-extend-bitwise.c new file mode 100644 index 00000000000..5753ef69db2 --- /dev/null +++ b/gcc/testsuite/gcc.target/loongarch/sign-extend-bitwise.c @@ -0,0 +1,21 @@ +/* { dg-do compile } */ +/* { dg-options "-mabi=lp64d -O2" } */ +/* { dg-final { scan-assembler-not "slli.w\t\\\$r\[0-9\]+,\\\$r\[0-9\]+,0" } } */ + +struct pmop +{ + unsigned int op_pmflags; + unsigned int op_pmpermflags; +}; +unsigned int PL_hints; + +struct pmop *pmop; +void +Perl_newPMOP (int type, int flags) +{ + if (PL_hints & 0x00100000) + pmop->op_pmpermflags |= 0x0001; + if (PL_hints & 0x00000004) + pmop->op_pmpermflags |= 0x0800; + pmop->op_pmflags = pmop->op_pmpermflags; +}