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[2620:52:3:1:0:246e:9693:128c]) by mx.google.com with ESMTPS id m4-20020a05620a290400b007811da867ebsi31434249qkp.446.2024.01.03.18.39.07 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 03 Jan 2024 18:39:07 -0800 (PST) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) client-ip=2620:52:3:1:0:246e:9693:128c; Authentication-Results: mx.google.com; arc=pass (i=1); spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org" Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 87324385E02A for ; Thu, 4 Jan 2024 02:39:07 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from eggs.gnu.org (eggs.gnu.org [IPv6:2001:470:142:3::10]) by sourceware.org (Postfix) with ESMTPS id 9A021385DC1D for ; Thu, 4 Jan 2024 02:38:28 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 9A021385DC1D Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=loongson.cn Authentication-Results: sourceware.org; spf=fail smtp.mailfrom=loongson.cn ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 9A021385DC1D Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=2001:470:142:3::10 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1704335910; cv=none; b=mOFy7T3qaGK5GMUOrANFn6rWwatLUtAcVVNFKtKxfqfvlBatKT8squXNo7/M9lTZILwlM17Iqvt4v7uFkinyRqdVWYDcW0NPGqrbZsDsoDh7ETEl9rWkm6PufPR7X5nJ0pG4XgLKBbN+nVhx8kzrk53vkmEU9gyrTyjflUKJV+M= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1704335910; c=relaxed/simple; bh=jESW04aXgUl43hvpzn6bTMsVdoCLyfH/t+LAnnxMlko=; h=From:To:Subject:Date:Message-Id:MIME-Version; b=ZrY3OwDS0Bg9DmLNcYTPOxhXSuAMJBOU4ivD0mNahD3iwInqrt+3QDUaC27DZsseIqePKJeV+9doha5/+Iu1yTPvxXkQ/COervgoDY0SyiZjsNfg5mkGd5oZJMHBtnwaYvZGhjNPF4l9gizgRwb22EmGw+UFDD/oTDl04EvCZic= ARC-Authentication-Results: i=1; server2.sourceware.org Received: from mail.loongson.cn ([114.242.206.163]) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rLDcb-00057n-Et for gcc-patches@gcc.gnu.org; Wed, 03 Jan 2024 21:38:28 -0500 Received: from loongson.cn (unknown [10.20.4.107]) by gateway (Coremail) with SMTP id _____8Dx+ekMGpZlgs8BAA--.2758S3; Thu, 04 Jan 2024 10:38:05 +0800 (CST) Received: from loongson-pc.loongson.cn (unknown [10.20.4.107]) by localhost.localdomain (Coremail) with SMTP id AQAAf8Cx798IGpZlrUsAAA--.819S2; Thu, 04 Jan 2024 10:38:01 +0800 (CST) From: Lulu Cheng To: gcc-patches@gcc.gnu.org Cc: xry111@xry111.site, i@xen0n.name, xuchenghua@loongson.cn, chenglulu@loongson.cn Subject: [PATCH] LoongArch: Fixed the problem of incorrect judgment of the immediate field of the [x]vld/[x]vst instruction. Date: Thu, 4 Jan 2024 10:37:53 +0800 Message-Id: <20240104023753.22590-1-chenglulu@loongson.cn> X-Mailer: git-send-email 2.20.1 MIME-Version: 1.0 X-CM-TRANSID: AQAAf8Cx798IGpZlrUsAAA--.819S2 X-CM-SenderInfo: xfkh0wpoxo3qxorr0wxvrqhubq/ X-Coremail-Antispam: 1Uk129KBj93XoW3WFWDKw18tw45tryUCrW7trc_yoWxKF43pr Zxuw17trW8Jrs2g34kJa45Xwn8tr4xGFW2vFW3Kr92kw1UX34UX3W8ArZaqFy5Xw4Fgr12 qF4Ivw1jqa1DKwcCm3ZEXasCq-sJn29KB7ZKAUJUUUU5529EdanIXcx71UUUUU7KY7ZEXa sCq-sGcSsGvfJ3Ic02F40EFcxC0VAKzVAqx4xG6I80ebIjqfuFe4nvWSU5nxnvy29KBjDU 0xBIdaVrnRJUUUk0b4IE77IF4wAFF20E14v26r1j6r4UM7CY07I20VC2zVCF04k26cxKx2 IYs7xG6rWj6s0DM7CIcVAFz4kK6r1j6r18M28lY4IEw2IIxxk0rwA2F7IY1VAKz4vEj48v e4kI8wA2z4x0Y4vE2Ix0cI8IcVAFwI0_JFI_Gr1l84ACjcxK6xIIjxv20xvEc7CjxVAFwI 0_Gr0_Cr1l84ACjcxK6I8E87Iv67AKxVWxJVW8Jr1l84ACjcxK6I8E87Iv6xkF7I0E14v2 6r4j6r4UJwAS0I0E0xvYzxvE52x082IY62kv0487Mc804VCY07AIYIkI8VC2zVCFFI0UMc 02F40EFcxC0VAKzVAqx4xG6I80ewAv7VC0I7IYx2IY67AKxVWUXVWUAwAv7VC2z280aVAF wI0_Jr0_Gr1lOx8S6xCaFVCjc4AY6r1j6r4UM4x0Y48IcxkI7VAKI48JMxAIw28IcxkI7V AKI48JMxC20s026xCaFVCjc4AY6r1j6r4UMI8I3I0E5I8CrVAFwI0_Jr0_Jr4lx2IqxVCj r7xvwVAFwI0_JrI_JrWlx4CE17CEb7AF67AKxVWUAVWUtwCIc40Y0x0EwIxGrwCI42IY6x IIjxv20xvE14v26r1j6r1xMIIF0xvE2Ix0cI8IcVCY1x0267AKxVWUJVW8JwCI42IY6xAI w20EY4v20xvaj40_Jr0_JF4lIxAIcVC2z280aVAFwI0_Jr0_Gr1lIxAIcVC2z280aVCY1x 0267AKxVWUJVW8JbIYCTnIWIevJa73UjIFyTuYvjxUwmhFDUUUU Received-SPF: pass client-ip=114.242.206.163; envelope-from=chenglulu@loongson.cn; helo=mail.loongson.cn X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-Spam-Status: No, score=-13.1 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, KAM_SHORT, SPF_FAIL, SPF_HELO_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1787125770842044653 X-GMAIL-MSGID: 1787125770842044653 The [x]vld/[x]vst directive is defined as follows: [x]vld/[x]vst {x/v}d, rj, si12 When not modified, the immediate field of [x]vld/[x]vst is between 10 and 14 bits depending on the type. However, in loongarch_valid_offset_p, the immediate field is restricted first, so there is no error. However, in some cases redundant instructions will be generated, see test cases. Now modify it according to the description in the instruction manual. gcc/ChangeLog: * config/loongarch/lasx.md (lasx_mxld_): Modify the method of determining the memory offset of [x]vld/[x]vst. (lasx_mxst_): Likewise. * config/loongarch/loongarch.cc (loongarch_valid_offset_p): Delete. (loongarch_address_insns): Likewise. * config/loongarch/lsx.md (lsx_ld_): Likewise. (lsx_st_): Likewise. * config/loongarch/predicates.md (aq10b_operand): Likewise. (aq10h_operand): Likewise. (aq10w_operand): Likewise. (aq10d_operand): Likewise. gcc/testsuite/ChangeLog: * gcc.target/loongarch/vect-ld-st-imm12.c: New test. --- gcc/config/loongarch/lasx.md | 26 ------------------- gcc/config/loongarch/loongarch.cc | 19 +++----------- gcc/config/loongarch/lsx.md | 26 ------------------- gcc/config/loongarch/predicates.md | 16 ------------ .../gcc.target/loongarch/vect-ld-st-imm12.c | 15 +++++++++++ 5 files changed, 19 insertions(+), 83 deletions(-) create mode 100644 gcc/testsuite/gcc.target/loongarch/vect-ld-st-imm12.c diff --git a/gcc/config/loongarch/lasx.md b/gcc/config/loongarch/lasx.md index dbbf5a136b7..95c6bae20ae 100644 --- a/gcc/config/loongarch/lasx.md +++ b/gcc/config/loongarch/lasx.md @@ -846,32 +846,6 @@ (define_split DONE; }) -;; Offset load -(define_expand "lasx_mxld_" - [(match_operand:LASX 0 "register_operand") - (match_operand 1 "pmode_register_operand") - (match_operand 2 "aq10_operand")] - "ISA_HAS_LASX" -{ - rtx addr = plus_constant (GET_MODE (operands[1]), operands[1], - INTVAL (operands[2])); - loongarch_emit_move (operands[0], gen_rtx_MEM (mode, addr)); - DONE; -}) - -;; Offset store -(define_expand "lasx_mxst_" - [(match_operand:LASX 0 "register_operand") - (match_operand 1 "pmode_register_operand") - (match_operand 2 "aq10_operand")] - "ISA_HAS_LASX" -{ - rtx addr = plus_constant (GET_MODE (operands[1]), operands[1], - INTVAL (operands[2])); - loongarch_emit_move (gen_rtx_MEM (mode, addr), operands[0]); - DONE; -}) - ;; LASX (define_insn "add3" [(set (match_operand:ILASX 0 "register_operand" "=f,f,f") diff --git a/gcc/config/loongarch/loongarch.cc b/gcc/config/loongarch/loongarch.cc index db83232884f..b82ef1a7c0a 100644 --- a/gcc/config/loongarch/loongarch.cc +++ b/gcc/config/loongarch/loongarch.cc @@ -2126,21 +2126,11 @@ loongarch_valid_offset_p (rtx x, machine_mode mode) /* We may need to split multiword moves, so make sure that every word is accessible. */ - if (GET_MODE_SIZE (mode) > UNITS_PER_WORD + if (!(LSX_SUPPORTED_MODE_P (mode) || LASX_SUPPORTED_MODE_P (mode)) + && GET_MODE_SIZE (mode) > UNITS_PER_WORD && !IMM12_OPERAND (INTVAL (x) + GET_MODE_SIZE (mode) - UNITS_PER_WORD)) return false; - /* LSX LD.* and ST.* supports 10-bit signed offsets. */ - if (LSX_SUPPORTED_MODE_P (mode) - && !loongarch_signed_immediate_p (INTVAL (x), 10, - loongarch_ldst_scaled_shift (mode))) - return false; - - /* LASX XVLD.B and XVST.B supports 10-bit signed offsets without shift. */ - if (LASX_SUPPORTED_MODE_P (mode) - && !loongarch_signed_immediate_p (INTVAL (x), 10, 0)) - return false; - return true; } @@ -2376,9 +2366,8 @@ loongarch_address_insns (rtx x, machine_mode mode, bool might_split_p) case ADDRESS_REG: if (lsx_p) { - /* LSX LD.* and ST.* supports 10-bit signed offsets. */ - if (loongarch_signed_immediate_p (INTVAL (addr.offset), 10, - loongarch_ldst_scaled_shift (mode))) + /* LSX LD.* and ST.* supports 12-bit signed offsets. */ + if (IMM12_OPERAND (INTVAL (addr.offset))) return 1; else return 0; diff --git a/gcc/config/loongarch/lsx.md b/gcc/config/loongarch/lsx.md index 3e3248ef499..02e89247bdf 100644 --- a/gcc/config/loongarch/lsx.md +++ b/gcc/config/loongarch/lsx.md @@ -812,32 +812,6 @@ (define_split DONE; }) -;; Offset load -(define_expand "lsx_ld_" - [(match_operand:LSX 0 "register_operand") - (match_operand 1 "pmode_register_operand") - (match_operand 2 "aq10_operand")] - "ISA_HAS_LSX" -{ - rtx addr = plus_constant (GET_MODE (operands[1]), operands[1], - INTVAL (operands[2])); - loongarch_emit_move (operands[0], gen_rtx_MEM (mode, addr)); - DONE; -}) - -;; Offset store -(define_expand "lsx_st_" - [(match_operand:LSX 0 "register_operand") - (match_operand 1 "pmode_register_operand") - (match_operand 2 "aq10_operand")] - "ISA_HAS_LSX" -{ - rtx addr = plus_constant (GET_MODE (operands[1]), operands[1], - INTVAL (operands[2])); - loongarch_emit_move (gen_rtx_MEM (mode, addr), operands[0]); - DONE; -}) - ;; Integer operations (define_insn "add3" [(set (match_operand:ILSX 0 "register_operand" "=f,f,f") diff --git a/gcc/config/loongarch/predicates.md b/gcc/config/loongarch/predicates.md index 4db444233c7..473063ccbff 100644 --- a/gcc/config/loongarch/predicates.md +++ b/gcc/config/loongarch/predicates.md @@ -167,22 +167,6 @@ (define_predicate "aq8d_operand" (and (match_code "const_int") (match_test "loongarch_signed_immediate_p (INTVAL (op), 8, 3)"))) -(define_predicate "aq10b_operand" - (and (match_code "const_int") - (match_test "loongarch_signed_immediate_p (INTVAL (op), 10, 0)"))) - -(define_predicate "aq10h_operand" - (and (match_code "const_int") - (match_test "loongarch_signed_immediate_p (INTVAL (op), 10, 1)"))) - -(define_predicate "aq10w_operand" - (and (match_code "const_int") - (match_test "loongarch_signed_immediate_p (INTVAL (op), 10, 2)"))) - -(define_predicate "aq10d_operand" - (and (match_code "const_int") - (match_test "loongarch_signed_immediate_p (INTVAL (op), 10, 3)"))) - (define_predicate "aq12b_operand" (and (match_code "const_int") (match_test "loongarch_signed_immediate_p (INTVAL (op), 12, 0)"))) diff --git a/gcc/testsuite/gcc.target/loongarch/vect-ld-st-imm12.c b/gcc/testsuite/gcc.target/loongarch/vect-ld-st-imm12.c new file mode 100644 index 00000000000..bfc208e4fe8 --- /dev/null +++ b/gcc/testsuite/gcc.target/loongarch/vect-ld-st-imm12.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-march=loongarch64 -mabi=lp64d -mlasx -O2" } */ +/* { dg-final { scan-assembler-not "addi.d" } } */ + +extern short a[1000]; +extern short b[1000]; +extern short c[1000]; + +void +test (void) +{ + for (int i = 501; i < 517; i++) + ((int *)(c + 1))[i] = ((int *)(a + 1))[i] + ((int *)(b + 1))[i]; +} +