From patchwork Tue Jan 2 09:23:40 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ezra Sitorus X-Patchwork-Id: 184297 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7301:6f82:b0:100:9c79:88ff with SMTP id tb2csp4346647dyb; Tue, 2 Jan 2024 01:27:13 -0800 (PST) X-Google-Smtp-Source: AGHT+IEYmynFG6x/gg5/VTYy0E7/3xIBEHbcwZ2MRGuY2yXc5ZnQOmFl9vzConZonH/hGTK8SG1N X-Received: by 2002:a05:622a:164c:b0:427:eb94:692e with SMTP id y12-20020a05622a164c00b00427eb94692emr15744795qtj.55.1704187633490; Tue, 02 Jan 2024 01:27:13 -0800 (PST) ARC-Seal: i=4; a=rsa-sha256; t=1704187633; cv=pass; d=google.com; s=arc-20160816; b=L78C7LtffRsOzT/Pyz08B+3/fuzofRe/770Jy57HOWSIJv53Uyq91Q326NW8mmBL8e n5teUPRJ9KGrB0BlBoWN1kH3h7BN8tunVpd7LOYxut4mN5wHLv0EpCvw+xjamibG28GB yOBiHykNHqvPgX8xvRTYGn2rJyPhPqnDCzorgsBPu9nsV2Z/zUGGPtlgJRhygVKQAx69 4LaedmdXr4KNRYLSTRs50HAZv5BPsohgTg52dL6kh89ZLYzljBulC4slr658VFevLV1P nyTF8U0VIl6FWfnOfVvJKG01hXaPNDSCzDgvNjvikGhIQLw6QMoVCHitsAAnAiE58tiN x6Uw== ARC-Message-Signature: i=4; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:nodisclaimer :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature:dkim-signature :arc-filter:dmarc-filter:delivered-to; bh=rZ1Mdz05uI2JWp8JqhSXMxzsI2346AH3bpESJcQb9eQ=; fh=Nfw27wyEgniZsGAEbsUUX37vOWF621moG02UMdzco6I=; b=LkXbOYypKy/NCI75nbnntxlt0FaoFwPvDJ6t/eb9ppexiei5zKPIcCwKdlOTYv79UA Bsm/26wfA0QSZEvwssYqc+yzaJxoNt5Q+WsxrEQWmmmoqaDJTmZUPORJNzbu2l9hHptz A08GK1A2dZxXhM/WoJvyV5n4jSLzZhTQIxy2IzSFdpOPCokspqttN6zPgKxntNdWPN8Y gga2EPrBpcK5DELEcuIOlaciQD+Y85dnmTs7CLRttdvAP844BkdL0UEmt7fjvjerdi11 4Lfz+5gWkzolzi8SIzrJW00ho3K0XYTkUFfoiPFAfqIscPS8lbFZwpwZ2pv8SKNfDtzi 7X+w== ARC-Authentication-Results: i=4; mx.google.com; dkim=pass header.i=@armh.onmicrosoft.com header.s=selector2-armh-onmicrosoft-com header.b="otWfsDr/"; dkim=pass header.i=@armh.onmicrosoft.com header.s=selector2-armh-onmicrosoft-com header.b="otWfsDr/"; arc=pass (i=3); spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=arm.com Received: from server2.sourceware.org (server2.sourceware.org. [8.43.85.97]) by mx.google.com with ESMTPS id 13-20020ac8590d000000b0042374c4031csi26930510qty.391.2024.01.02.01.27.13 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 02 Jan 2024 01:27:13 -0800 (PST) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) client-ip=8.43.85.97; Authentication-Results: mx.google.com; dkim=pass header.i=@armh.onmicrosoft.com header.s=selector2-armh-onmicrosoft-com header.b="otWfsDr/"; dkim=pass header.i=@armh.onmicrosoft.com header.s=selector2-armh-onmicrosoft-com header.b="otWfsDr/"; arc=pass (i=3); spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=arm.com Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id CFF9D3858438 for ; Tue, 2 Jan 2024 09:27:12 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from EUR04-HE1-obe.outbound.protection.outlook.com (mail-he1eur04on2078.outbound.protection.outlook.com [40.107.7.78]) by sourceware.org (Postfix) with ESMTPS id 7904A3858417 for ; Tue, 2 Jan 2024 09:24:05 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 7904A3858417 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=arm.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 7904A3858417 Authentication-Results: server2.sourceware.org; arc=pass smtp.remote-ip=40.107.7.78 ARC-Seal: i=3; a=rsa-sha256; d=sourceware.org; s=key; t=1704187450; cv=pass; b=XyhCMhWjfjXI9fXZs3txaJRRIr8RkxqaOcGFD3VoYl2Rm+VHLz9lKU9YUSsM1PHYPObFEULWN4dvisBHTk+C7xTjeYSujsMF6MJTbhN/3gcxtMHi/jvWH3yXUGGhJNx216cuSwcLff58Md4KkhNIRz+xp0O0bi0SMtHNrR6zIhc= ARC-Message-Signature: i=3; a=rsa-sha256; d=sourceware.org; s=key; t=1704187450; c=relaxed/simple; bh=/STG9qyOEGiv5+bbfqp+iP0cPpPvZZ+lVsvPeDw4QEM=; h=DKIM-Signature:DKIM-Signature:From:To:Subject:Date:Message-ID: MIME-Version; b=Lx6nceFeFyI/hiZeyWrJ1tzXXYRJ/WC8JVyWBjUN4u7JK5VBFdEo1xhMwWNOjfpd9vie+PEuPl4WwWfWzOKoPehfYgzw1SwJpGmrWvCwFt7UoJTEXiBmAq1xCw4kN5hPPUlRa7oLXSmsdiNmukK63haoDnvSgejSSEsA6jbRgoI= ARC-Authentication-Results: i=3; server2.sourceware.org ARC-Seal: i=2; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=pass; b=HdGzZ91ADOiVmDczxdALQVevw2PM2+vlMg+pn7cbWoc2ZCgp4Tr02oVFrZev/7W18vh2Br8E0hF8KncE+VD4COETHafGAYhCdzZbLfcnXS1KG0E5La0VzD1i5qmQ9Nm5LHCDzw3QmvTV0FUsm27jLIX61+ieUBu6TQr2xOppjeSIJJNsMrLi861G7DD6WE4afX0o2X+8wcTXywXjT1z86VKLWhEv+x1MLbGDrYfb5LAHAUEk8fTdvUraXXpxnNIUl/vlbLNmw4LRqKONQe4YfRcKHrO4pg5d20nPaUohOhQolv4xErQH6Ytu/14OZyT4k8AQs2nTYB9Jcch0Uo1vfQ== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=rZ1Mdz05uI2JWp8JqhSXMxzsI2346AH3bpESJcQb9eQ=; b=EtimpeczVkWHnF/iM1RQuGd37EgF8bGAldG3r3Fo9MmBbZHvDj5+1aYQOKb7xkIJwTd6fHrYQD9A24LnvYsbG9T+4hNebfK5OUDFeuHSzrPtzpgUcsAMKJGJ06UFYJB+nTnT6ah/HSw/oaUNSg3TA6Y/5nlZ5w6CuPxvINFSxj4RXmLrn+cRYFib5oD+zH1nUTBcmQagioZUUTlhurPsdjtWx8HdgTYhkMp30WluanRzrvJy5Q11VwidFLtsqn/Z40raJQ/TkTV2j3NdTr4ZB6ZjA208gsLktClH4LFyYIvvoNQFoXLWQ/WNLlsgJa4U5GSzcWTAk0z1sHfHJ1PDfw== ARC-Authentication-Results: i=2; mx.microsoft.com 1; spf=pass (sender ip is 63.35.35.123) smtp.rcpttodomain=gcc.gnu.org smtp.mailfrom=arm.com; dmarc=pass (p=none sp=none pct=100) action=none header.from=arm.com; dkim=pass (signature was verified) header.d=armh.onmicrosoft.com; arc=pass (0 oda=1 ltdi=1 spf=[1,1,smtp.mailfrom=arm.com] dmarc=[1,1,header.from=arm.com]) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=armh.onmicrosoft.com; s=selector2-armh-onmicrosoft-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=rZ1Mdz05uI2JWp8JqhSXMxzsI2346AH3bpESJcQb9eQ=; b=otWfsDr/tx80iaBETsUEzcVlKpwp02XPap+ORceCposopffe7dwIehyuZdjpOcc+62W0fGc/o+BAswDCTDItx2Mo8IgLaYXRCFw7Rfo1C4jpL4ebz3dS/GUm+TZdG4LU0eUEeORTGnKR4HYEbvhnmBzfmuhsiINYRWp1T7IFzXo= Received: from DU2PR04CA0299.eurprd04.prod.outlook.com (2603:10a6:10:28c::34) by PAVPR08MB9857.eurprd08.prod.outlook.com (2603:10a6:102:301::18) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7135.24; Tue, 2 Jan 2024 09:24:02 +0000 Received: from DU2PEPF0001E9C3.eurprd03.prod.outlook.com (2603:10a6:10:28c:cafe::1a) by DU2PR04CA0299.outlook.office365.com (2603:10a6:10:28c::34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7135.25 via Frontend Transport; Tue, 2 Jan 2024 09:24:01 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 63.35.35.123) smtp.mailfrom=arm.com; dkim=pass (signature was verified) header.d=armh.onmicrosoft.com;dmarc=pass action=none header.from=arm.com; Received-SPF: Pass (protection.outlook.com: domain of arm.com designates 63.35.35.123 as permitted sender) receiver=protection.outlook.com; client-ip=63.35.35.123; helo=64aa7808-outbound-1.mta.getcheckrecipient.com; pr=C Received: from 64aa7808-outbound-1.mta.getcheckrecipient.com (63.35.35.123) by DU2PEPF0001E9C3.mail.protection.outlook.com (10.167.8.72) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7159.9 via Frontend Transport; Tue, 2 Jan 2024 09:24:01 +0000 Received: ("Tessian outbound e243565b0037:v228"); Tue, 02 Jan 2024 09:24:01 +0000 X-CheckRecipientChecked: true X-CR-MTA-CID: b4029796d474de9c X-CR-MTA-TID: 64aa7808 Received: from 33c1aedc4feb.1 by 64aa7808-outbound-1.mta.getcheckrecipient.com id 02E4019D-703C-4F18-AF23-CCA47857421D.1; Tue, 02 Jan 2024 09:23:55 +0000 Received: from EUR05-VI1-obe.outbound.protection.outlook.com by 64aa7808-outbound-1.mta.getcheckrecipient.com with ESMTPS id 33c1aedc4feb.1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384); Tue, 02 Jan 2024 09:23:55 +0000 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=BIHPe4PwFPSOOBp+GkNgIDoPSL4fa85upOFxzPk+7QYYiCVUbDF1tOWhlB++iuxMox8QF1xoQGS5wcR+ohNUxUfi+NUoI3KR54S8c7xaDGme6w23WeAjcdFQEE+mABPy1BBXVgfG268RnOVwvaa+QIMnsbSX9voJg7lJr1wuH822YqtMXx0h7wK0r+vukUBTXf2CiG+ZKyu3gULfMPb6SNekOjF72JdE2O4jvqHPQ0HYkouTfM8/5gVitbwq4gfhSw4gX92Vsg7LTpSVLEQYcCGojB/sPVbokbiSy3Nz58M0fbfToJuKOetNEXMEM88xBEPA9B12/TLS4A4WouaW0w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=rZ1Mdz05uI2JWp8JqhSXMxzsI2346AH3bpESJcQb9eQ=; b=dS2snHr5mgDqNuEgP1dus80IgYXeSOJQ4GH0Kgej5mpa5ofsUfvACFyzuI4xwLavFyKG6SJqJfyjgNMhHrUHfLp0E6V88ug0Nk37BGUNr8WH6menCClh6QGOi3FOAPdS/sAAdJ5vF3BvzQHaue5SoCiMSTFgEdNcHF/9pSLOTKJbQRzMBrtMQhdGs2beckVF0Y6P1VKnYQDvtqp6U4RdXbTSYHTyKwvRdthmAKT9ZCCIJ3yaXn+xlmN8dhL+4ukDa0uWWZhuBFgpgY89/PlHOOQCdgXFIM4Aw63aGDouA/DHFh6NV0DzBRQY9WPsGvEfqNJKvwTVTVzj796jqgrAng== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 40.67.248.234) smtp.rcpttodomain=gcc.gnu.org smtp.mailfrom=arm.com; dmarc=pass (p=none sp=none pct=100) action=none header.from=arm.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=armh.onmicrosoft.com; s=selector2-armh-onmicrosoft-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=rZ1Mdz05uI2JWp8JqhSXMxzsI2346AH3bpESJcQb9eQ=; b=otWfsDr/tx80iaBETsUEzcVlKpwp02XPap+ORceCposopffe7dwIehyuZdjpOcc+62W0fGc/o+BAswDCTDItx2Mo8IgLaYXRCFw7Rfo1C4jpL4ebz3dS/GUm+TZdG4LU0eUEeORTGnKR4HYEbvhnmBzfmuhsiINYRWp1T7IFzXo= Received: from AM8P251CA0013.EURP251.PROD.OUTLOOK.COM (2603:10a6:20b:21b::18) by GV2PR08MB8169.eurprd08.prod.outlook.com (2603:10a6:150:78::8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7135.24; Tue, 2 Jan 2024 09:23:52 +0000 Received: from AMS0EPF000001AF.eurprd05.prod.outlook.com (2603:10a6:20b:21b:cafe::a) by AM8P251CA0013.outlook.office365.com (2603:10a6:20b:21b::18) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7135.25 via Frontend Transport; Tue, 2 Jan 2024 09:23:51 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 40.67.248.234) smtp.mailfrom=arm.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=arm.com; Received-SPF: Pass (protection.outlook.com: domain of arm.com designates 40.67.248.234 as permitted sender) receiver=protection.outlook.com; client-ip=40.67.248.234; helo=nebula.arm.com; pr=C Received: from nebula.arm.com (40.67.248.234) by AMS0EPF000001AF.mail.protection.outlook.com (10.167.16.155) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.7159.9 via Frontend Transport; Tue, 2 Jan 2024 09:23:51 +0000 Received: from AZ-NEU-EX04.Arm.com (10.251.24.32) by AZ-NEU-EX03.Arm.com (10.251.24.31) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.32; Tue, 2 Jan 2024 09:23:49 +0000 Received: from e127754.cambridge.arm.com (10.1.26.16) by mail.arm.com (10.251.24.32) with Microsoft SMTP Server id 15.1.2507.32 via Frontend Transport; Tue, 2 Jan 2024 09:23:49 +0000 From: To: CC: Subject: [PATCH v3 07/12] [GCC] arm: vst1q_types_x2 ACLE intrinsics Date: Tue, 2 Jan 2024 09:23:40 +0000 Message-ID: <20240102092345.28370-8-Ezra.Sitorus@arm.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20240102092345.28370-1-Ezra.Sitorus@arm.com> References: <20240102092345.28370-1-Ezra.Sitorus@arm.com> MIME-Version: 1.0 X-EOPAttributedMessage: 1 X-MS-TrafficTypeDiagnostic: AMS0EPF000001AF:EE_|GV2PR08MB8169:EE_|DU2PEPF0001E9C3:EE_|PAVPR08MB9857:EE_ X-MS-Office365-Filtering-Correlation-Id: 76238132-2136-43db-9cc4-08dc0b748eb2 x-checkrecipientrouted: true NoDisclaimer: true X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam-Untrusted: BCL:0; X-Microsoft-Antispam-Message-Info-Original: O7iTdIuFJNID9LA80GTQNfTsiwNON1E59nA7bs3pRFbcUZKqRmKQ6MvpwKq2m49Kx9aVM2Lmn9dQRB+ZJP8JzMEefwSPiOwDoSItQj0qRE0fPu8/vhEAUuHuZ/Fi/RLAm46EAijW3rrWztwdWgTUi3h4rkuLfY5m9iaPTA04cRdIu0kZBTmvdduntYM4kjv3C2+BSdWSyCs2RfX/UuqoI27rcIbEm4CywFJJ2dxEzBq1uFC89+xw5G8ZGw+KiyGr2ZjYJpIp4+oA7/NoA99826Dky2k+Dq/qOwYSDzTakt2ie4x+rWuddu9v0S89EO+rD7XBNKskWVpg0CWGB57fBI36fnbJ/32PJdDSDR3jyvJUUNwGYF7yryU1ARVTuSK21O3uUZZ/ZKm7EiXLFiOpgW/n59CTBolUy5JhKaiIH/U38VqHNlC5DQz+GIimZWTf4/OW0R4WEJSQTNL3xsl2ASiM8ZkxNQl6nvvmDfduDOhStIFvgc0eA4RDJsqmLe5wdIi0l3dsc588PqOi6gT2KGnIcL2ODURZ9ggk2ut3mAGZ1vlfK246vFRzDBqfFP2Roo+SiLzoj3WqA1yjP1K1Wbml8GaS4cWycu+8dZPUrTpDmnYj+kj4BaHWcWJuMqMB1Sx/228lEarKneqKPJmm30OHFfkoQ/ReG6ZPckNT22K/zHVQPOLdBEXj6EenJyRzq1cODxM0KEKR1aczcMznMnk0Rs9sfhvArMkmzHMomrP6St+3gYBJdX9JNKPfWNwNuoVDFsnXcsNs2ROUXpgtUlmKkiu17BSRg+ZOrebuatDSvAEt69Ej+u4s16pOo9Bk X-Forefront-Antispam-Report-Untrusted: CIP:40.67.248.234; CTRY:IE; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:nebula.arm.com; PTR:InfoDomainNonexistent; CAT:NONE; SFS:(13230031)(4636009)(39860400002)(136003)(396003)(376002)(346002)(230922051799003)(64100799003)(186009)(451199024)(1800799012)(82310400011)(36840700001)(46966006)(40470700004)(83380400001)(47076005)(81166007)(356005)(6916009)(36860700001)(82740400003)(316002)(70586007)(478600001)(966005)(5660300002)(70206006)(2876002)(2906002)(30864003)(4326008)(8936002)(8676002)(1076003)(2616005)(26005)(336012)(426003)(41300700001)(7696005)(6666004)(40460700003)(40480700001)(84970400001)(86362001)(36756003)(36900700001)(357404004); DIR:OUT; SFP:1101; X-MS-Exchange-Transport-CrossTenantHeadersStamped: GV2PR08MB8169 X-MS-Exchange-Transport-CrossTenantHeadersStripped: DU2PEPF0001E9C3.eurprd03.prod.outlook.com X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id-Prvs: 76e82300-ee9f-47a8-81b0-08dc0b7488d6 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: B8BKSG7M0WlvdiLuFnXEeLaWXoUs7GyTtgM+nQQz4nZ+F1vhKFyHN1yEV69DkIT+7QFstXI9iaT+O+9J38MNfcDRuXBhY2o/joK0GeMtDRc4lnNI1Ji8KwSzWsRMO/eMnR/gtOL/YFCzveS3MtgKvDGAGU/4l2y+OqoQ12paxNQV6DmuERxj2lJS4hj0/GptlXHUFlXfkpD4OV6qssoJLN0iz7lNFuwZQyfR4Pykcy63nL2mozA50d5q98Qz02qUX0PJWBXo/1tUHMYKwo2Dm6TvBNAxTWIFehAC6KU7oNL/9KLLRS26ZWMTz2hhCPBVh7Hwcr95va4AHVnx3zYNUgJ1lVd9qmrxTQeioXXlgXVHJJ3WuEZwqBLilEh8rgvtPtVkqGbX2oBrDu+8QrAOnObWsmXI09CbbrOsChGJnp0T1VkuwBdrbkuNeO0OtP/XeGX4dkMmsTFK5979X4GDg9JIGIIpFL1nXnczFSjpW8GtxqCz+CWAm3YzSlgwLVnF1fXTN2H9NpcoN+aG1hFWSBT7AW/gew4gbMnb03r4wOHOhBvbMxGmdGpw63Xka901aC22Zv6aAHz+qXgXgOLUeoYhjnpb6H32sKsZfJ/LXfeYcsJ4PL+m+812whKtEBEcseTJ4AcOCHhOAwc6p60dJSfrYJzyvT8Op7Zw0gkzLYNv6M3TZfWOvFKNGDrZPVIIeC7HaShb9v6ZzaAfPRQsiF1VY12SSTC6zFrrvfm0bsnnJ/SNq35/qBLOYA3Xkl9HnjGVTXnBJVmn8LWeFF7FTkewhI73H8IYjEiv+JSIoos= X-Forefront-Antispam-Report: CIP:63.35.35.123; CTRY:IE; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:64aa7808-outbound-1.mta.getcheckrecipient.com; PTR:ec2-63-35-35-123.eu-west-1.compute.amazonaws.com; CAT:NONE; SFS:(13230031)(4636009)(396003)(346002)(39860400002)(136003)(376002)(230922051799003)(451199024)(64100799003)(186009)(82310400011)(1800799012)(36840700001)(46966006)(40470700004)(336012)(83380400001)(426003)(26005)(1076003)(7696005)(2616005)(36860700001)(4326008)(47076005)(5660300002)(30864003)(70206006)(41300700001)(2876002)(2906002)(966005)(6916009)(478600001)(8676002)(8936002)(316002)(70586007)(86362001)(81166007)(36756003)(82740400003)(6666004)(40480700001)(40460700003)(84970400001)(357404004); DIR:OUT; SFP:1101; X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 02 Jan 2024 09:24:01.7793 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 76238132-2136-43db-9cc4-08dc0b748eb2 X-MS-Exchange-CrossTenant-Id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=f34e5979-57d9-4aaa-ad4d-b122a662184d; Ip=[63.35.35.123]; Helo=[64aa7808-outbound-1.mta.getcheckrecipient.com] X-MS-Exchange-CrossTenant-AuthSource: DU2PEPF0001E9C3.eurprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PAVPR08MB9857 X-Spam-Status: No, score=-12.0 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, FORGED_SPF_HELO, GIT_PATCH_0, KAM_DMARC_NONE, KAM_SHORT, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2, SPF_HELO_PASS, SPF_NONE, TXREP, T_SCC_BODY_TEXT_LINE, UNPARSEABLE_RELAY autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1786970251985934311 X-GMAIL-MSGID: 1786970251985934311 From: Ezra Sitorus This patch is part of a series of patches implementing the _xN variants of the vst1q intrinsic for the arm port. This patch adds the _x2 variants of the vst1q intrinsic. ACLE documents: https://developer.arm.com/documentation/ihi0053/latest/ ISA documents: https://developer.arm.com/documentation/ddi0487/latest/ gcc/ChangeLog: * config/arm/arm_neon.h (vst1q_u8_x2, vst1q_u16_x2, vst1q_u32_x2, vst1q_u64_x2): New. (vst1q_s8_x2, vst1q_s16_x2, vst1q_s32_x2, vst1q_s64_x2): New. (vst1q_f16_x2, vst1q_f32_x2): New. (vst1q_p8_x2, vst1q_p16_x2, vst1q_p64_x2): New. (vst1q_bf16_x2): New. * config/arm/arm_neon_builtins.def (vst1<_x2): New entries. * config/arm/neon.md (neon_vst1_x2): Updated from neon_vst1_x2. * config/arm/iterators.md (VMEMX2): New mode iterator. (VMEMX2_q): New mode attribute. gcc/testsuite/ChangeLog: * gcc.target/arm/simd/vst1q_base_xN_1.c: Add new tests. * gcc.target/arm/simd/vst1q_bf16_xN_1.c: Add new tests. * gcc.target/arm/simd/vst1q_fp16_xN_1.c: Add new tests. * gcc.target/arm/simd/vst1q_p64_xN_1.c: Add new tests. --- gcc/config/arm/arm_neon.h | 114 ++++++++++++++++++ gcc/config/arm/arm_neon_builtins.def | 1 + gcc/config/arm/iterators.md | 6 + gcc/config/arm/neon.md | 6 +- .../gcc.target/arm/simd/vst1q_base_xN_1.c | 70 +++++++++++ .../gcc.target/arm/simd/vst1q_bf16_xN_1.c | 13 ++ .../gcc.target/arm/simd/vst1q_fp16_xN_1.c | 13 ++ .../gcc.target/arm/simd/vst1q_p64_xN_1.c | 13 ++ 8 files changed, 233 insertions(+), 3 deletions(-) create mode 100644 gcc/testsuite/gcc.target/arm/simd/vst1q_base_xN_1.c create mode 100644 gcc/testsuite/gcc.target/arm/simd/vst1q_bf16_xN_1.c create mode 100644 gcc/testsuite/gcc.target/arm/simd/vst1q_fp16_xN_1.c create mode 100644 gcc/testsuite/gcc.target/arm/simd/vst1q_p64_xN_1.c diff --git a/gcc/config/arm/arm_neon.h b/gcc/config/arm/arm_neon.h index c9bdda39663..1c447b6d42f 100644 --- a/gcc/config/arm/arm_neon.h +++ b/gcc/config/arm/arm_neon.h @@ -11327,6 +11327,38 @@ vst1_s64_x2 (int64_t * __a, int64x1x2_t __b) __builtin_neon_vst1_x2di ((__builtin_neon_di *) __a, __bu.__o); } +__extension__ extern __inline void +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +vst1q_s8_x2 (int8_t * __a, int8x16x2_t __b) +{ + union { int8x16x2_t __i; __builtin_neon_oi __o; } __bu = { __b }; + __builtin_neon_vst1q_x2v16qi ((__builtin_neon_qi *) __a, __bu.__o); +} + +__extension__ extern __inline void +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +vst1q_s16_x2 (int16_t * __a, int16x8x2_t __b) +{ + union { int16x8x2_t __i; __builtin_neon_oi __o; } __bu = { __b }; + __builtin_neon_vst1q_x2v8hi ((__builtin_neon_hi *) __a, __bu.__o); +} + +__extension__ extern __inline void +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +vst1q_s32_x2 (int32_t * __a, int32x4x2_t __b) +{ + union { int32x4x2_t __i; __builtin_neon_oi __o; } __bu = { __b }; + __builtin_neon_vst1q_x2v4si ((__builtin_neon_si *) __a, __bu.__o); +} + +__extension__ extern __inline void +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +vst1q_s64_x2 (int64_t * __a, int64x2x2_t __b) +{ + union { int64x2x2_t __i; __builtin_neon_oi __o; } __bu = { __b }; + __builtin_neon_vst1q_x2v2di ((__builtin_neon_di *) __a, __bu.__o); +} + __extension__ extern __inline void __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vst1_s8_x3 (int8_t * __a, int8x8x3_t __b) @@ -11656,6 +11688,14 @@ vst1q_p64 (poly64_t * __a, poly64x2_t __b) __builtin_neon_vst1v2di ((__builtin_neon_di *) __a, (int64x2_t) __b); } +__extension__ extern __inline void +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +vst1q_p64_x2 (poly64_t * __a, poly64x2x2_t __b) +{ + union { poly64x2x2_t __i; __builtin_neon_oi __o; } __bu = { __b }; + __builtin_neon_vst1q_x2v2di ((__builtin_neon_di *) __a, __bu.__o); +} + #pragma GCC pop_options __extension__ extern __inline void __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) @@ -11701,6 +11741,24 @@ vst1q_f32 (float32_t * __a, float32x4_t __b) __builtin_neon_vst1v4sf ((__builtin_neon_sf *) __a, __b); } +#if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE) +__extension__ extern __inline void +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +vst1q_f16_x2 (float16_t * __a, float16x8x2_t __b) +{ + union { float16x8x2_t __i; __builtin_neon_oi __o; } __bu = { __b }; + __builtin_neon_vst1q_x2v8hf (__a, __bu.__o); +} +#endif + +__extension__ extern __inline void +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +vst1q_f32_x2 (float32_t * __a, float32x4x2_t __b) +{ + union { float32x4x2_t __i; __builtin_neon_oi __o; } __bu = { __b }; + __builtin_neon_vst1q_x2v4sf (__a, __bu.__o); +} + __extension__ extern __inline void __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vst1q_u8 (uint8_t * __a, uint8x16_t __b) @@ -11729,6 +11787,38 @@ vst1q_u64 (uint64_t * __a, uint64x2_t __b) __builtin_neon_vst1v2di ((__builtin_neon_di *) __a, (int64x2_t) __b); } +__extension__ extern __inline void +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +vst1q_u8_x2 (uint8_t * __a, uint8x16x2_t __b) +{ + union { uint8x16x2_t __i; __builtin_neon_oi __o; } __bu = { __b }; + __builtin_neon_vst1q_x2v16qi ((__builtin_neon_qi *) __a, __bu.__o); +} + +__extension__ extern __inline void +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +vst1q_u16_x2 (uint16_t * __a, uint16x8x2_t __b) +{ + union { uint16x8x2_t __i; __builtin_neon_oi __o; } __bu = { __b }; + __builtin_neon_vst1q_x2v8hi ((__builtin_neon_hi *) __a, __bu.__o); +} + +__extension__ extern __inline void +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +vst1q_u32_x2 (uint32_t * __a, uint32x4x2_t __b) +{ + union { uint32x4x2_t __i; __builtin_neon_oi __o; } __bu = { __b }; + __builtin_neon_vst1q_x2v4si ((__builtin_neon_si *) __a, __bu.__o); +} + +__extension__ extern __inline void +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +vst1q_u64_x2 (uint64_t * __a, uint64x2x2_t __b) +{ + union { uint64x2x2_t __i; __builtin_neon_oi __o; } __bu = { __b }; + __builtin_neon_vst1q_x2v2di ((__builtin_neon_di *) __a, __bu.__o); +} + __extension__ extern __inline void __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vst1q_p8 (poly8_t * __a, poly8x16_t __b) @@ -11743,6 +11833,22 @@ vst1q_p16 (poly16_t * __a, poly16x8_t __b) __builtin_neon_vst1v8hi ((__builtin_neon_hi *) __a, (int16x8_t) __b); } +__extension__ extern __inline void +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +vst1q_p8_x2 (poly8_t * __a, poly8x16x2_t __b) +{ + union { poly8x16x2_t __i; __builtin_neon_oi __o; } __bu = { __b }; + __builtin_neon_vst1q_x2v16qi ((__builtin_neon_qi *) __a, __bu.__o); +} + +__extension__ extern __inline void +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +vst1q_p16_x2 (poly16_t * __a, poly16x8x2_t __b) +{ + union { poly16x8x2_t __i; __builtin_neon_oi __o; } __bu = { __b }; + __builtin_neon_vst1q_x2v8hi ((__builtin_neon_hi *) __a, __bu.__o); +} + __extension__ extern __inline void __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vst1_lane_s8 (int8_t * __a, int8x8_t __b, const int __c) @@ -20419,6 +20525,14 @@ vst1q_bf16 (bfloat16_t * __a, bfloat16x8_t __b) __builtin_neon_vst1v8bf (__a, __b); } +__extension__ extern __inline void +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +vst1q_bf16_x2 (bfloat16_t * __a, bfloat16x8x2_t __b) +{ + union { bfloat16x8x2_t __i; __builtin_neon_oi __o; } __bu = { __b }; + __builtin_neon_vst1q_x2v8bf (__a, __bu.__o); +} + __extension__ extern __inline void __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vst2_bf16 (bfloat16_t * __ptr, bfloat16x4x2_t __val) diff --git a/gcc/config/arm/arm_neon_builtins.def b/gcc/config/arm/arm_neon_builtins.def index cb6d650c2e4..d44abb80139 100644 --- a/gcc/config/arm/arm_neon_builtins.def +++ b/gcc/config/arm/arm_neon_builtins.def @@ -312,6 +312,7 @@ VAR14 (STORE1, vst1, v8qi, v4hi, v4hf, v2si, v2sf, di, v16qi, v8hi, v8hf, v4si, v4sf, v2di, v4bf, v8bf) VAR7 (STORE1, vst1_x2, v8qi, v4hi, v2si, di, v4hf, v2sf, v4bf) +VAR7 (STORE1, vst1q_x2, v16qi, v8hi, v4si, v2di, v8hf, v4sf, v8bf) VAR7 (STORE1, vst1_x3, v8qi, v4hi, v2si, di, v4hf, v2sf, v4bf) VAR7 (STORE1, vst1_x4, v8qi, v4hi, v2si, di, v4hf, v2sf, v4bf) VAR14 (STORE1LANE, vst1_lane, diff --git a/gcc/config/arm/iterators.md b/gcc/config/arm/iterators.md index a9803538101..6c5a80d9348 100644 --- a/gcc/config/arm/iterators.md +++ b/gcc/config/arm/iterators.md @@ -141,6 +141,9 @@ ;; Opaque structure types used in table lookups (except vtbl1/vtbx1). (define_mode_iterator VTAB [TI EI OI]) +;; Opaque structure types for x2 variants of VSTR1/VSTR1Q or VLD1/VLD1Q. +(define_mode_iterator VMEMX2 [TI OI]) + ;; Widenable modes. (define_mode_iterator VW [V8QI V4HI V2SI]) @@ -1533,6 +1536,9 @@ ;; vtbl suffix for NEON vector modes. (define_mode_attr VTAB_n [(TI "2") (EI "3") (OI "4")]) +;; Suffix for x2 variants of vld1 and vst1. +(define_mode_attr VMEMX2_q [(TI "") (OI "q")]) + ;; fp16 or bf16 marker for 16-bit float modes. (define_mode_attr fporbf [(HF "fp16") (BF "bf16")]) diff --git a/gcc/config/arm/neon.md b/gcc/config/arm/neon.md index 96078aadcd5..270130c4086 100644 --- a/gcc/config/arm/neon.md +++ b/gcc/config/arm/neon.md @@ -5172,9 +5172,9 @@ if (BYTES_BIG_ENDIAN) "vst1.\t%h1, %A0" [(set_attr "type" "neon_store1_1reg")]) -(define_insn "neon_vst1_x2" - [(set (match_operand:TI 0 "neon_struct_operand" "=Um") - (unspec:TI [(match_operand:TI 1 "s_register_operand" "w") +(define_insn "neon_vst1_x2" + [(set (match_operand:VMEMX2 0 "neon_struct_operand" "=Um") + (unspec:VMEMX2 [(match_operand:VMEMX2 1 "s_register_operand" "w") (unspec:VDQX [(const_int 0)] UNSPEC_VSTRUCTDUMMY)] UNSPEC_VST1))] "TARGET_NEON" diff --git a/gcc/testsuite/gcc.target/arm/simd/vst1q_base_xN_1.c b/gcc/testsuite/gcc.target/arm/simd/vst1q_base_xN_1.c new file mode 100644 index 00000000000..232feafade0 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/simd/vst1q_base_xN_1.c @@ -0,0 +1,70 @@ +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O2" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + + +void test_vst1q_u8_x2 (uint8_t * ptr, uint8x16x2_t val) +{ + vst1q_u8_x2 (ptr, val); +} + +void test_vst1q_u16_x2 (uint16_t * ptr, uint16x8x2_t val) +{ + vst1q_u16_x2 (ptr, val); +} + +void test_vst1q_u32_x2 (uint32_t * ptr, uint32x4x2_t val) +{ + vst1q_u32_x2 (ptr, val); +} + +void test_vst1q_u64_x2 (uint64_t * ptr, uint64x2x2_t val) +{ + vst1q_u64_x2 (ptr, val); +} + +void test_vst1q_s8_x2 (int8_t * ptr, int8x16x2_t val) +{ + vst1q_s8_x2 (ptr, val); +} + +void test_vst1q_s16_x2 (int16_t * ptr, int16x8x2_t val) +{ + vst1q_s16_x2 (ptr, val); +} + +void test_vst1q_s32_x2 (int32_t * ptr, int32x4x2_t val) +{ + vst1q_s32_x2 (ptr, val); +} + +void test_vst1q_s64_x2 (int64_t * ptr, int64x2x2_t val) +{ + vst1q_s64_x2 (ptr, val); +} + +void test_vst1q_f32_x2 (float32_t * ptr, float32x4x2_t val) +{ + vst1q_f32_x2 (ptr, val); +} + +void test_vst1q_p8_x2 (poly8_t * ptr, poly8x16x2_t val) +{ + vst1q_p8_x2 (ptr, val); +} + +void test_vst1q_p16_x2 (poly16_t * ptr, poly16x8x2_t val) +{ + vst1q_p16_x2 (ptr, val); +} + +/* { dg-final { scan-assembler-times {vst1.8\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+\]\n} 3 } } */ + +/* { dg-final { scan-assembler-times {vst1.16\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+\]\n} 3 } } */ + +/* { dg-final { scan-assembler-times {vst1.32\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+\]\n} 3 } } */ + +/* { dg-final { scan-assembler-times {vst1.64\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+:64\]\n} 2 } } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vst1q_bf16_xN_1.c b/gcc/testsuite/gcc.target/arm/simd/vst1q_bf16_xN_1.c new file mode 100644 index 00000000000..2a4579f0aae --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/simd/vst1q_bf16_xN_1.c @@ -0,0 +1,13 @@ +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_v8_2a_bf16_neon_ok } */ +/* { dg-options "-save-temps -O2" } */ +/* { dg-add-options arm_v8_2a_bf16_neon } */ + +#include "arm_neon.h" + +void test_vst1q_bf16_x2 (bfloat16_t * ptr, bfloat16x8x2_t val) +{ + vst1q_bf16_x2 (ptr, val); +} + +/* { dg-final { scan-assembler-times {vst1.16\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+\]\n} 1 } } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vst1q_fp16_xN_1.c b/gcc/testsuite/gcc.target/arm/simd/vst1q_fp16_xN_1.c new file mode 100644 index 00000000000..61a7e558c48 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/simd/vst1q_fp16_xN_1.c @@ -0,0 +1,13 @@ +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_fp16_ok } */ +/* { dg-options "-save-temps -O2" } */ +/* { dg-add-options arm_neon_fp16 } */ + +#include "arm_neon.h" + +void test_vst1q_f16_x2 (float16_t * ptr, float16x8x2_t val) +{ + vst1q_f16_x2 (ptr, val); +} + +/* { dg-final { scan-assembler-times {vst1.16\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+\]\n} 1 } } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vst1q_p64_xN_1.c b/gcc/testsuite/gcc.target/arm/simd/vst1q_p64_xN_1.c new file mode 100644 index 00000000000..82f3dad293c --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/simd/vst1q_p64_xN_1.c @@ -0,0 +1,13 @@ +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_crypto_ok } */ +/* { dg-options "-save-temps -O2" } */ +/* { dg-add-options arm_crypto } */ + +#include "arm_neon.h" + +void test_vst1q_p64_x2 (poly64_t * ptr, poly64x2x2_t val) +{ + vst1q_p64_x2 (ptr, val); +} + +/* { dg-final { scan-assembler-times {vst1.64\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+:64\]\n} 1 } } */