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Ip=[63.35.35.123]; Helo=[64aa7808-outbound-1.mta.getcheckrecipient.com] X-MS-Exchange-CrossTenant-AuthSource: DU2PEPF0001E9C1.eurprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DU0PR08MB9227 X-Spam-Status: No, score=-12.1 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, FORGED_SPF_HELO, GIT_PATCH_0, KAM_DMARC_NONE, KAM_SHORT, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2, SPF_HELO_PASS, SPF_NONE, TXREP, T_SCC_BODY_TEXT_LINE, UNPARSEABLE_RELAY autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1786970253756436632 X-GMAIL-MSGID: 1786970253756436632 From: Ezra Sitorus This patch is part of a series of patches implementing the _xN variants of the vld1q intrinsic for the arm port. This patch adds the _x3 variants of the vld1q intrinsic. ACLE documents: https://developer.arm.com/documentation/ihi0053/latest/ ISA documents: https://developer.arm.com/documentation/ddi0487/latest/ gcc/ChangeLog: * config/arm/arm_neon.h (vld1q_u8_x3, vld1q_u16_x3, vld1q_u32_x3, vld1q_u64_x3): New. (vld1q_s8_x3, vld1q_s16_x3, vld1q_s32_x3, vld1q_s64_x3): New. (vld1q_f16_x3, vld1q_f32_x3): New. (vld1q_p8_x3, vld1q_p16_x3, vld1q_p64_x3): New. (vld1q_bf16_x3): New. * config/arm/arm_neon_builtins.def (vld1_x3): New entries. * config/arm/neon.md (neon_vld1_x3): New. (neon_vld1x3qa, neon_vld1x3qb): New. * config/arm/unspecs.md (UNSPEC_VLD1X3A, UNSPEC_VLD1X3B): New. gcc/testsuite/ChangeLog: * gcc.target/arm/simd/vld1q_base_xN_1.c: Add new tests. * gcc.target/arm/simd/vld1q_bf16_xN_1.c: Add new tests. * gcc.target/arm/simd/vld1q_fp16_xN_1.c: Add new tests. * gcc.target/arm/simd/vld1q_p64_xN_1.c: Add new tests. --- gcc/config/arm/arm_neon.h | 128 ++++++++++++++++++ gcc/config/arm/arm_neon_builtins.def | 1 + gcc/config/arm/neon.md | 48 +++++++ gcc/config/arm/unspecs.md | 2 + .../gcc.target/arm/simd/vld1q_base_xN_1.c | 69 +++++++++- .../gcc.target/arm/simd/vld1q_bf16_xN_1.c | 8 +- .../gcc.target/arm/simd/vld1q_fp16_xN_1.c | 7 +- .../gcc.target/arm/simd/vld1q_p64_xN_1.c | 7 +- 8 files changed, 263 insertions(+), 7 deletions(-) diff --git a/gcc/config/arm/arm_neon.h b/gcc/config/arm/arm_neon.h index 3eb41c6bdc8..557873ac028 100644 --- a/gcc/config/arm/arm_neon.h +++ b/gcc/config/arm/arm_neon.h @@ -10412,6 +10412,15 @@ vld1q_p64_x2 (const poly64_t * __a) return __rv.__i; } +__extension__ extern __inline poly64x2x3_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +vld1q_p64_x3 (const poly64_t * __a) +{ + union { poly64x2x3_t __i; __builtin_neon_ci __o; } __rv; + __rv.__o = __builtin_neon_vld1_x3v2di ((const __builtin_neon_di *) __a); + return __rv.__i; +} + #pragma GCC pop_options __extension__ extern __inline int8x16_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) @@ -10477,6 +10486,42 @@ vld1q_s64_x2 (const int64_t * __a) return __rv.__i; } +__extension__ extern __inline int8x16x3_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +vld1q_s8_x3 (const uint8_t * __a) +{ + union { int8x16x3_t __i; __builtin_neon_ci __o; } __rv; + __rv.__o = __builtin_neon_vld1_x3v16qi ((const __builtin_neon_qi *) __a); + return __rv.__i; +} + +__extension__ extern __inline int16x8x3_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +vld1q_s16_x3 (const uint16_t * __a) +{ + union { int16x8x3_t __i; __builtin_neon_ci __o; } __rv; + __rv.__o = __builtin_neon_vld1_x3v8hi ((const __builtin_neon_hi *) __a); + return __rv.__i; +} + +__extension__ extern __inline int32x4x3_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +vld1q_s32_x3 (const int32_t * __a) +{ + union { int32x4x3_t __i; __builtin_neon_ci __o; } __rv; + __rv.__o = __builtin_neon_vld1_x3v4si ((const __builtin_neon_si *) __a); + return __rv.__i; +} + +__extension__ extern __inline int64x2x3_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +vld1q_s64_x3 (const int64_t * __a) +{ + union { int64x2x3_t __i; __builtin_neon_ci __o; } __rv; + __rv.__o = __builtin_neon_vld1_x3v2di ((const __builtin_neon_di *) __a); + return __rv.__i; +} + #if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE) __extension__ extern __inline float16x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) @@ -10513,6 +10558,26 @@ vld1q_f32_x2 (const float32_t * __a) return __rv.__i; } +#if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE) +__extension__ extern __inline float16x8x3_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +vld1q_f16_x3 (const float16_t * __a) +{ + union { float16x8x3_t __i; __builtin_neon_ci __o; } __rv; + __rv.__o = __builtin_neon_vld1_x3v8hf (__a); + return __rv.__i; +} +#endif + +__extension__ extern __inline float32x4x3_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +vld1q_f32_x3 (const float32_t * __a) +{ + union { float32x4x3_t __i; __builtin_neon_ci __o; } __rv; + __rv.__o = __builtin_neon_vld1_x3v4sf ((const __builtin_neon_sf *) __a); + return __rv.__i; +} + __extension__ extern __inline uint8x16_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vld1q_u8 (const uint8_t * __a) @@ -10577,6 +10642,42 @@ vld1q_u64_x2 (const uint64_t * __a) return __rv.__i; } +__extension__ extern __inline uint8x16x3_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +vld1q_u8_x3 (const uint8_t * __a) +{ + union { uint8x16x3_t __i; __builtin_neon_ci __o; } __rv; + __rv.__o = __builtin_neon_vld1_x3v16qi ((const __builtin_neon_qi *) __a); + return __rv.__i; +} + +__extension__ extern __inline uint16x8x3_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +vld1q_u16_x3 (const uint16_t * __a) +{ + union { uint16x8x3_t __i; __builtin_neon_ci __o; } __rv; + __rv.__o = __builtin_neon_vld1_x3v8hi ((const __builtin_neon_hi *) __a); + return __rv.__i; +} + +__extension__ extern __inline uint32x4x3_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +vld1q_u32_x3 (const uint32_t * __a) +{ + union { uint32x4x3_t __i; __builtin_neon_ci __o; } __rv; + __rv.__o = __builtin_neon_vld1_x3v4si ((const __builtin_neon_si *) __a); + return __rv.__i; +} + +__extension__ extern __inline uint64x2x3_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +vld1q_u64_x3 (const uint64_t * __a) +{ + union { uint64x2x3_t __i; __builtin_neon_ci __o; } __rv; + __rv.__o = __builtin_neon_vld1_x3v2di ((const __builtin_neon_di *) __a); + return __rv.__i; +} + __extension__ extern __inline poly8x16_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vld1q_p8 (const poly8_t * __a) @@ -10609,6 +10710,24 @@ vld1q_p16_x2 (const poly16_t * __a) return __rv.__i; } +__extension__ extern __inline poly8x16x3_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +vld1q_p8_x3 (const poly8_t * __a) +{ + union { poly8x16x3_t __i; __builtin_neon_ci __o; } __rv; + __rv.__o = __builtin_neon_vld1_x3v16qi ((const __builtin_neon_qi *) __a); + return __rv.__i; +} + +__extension__ extern __inline poly16x8x3_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +vld1q_p16_x3 (const poly16_t * __a) +{ + union { poly16x8x3_t __i; __builtin_neon_ci __o; } __rv; + __rv.__o = __builtin_neon_vld1_x3v8hi ((const __builtin_neon_hi *) __a); + return __rv.__i; +} + __extension__ extern __inline int8x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vld1_lane_s8 (const int8_t * __a, int8x8_t __b, const int __c) @@ -19910,6 +20029,15 @@ vld1q_bf16_x2 (const bfloat16_t * __ptr) return __rv.__i; } +__extension__ extern __inline bfloat16x8x3_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +vld1q_bf16_x3 (const bfloat16_t * __ptr) +{ + union { bfloat16x8x3_t __i; __builtin_neon_oi __o; } __rv; + __rv.__o = __builtin_neon_vld1_x3v8bf ((const __builtin_neon_bf *) __ptr); + return __rv.__i; +} + __extension__ extern __inline bfloat16x4x2_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vld2_bf16 (bfloat16_t const * __ptr) diff --git a/gcc/config/arm/arm_neon_builtins.def b/gcc/config/arm/arm_neon_builtins.def index 5fadd255c18..57783bd0089 100644 --- a/gcc/config/arm/arm_neon_builtins.def +++ b/gcc/config/arm/arm_neon_builtins.def @@ -299,6 +299,7 @@ VAR1 (TERNOP, vtbx2, v8qi) VAR1 (TERNOP, vtbx3, v8qi) VAR1 (TERNOP, vtbx4, v8qi) VAR7 (LOAD1, vld1_x2, v16qi, v8hi, v4si, v2di, v8hf, v4sf, v8bf) +VAR7 (LOAD1, vld1_x3, v16qi, v8hi, v4si, v2di, v8hf, v4sf, v8bf) VAR13 (LOAD1, vld1, v8qi, v4hi, v4hf, v2si, v2sf, v16qi, v8hi, v8hf, v4si, v4sf, v2di, v4bf, v8bf) diff --git a/gcc/config/arm/neon.md b/gcc/config/arm/neon.md index 55049ea549f..235999e152a 100644 --- a/gcc/config/arm/neon.md +++ b/gcc/config/arm/neon.md @@ -4967,6 +4967,54 @@ if (BYTES_BIG_ENDIAN) [(set_attr "type" "neon_load1_2reg")] ) +(define_expand "neon_vld1_x3" + [(match_operand:CI 0 "s_register_operand") + (match_operand:CI 1 "neon_struct_operand") + (unspec:VQXBF [(const_int 0)] UNSPEC_VSTRUCTDUMMY)] + "TARGET_NEON" +{ + rtx mem = adjust_address (operands[1], EImode, 0); + emit_insn (gen_neon_vld1x3qa (operands[0], mem)); + mem = adjust_address (mem, EImode, GET_MODE_SIZE (EImode)); + emit_insn (gen_neon_vld1x3qb (operands[0], mem, operands[0])); + DONE; +}) + +(define_insn "neon_vld1x3qa" + [(set (match_operand:CI 0 "s_register_operand" "=w") + (unspec:CI [(match_operand:EI 1 "neon_struct_operand" "Um") + (unspec:VQXBF [(const_int 0)] UNSPEC_VSTRUCTDUMMY)] + UNSPEC_VLD1X3A))] + "TARGET_NEON" +{ + rtx ops[2]; + ops[0] = gen_rtx_REG (EImode, REGNO (operands[0])); + ops[1] = operands[1]; + + output_asm_insn ("vld1.\t%h0, %A1", ops); + return ""; +} + [(set_attr "type" "neon_load1_3reg")] +) + +(define_insn "neon_vld1x3qb" + [(set (match_operand:CI 0 "s_register_operand" "=w") + (unspec:CI [(match_operand:EI 1 "neon_struct_operand" "Um") + (match_operand:CI 2 "s_register_operand" "0") + (unspec:VQXBF [(const_int 0)] UNSPEC_VSTRUCTDUMMY)] + UNSPEC_VLD1X3B))] + "TARGET_NEON" +{ + rtx ops[2]; + ops[0] = gen_rtx_REG (EImode, REGNO (operands[0]) + 6); + ops[1] = operands[1]; + + output_asm_insn ("vld1.\t%h0, %A1", ops); + return ""; +} + [(set_attr "type" "neon_load1_3reg")] +) + ;; The lane numbers in the RTL are in GCC lane order, having been flipped ;; in arm_expand_neon_args. The lane numbers are restored to architectural ;; lane order here. diff --git a/gcc/config/arm/unspecs.md b/gcc/config/arm/unspecs.md index 4713ec840ab..e777edceef5 100644 --- a/gcc/config/arm/unspecs.md +++ b/gcc/config/arm/unspecs.md @@ -342,6 +342,8 @@ UNSPEC_VHSUB_S UNSPEC_VHSUB_U UNSPEC_VLD1 + UNSPEC_VLD1X3A + UNSPEC_VLD1X3B UNSPEC_VLD1_LANE UNSPEC_VLD2 UNSPEC_VLD2_DUP diff --git a/gcc/testsuite/gcc.target/arm/simd/vld1q_base_xN_1.c b/gcc/testsuite/gcc.target/arm/simd/vld1q_base_xN_1.c index 1d31777afdf..117bc58c161 100644 --- a/gcc/testsuite/gcc.target/arm/simd/vld1q_base_xN_1.c +++ b/gcc/testsuite/gcc.target/arm/simd/vld1q_base_xN_1.c @@ -60,8 +60,69 @@ poly16x8x2_t test_vld1q_p16_x2 (poly16_t * a) return vld1q_p16_x2 (a); } -/* { dg-final { scan-assembler-times {vld1.8\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+\]\n} 3 } } */ -/* { dg-final { scan-assembler-times {vld1.16\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+\]\n} 3 } } */ -/* { dg-final { scan-assembler-times {vld1.32\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+\]\n} 3 } } */ -/* { dg-final { scan-assembler-times {vld1.64\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+:64\]\n} 2 } } */ +uint8x16x3_t test_vld1q_u8_x3 (uint8_t * a) +{ + return vld1q_u8_x3 (a); +} + +uint16x8x3_t test_vld1q_u16_x3 (uint16_t * a) +{ + return vld1q_u16_x3 (a); +} + +uint32x4x3_t test_vld1q_u32_x3 (uint32_t * a) +{ + return vld1q_u32_x3 (a); +} + +uint64x2x3_t test_vld1q_u64_x3 (uint64_t * a) +{ + return vld1q_u64_x3 (a); +} + +int8x16x3_t test_vld1q_s8_x3 (int8_t * a) +{ + return vld1q_s8_x3 (a); +} + +int16x8x3_t test_vld1q_s16_x3 (int16_t * a) +{ + return vld1q_s16_x3 (a); +} + +int32x4x3_t test_vld1q_s32_x3 (int32_t * a) +{ + return vld1q_s32_x3 (a); +} + +int64x2x3_t test_vld1q_s64_x3 (int64_t * a) +{ + return vld1q_s64_x3 (a); +} + +float32x4x3_t test_vld1q_f32_x3 (float32_t * a) +{ + return vld1q_f32_x3 (a); +} + +poly8x16x3_t test_vld1q_p8_x3 (poly8_t * a) +{ + return vld1q_p8_x3 (a); +} + +poly16x8x3_t test_vld1q_p16_x3 (poly16_t * a) +{ + return vld1q_p16_x3 (a); +} + +/* { dg-final { scan-assembler-times {vld1.8\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+\]\n} 6 } } */ +/* { dg-final { scan-assembler-times {vld1.8\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+\]!\n} 3 } } */ + +/* { dg-final { scan-assembler-times {vld1.16\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+\]\n} 6 } } */ +/* { dg-final { scan-assembler-times {vld1.16\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+\]!\n} 3 } } */ + +/* { dg-final { scan-assembler-times {vld1.32\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+\]\n} 6 } } */ +/* { dg-final { scan-assembler-times {vld1.32\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+\]!\n} 3 } } */ +/* { dg-final { scan-assembler-times {vld1.64\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+:64\]\n} 4 } } */ +/* { dg-final { scan-assembler-times {vld1.64\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+:64\]!\n} 2 } } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vld1q_bf16_xN_1.c b/gcc/testsuite/gcc.target/arm/simd/vld1q_bf16_xN_1.c index 5f6fc98640e..75b61f1ecf0 100644 --- a/gcc/testsuite/gcc.target/arm/simd/vld1q_bf16_xN_1.c +++ b/gcc/testsuite/gcc.target/arm/simd/vld1q_bf16_xN_1.c @@ -10,4 +10,10 @@ bfloat16x8x2_t test_vld1q_bf16_x2 (bfloat16_t * a) return vld1q_bf16_x2 (a); } -/* { dg-final { scan-assembler-times {vld1.16\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+\]\n} 1 } } */ +bfloat16x8x3_t test_vld1q_bf16_x3 (bfloat16_t * a) +{ + return vld1q_bf16_x3 (a); +} + +/* { dg-final { scan-assembler-times {vld1.16\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+\]\n} 2 } } */ +/* { dg-final { scan-assembler-times {vld1.16\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+\]!\n} 1 } } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vld1q_fp16_xN_1.c b/gcc/testsuite/gcc.target/arm/simd/vld1q_fp16_xN_1.c index aecf491a4de..9032048bed5 100644 --- a/gcc/testsuite/gcc.target/arm/simd/vld1q_fp16_xN_1.c +++ b/gcc/testsuite/gcc.target/arm/simd/vld1q_fp16_xN_1.c @@ -10,5 +10,10 @@ float16x8x2_t test_vld1q_f16_x2 (float16_t * a) return vld1q_f16_x2 (a); } -/* { dg-final { scan-assembler-times {vld1.16\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+\]\n} 1 } } */ +float16x8x3_t test_vld1q_f16_x3 (float16_t * a) +{ + return vld1q_f16_x3 (a); +} +/* { dg-final { scan-assembler-times {vld1.16\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+\]\n} 2 } } */ +/* { dg-final { scan-assembler-times {vld1.16\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+\]!\n} 1 } } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vld1q_p64_xN_1.c b/gcc/testsuite/gcc.target/arm/simd/vld1q_p64_xN_1.c index 04ceb5e4a24..aabc31bbd08 100644 --- a/gcc/testsuite/gcc.target/arm/simd/vld1q_p64_xN_1.c +++ b/gcc/testsuite/gcc.target/arm/simd/vld1q_p64_xN_1.c @@ -10,5 +10,10 @@ poly64x2x2_t test_vld1q_p64_x2 (poly64_t * a) return vld1q_p64_x2 (a); } -/* { dg-final { scan-assembler-times {vld1.64\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+:64\]\n} 1 } } */ +poly64x2x3_t test_vld1q_p64_x3 (poly64_t * a) +{ + return vld1q_p64_x3 (a); +} +/* { dg-final { scan-assembler-times {vld1.64\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+:64\]\n} 2 } } */ +/* { dg-final { scan-assembler-times {vld1.64\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+:64\]!\n} 1 } } */