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(unknown [IPv6:240e:358:11fc:5500:dc73:854d:832e:3]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (P-384) server-digest SHA384) (Client did not present a certificate) (Authenticated sender: xry111@xry111.site) by xry111.site (Postfix) with ESMTPSA id 31EBA66A0F; Sun, 31 Dec 2023 14:17:48 -0500 (EST) From: Xi Ruoyao To: gcc-patches@gcc.gnu.org Cc: chenglulu , Richard Sandiford , i@xen0n.name, xuchenghua@loongson.cn, chenxiaolong@loongson.cn, Xi Ruoyao Subject: [PATCH] LoongArch: Provide fmin/fmax RTL pattern for vectors Date: Mon, 1 Jan 2024 03:15:10 +0800 Message-ID: <20231231191738.126529-1-xry111@xry111.site> X-Mailer: git-send-email 2.43.0 MIME-Version: 1.0 X-Spam-Status: No, score=-9.1 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, KAM_SHORT, LIKELY_SPAM_FROM, SPF_HELO_PASS, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1786826263217375916 X-GMAIL-MSGID: 1786826263217375916 We already had smin/smax RTL pattern using vfmin/vfmax instructions. But for smin/smax, it's unspecified what will happen if either operand contains any NaN operands. So we would not vectorize the loop with -fno-finite-math-only (the default for all optimization levels expect -Ofast). But, LoongArch vfmin/vfmax instruction is IEEE-754-2008 conformant so we can also use them and vectorize the loop. gcc/ChangeLog: * config/loongarch/simd.md (fmax3): New define_insn. (fmin3): Likewise. (reduc_fmax_scal_3): New define_expand. (reduc_fmin_scal_3): Likewise. gcc/testsuite/ChangeLog: * gcc.target/loongarch/vfmax-vfmin.c: New test. --- Happy new year folks. This is a follow-up of [1]. Bootstrapped and regtested on loongarch64-linux-gnu. Ok for trunk? [1]:https://gcc.gnu.org/pipermail/gcc-patches/2023-December/641583.html gcc/config/loongarch/simd.md | 31 +++++++++++++++++++ .../gcc.target/loongarch/vfmax-vfmin.c | 31 +++++++++++++++++++ 2 files changed, 62 insertions(+) create mode 100644 gcc/testsuite/gcc.target/loongarch/vfmax-vfmin.c diff --git a/gcc/config/loongarch/simd.md b/gcc/config/loongarch/simd.md index 93fb39abcf5..8ac1d75a85c 100644 --- a/gcc/config/loongarch/simd.md +++ b/gcc/config/loongarch/simd.md @@ -426,6 +426,37 @@ (define_insn "_vfcmp__" [(set_attr "type" "simd_fcmp") (set_attr "mode" "")]) +; [x]vf{min/max} instructions are IEEE-754-2008 conforming, use them for +; the corresponding IEEE-754-2008 operations. We must use UNSPEC instead +; of smin/smax though, see PR105414 and PR107013. + +(define_int_iterator UNSPEC_FMAXMIN [UNSPEC_FMAX UNSPEC_FMIN]) +(define_int_attr fmaxmin [(UNSPEC_FMAX "fmax") (UNSPEC_FMIN "fmin")]) + +(define_insn "3" + [(set (match_operand:FVEC 0 "register_operand" "=f") + (unspec:FVEC [(match_operand:FVEC 1 "register_operand" "f") + (match_operand:FVEC 2 "register_operand" "f")] + UNSPEC_FMAXMIN))] + "" + "v.\t%0,%1,%2" + [(set_attr "type" "simd_fminmax") + (set_attr "mode" "")]) + +;; ... and also reduc operations. +(define_expand "reduc__scal_" + [(match_operand: 0 "register_operand") + (match_operand:FVEC 1 "register_operand") + (const_int UNSPEC_FMAXMIN)] + "" +{ + rtx tmp = gen_reg_rtx (mode); + loongarch_expand_vector_reduc (gen_3, tmp, operands[1]); + emit_insn (gen_vec_extract (operands[0], tmp, + const0_rtx)); + DONE; +}) + ; The LoongArch SX Instructions. (include "lsx.md") diff --git a/gcc/testsuite/gcc.target/loongarch/vfmax-vfmin.c b/gcc/testsuite/gcc.target/loongarch/vfmax-vfmin.c new file mode 100644 index 00000000000..811fee361c3 --- /dev/null +++ b/gcc/testsuite/gcc.target/loongarch/vfmax-vfmin.c @@ -0,0 +1,31 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -mtune=la464 -mlasx" } */ +/* { dg-final { scan-assembler "\tvfmin\\.d" } } */ +/* { dg-final { scan-assembler "\tvfmax\\.d" } } */ +/* { dg-final { scan-assembler "\txvfmin\\.d" } } */ +/* { dg-final { scan-assembler "\txvfmax\\.d" } } */ +/* { dg-final { scan-assembler "\tvfmin\\.s" } } */ +/* { dg-final { scan-assembler "\tvfmax\\.s" } } */ +/* { dg-final { scan-assembler "\txvfmin\\.s" } } */ +/* { dg-final { scan-assembler "\txvfmax\\.s" } } */ + +#define T(OP) __typeof__ (__builtin_##OP (0, 0)) + +#define TEST(OP, LEN) \ +void \ +test_##OP##LEN (T (OP) *restrict dest, \ + const T (OP) *restrict src1, \ + const T (OP) *restrict src2) \ +{ \ + for (int i = 0; i < LEN / sizeof (T(OP)); i++) \ + dest[i] = __builtin_##OP (src1[i], src2[i]); \ +} + +TEST(fmin, 16) +TEST(fmax, 16) +TEST(fmin, 32) +TEST(fmax, 32) +TEST(fminf, 16) +TEST(fmaxf, 16) +TEST(fminf, 32) +TEST(fmaxf, 32)