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[2620:52:3:1:0:246e:9693:128c]) by mx.google.com with ESMTPS id ge19-20020a05622a5c9300b00427f206d0c5si4215738qtb.329.2023.12.28.17.23.02 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 28 Dec 2023 17:23:02 -0800 (PST) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) client-ip=2620:52:3:1:0:246e:9693:128c; Authentication-Results: mx.google.com; arc=pass (i=1); spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org" Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 0C8893858414 for ; Fri, 29 Dec 2023 01:23:02 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from smtpbgau1.qq.com (smtpbgau1.qq.com [54.206.16.166]) by sourceware.org (Postfix) with ESMTPS id B22EB3858D28 for ; Fri, 29 Dec 2023 01:21:26 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org B22EB3858D28 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=rivai.ai Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=rivai.ai ARC-Filter: OpenARC Filter v1.0.0 sourceware.org B22EB3858D28 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=54.206.16.166 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1703812893; cv=none; b=S9AbKjfta7q6l3JxO8+wf5JihaBXlC/j48BkUv2UvzcYIt0ELKdAo2lfvTSKuepZ6dWiT7jvhbkUFCKxpDGbd0zEHKko3DSwM2dbjjkrcuKBK36CEWOw5ffzvcf0/PLCse+GEKAghiXoM9BevCyLdJeY/8EAPTH5meaWVJpLMpY= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1703812893; c=relaxed/simple; bh=M4Rr1UqT1AAxHvcn2tST0uUE9KePKZDiaqlXNWuGkco=; h=From:To:Subject:Date:Message-Id:MIME-Version; b=MaiL5IAaytsr41jwYfQXkBmmgl2d6pXXrt9CoOh9y2SXoao/AsDGJMRTTusXpnAW0WvPqn3Tfo0E8LMWBbPVahPZH6IfponCflBQYUGzsf/J8gAbNeoMoNiJA3X4aHX+4abA9pQ4Ym3JtKbekfR/g7Mk19icbulw0sQ/w4FFVUo= ARC-Authentication-Results: i=1; server2.sourceware.org X-QQ-mid: bizesmtp66t1703812864t88qn12f Received: from rios-cad122.hadoop.rioslab.org ( [58.60.1.26]) by bizesmtp.qq.com (ESMTP) with id ; Fri, 29 Dec 2023 09:21:03 +0800 (CST) X-QQ-SSF: 01400000000000G0V000000A0000000 X-QQ-FEAT: 4MPk5pQyRCX7BDMp5OIKkAbQm4yup+2TLoJ/W9ks1wh36sj10qXq6PoEG4KI5 TVQ395S3zXM4lBeuUSUHWJKlPvJaTxph1XtpwCDrZRb82vI8Az2nPlWnduU279KF65wxRkK noiPdFHg0mTnI2l28r/60b8Nxa1G9cKqnP6YfZSZ9L72eNMwlqYBxQGGKVNC1JTzSGo+yo4 FhQM9ko5rPKUUic7Nh4Z7ThUgrr0DCGYqTlZuXCftc3qWFQBHdj7E/OghdV1edu6rUrSvmL HuQGBtsmu93/C1Y3SRiOBGkpW2dpToHihoFngiFMky6e5u/KG77pBJR0sAhLQWbzHagzQGx Vd34kLej2Q9g8/3wEDPj3v6T53n7bIO26V6lIFe X-QQ-GoodBg: 2 X-BIZMAIL-ID: 3420226717567248506 From: Juzhe-Zhong To: gcc-patches@gcc.gnu.org Cc: kito.cheng@gmail.com, kito.cheng@sifive.com, jeffreyalaw@gmail.com, rdapp.gcc@gmail.com, Juzhe-Zhong Subject: [PATCH] RISC-V: Count pointer type SSA into RVV regs liveness for dynamic LMUL cost model Date: Fri, 29 Dec 2023 09:21:02 +0800 Message-Id: <20231229012102.2424314-1-juzhe.zhong@rivai.ai> X-Mailer: git-send-email 2.36.3 MIME-Version: 1.0 X-QQ-SENDSIZE: 520 Feedback-ID: bizesmtp:rivai.ai:qybglogicsvrgz:qybglogicsvrgz7a-one-0 X-Spam-Status: No, score=-10.3 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, RCVD_IN_BARRACUDACENTRAL, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2, SPF_HELO_PASS, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1786577401803261756 X-GMAIL-MSGID: 1786577401803261756 This patch fixes the following choosing unexpected big LMUL which cause register spillings. Before this patch, choosing LMUL = 4: addi sp,sp,-160 addiw t1,a2,-1 li a5,7 bleu t1,a5,.L16 vsetivli zero,8,e64,m4,ta,ma vmv.v.x v4,a0 vs4r.v v4,0(sp) ---> spill to the stack. vmv.v.x v4,a1 addi a5,sp,64 vs4r.v v4,0(a5) ---> spill to the stack. The root cause is the following codes: if (poly_int_tree_p (var) || (is_gimple_val (var) && !POINTER_TYPE_P (TREE_TYPE (var)))) We count the variable as consuming a RVV reg group when it is not POINTER_TYPE. It is right for load/store STMT for example: _1 = (MEM)*addr --> addr won't be allocated an RVV vector group. However, we find it is not right for non-load/store STMT: _3 = _1 == x_8(D); _1 is pointer type too but we does allocate a RVV register group for it. So after this patch, we are choosing the perfect LMUL for the testcase in this patch: ble a2,zero,.L17 addiw a7,a2,-1 li a5,3 bleu a7,a5,.L15 srliw a5,a7,2 slli a6,a5,1 add a6,a6,a5 lui a5,%hi(replacements) addi t1,a5,%lo(replacements) slli a6,a6,5 lui t4,%hi(.LANCHOR0) lui t3,%hi(.LANCHOR0+8) lui a3,%hi(.LANCHOR0+16) lui a4,%hi(.LC1) vsetivli zero,4,e16,mf2,ta,ma addi t4,t4,%lo(.LANCHOR0) addi t3,t3,%lo(.LANCHOR0+8) addi a3,a3,%lo(.LANCHOR0+16) addi a4,a4,%lo(.LC1) add a6,t1,a6 addi a5,a5,%lo(replacements) vle16.v v18,0(t4) vle16.v v17,0(t3) vle16.v v16,0(a3) vmsgeu.vi v25,v18,4 vadd.vi v24,v18,-4 vmsgeu.vi v23,v17,4 vadd.vi v22,v17,-4 vlm.v v21,0(a4) vmsgeu.vi v20,v16,4 vadd.vi v19,v16,-4 vsetvli zero,zero,e64,m2,ta,mu vmv.v.x v12,a0 vmv.v.x v14,a1 .L4: vlseg3e64.v v6,(a5) vmseq.vv v2,v6,v12 vmseq.vv v0,v8,v12 vmsne.vv v1,v8,v12 vmand.mm v1,v1,v2 vmerge.vvm v2,v8,v14,v0 vmv1r.v v0,v1 addi a4,a5,24 vmerge.vvm v6,v6,v14,v0 vmerge.vim v2,v2,0,v0 vrgatherei16.vv v4,v6,v18 vmv1r.v v0,v25 vrgatherei16.vv v4,v2,v24,v0.t vs1r.v v4,0(a5) addi a3,a5,48 vmv1r.v v0,v21 vmv2r.v v4,v2 vcompress.vm v4,v6,v0 vs1r.v v4,0(a4) vmv1r.v v0,v23 addi a4,a5,72 vrgatherei16.vv v4,v6,v17 vrgatherei16.vv v4,v2,v22,v0.t vs1r.v v4,0(a3) vmv1r.v v0,v20 vrgatherei16.vv v4,v6,v16 addi a5,a5,96 vrgatherei16.vv v4,v2,v19,v0.t vs1r.v v4,0(a4) bne a6,a5,.L4 No spillings, no "sp" register used. Tested on both RV32 and RV64, no regression. Ok for trunk ? PR target/113112 gcc/ChangeLog: * config/riscv/riscv-vector-costs.cc (compute_nregs_for_mode): Fix pointer type liveness count. gcc/testsuite/ChangeLog: * gcc.dg/vect/costmodel/riscv/rvv/pr113112-4.c: New test. --- gcc/config/riscv/riscv-vector-costs.cc | 12 ++++++-- .../vect/costmodel/riscv/rvv/pr113112-4.c | 28 +++++++++++++++++++ 2 files changed, 37 insertions(+), 3 deletions(-) create mode 100644 gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/pr113112-4.c diff --git a/gcc/config/riscv/riscv-vector-costs.cc b/gcc/config/riscv/riscv-vector-costs.cc index 0c485dc4f29..b41a79429d4 100644 --- a/gcc/config/riscv/riscv-vector-costs.cc +++ b/gcc/config/riscv/riscv-vector-costs.cc @@ -277,9 +277,12 @@ compute_local_live_ranges ( { unsigned int point = program_point.point; gimple *stmt = program_point.stmt; + stmt_vec_info stmt_info = program_point.stmt_info; tree lhs = gimple_get_lhs (stmt); if (lhs != NULL_TREE && is_gimple_reg (lhs) - && !POINTER_TYPE_P (TREE_TYPE (lhs))) + && (!POINTER_TYPE_P (TREE_TYPE (lhs)) + || STMT_VINFO_TYPE (vect_stmt_to_vectorize (stmt_info)) + != store_vec_info_type)) { biggest_mode = get_biggest_mode (biggest_mode, TYPE_MODE (TREE_TYPE (lhs))); @@ -305,7 +308,10 @@ compute_local_live_ranges ( the future. */ if (poly_int_tree_p (var) || (is_gimple_val (var) - && !POINTER_TYPE_P (TREE_TYPE (var)))) + && (!POINTER_TYPE_P (TREE_TYPE (var)) + || STMT_VINFO_TYPE ( + vect_stmt_to_vectorize (stmt_info)) + != load_vec_info_type))) { biggest_mode = get_biggest_mode (biggest_mode, @@ -374,7 +380,7 @@ compute_nregs_for_mode (machine_mode mode, machine_mode biggest_mode, int lmul) unsigned int biggest_size = GET_MODE_SIZE (biggest_mode).to_constant (); gcc_assert (biggest_size >= mode_size); unsigned int ratio = biggest_size / mode_size; - return lmul / ratio; + return MAX (lmul / ratio, 1); } /* This function helps to determine whether current LMUL will cause diff --git a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/pr113112-4.c b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/pr113112-4.c new file mode 100644 index 00000000000..5c55a66ed77 --- /dev/null +++ b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/pr113112-4.c @@ -0,0 +1,28 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -Ofast -ftree-vectorize --param riscv-autovec-lmul=dynamic --param riscv-autovec-preference=fixed-vlmax -fno-schedule-insns -fno-schedule-insns2" } */ + +typedef struct rtx_def *rtx; +struct replacement { + rtx *where; + rtx *subreg_loc; + int mode; +}; +static struct replacement replacements[150]; +void move_replacements (rtx *x, rtx *y, int n_replacements) +{ + int i; + for (i = 0; i < n_replacements; i++) + if (replacements[i].subreg_loc == x) + replacements[i].subreg_loc = y; + else if (replacements[i].where == x) + { + replacements[i].where = y; + replacements[i].subreg_loc = 0; + } +} + +/* { dg-final { scan-assembler {e64,m2} } } */ +/* { dg-final { scan-assembler-not {e64,m4} } } */ +/* { dg-final { scan-assembler-not {jr} } } */ +/* { dg-final { scan-assembler {ret} } } */ +/* { dg-final { scan-assembler-not {sp} } } */