diff mbox series

[Committed] RISC-V: Add one more ASM check in PR113112-1.c

Message ID 20231225061952.897770-1-juzhe.zhong@rivai.ai
State Unresolved
Headers
Series [Committed] RISC-V: Add one more ASM check in PR113112-1.c |

Checks

Context Check Description
snail/gcc-patch-check warning Git am fail log

Commit Message

juzhe.zhong@rivai.ai Dec. 25, 2023, 6:19 a.m. UTC 
  gcc/testsuite/ChangeLog:

	* gcc.dg/vect/costmodel/riscv/rvv/pr113112-1.c: Add one more ASM check.

---
 gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/pr113112-1.c | 1 +
 1 file changed, 1 insertion(+)
diff mbox series

Patch

diff --git a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/pr113112-1.c b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/pr113112-1.c
index a44a1c041af..31b41ba707e 100644
--- a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/pr113112-1.c
+++ b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/pr113112-1.c
@@ -20,6 +20,7 @@  foo (int n){
   return 0;
 }
 
+/* { dg-final { scan-assembler {e32,m4} } } */
 /* { dg-final { scan-assembler-not {jr} } } */
 /* { dg-final { scan-assembler-times {ret} 1 } } */
 /* { dg-final { scan-tree-dump "Maximum lmul = 8" "vect" } } */