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(unknown [113.200.174.11]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (P-384) server-digest SHA384) (Client did not present a certificate) (Authenticated sender: xry111@xry111.site) by xry111.site (Postfix) with ESMTPSA id 9E87C6711B; Sun, 24 Dec 2023 07:36:20 -0500 (EST) From: Xi Ruoyao To: gcc-patches@gcc.gnu.org Cc: chenglulu , i@xen0n.name, xuchenghua@loongson.cn, c@jia.je, Xi Ruoyao Subject: [PATCH v2] LoongArch: Expand left rotate to right rotate with negated amount Date: Sun, 24 Dec 2023 20:33:14 +0800 Message-ID: <20231224123608.6650-1-xry111@xry111.site> X-Mailer: git-send-email 2.43.0 MIME-Version: 1.0 X-Spam-Status: No, score=-8.5 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, KAM_SHORT, LIKELY_SPAM_FROM, SPF_HELO_PASS, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1786166832169197733 X-GMAIL-MSGID: 1786166832169197733 gcc/ChangeLog: * config/loongarch/loongarch.md (rotl3): New define_expand. * config/loongarch/simd.md (vrotl3): Likewise. (rotl3): Likewise. gcc/testsuite/ChangeLog: * gcc.target/loongarch/rotl-with-rotr.c: New test. * gcc.target/loongarch/rotl-with-vrotr-b.c: New test. * gcc.target/loongarch/rotl-with-vrotr-h.c: New test. * gcc.target/loongarch/rotl-with-vrotr-w.c: New test. * gcc.target/loongarch/rotl-with-vrotr-d.c: New test. * gcc.target/loongarch/rotl-with-xvrotr-b.c: New test. * gcc.target/loongarch/rotl-with-xvrotr-h.c: New test. * gcc.target/loongarch/rotl-with-xvrotr-w.c: New test. * gcc.target/loongarch/rotl-with-xvrotr-d.c: New test. --- Change from [v1]: - Wrap the negated wrapping amount with subreg: for rotl, to avoid an ICE left rotating QI and HI vectors. - Add tests for QI, HI, and DI vectors. [v1]:https://gcc.gnu.org/pipermail/gcc-patches/2023-December/640872.html Bootstrapped and regtested on loongarch64-linux-gnu. Ok for trunk? gcc/config/loongarch/loongarch.md | 12 ++++++++ gcc/config/loongarch/simd.md | 29 +++++++++++++++++++ .../gcc.target/loongarch/rotl-with-rotr.c | 9 ++++++ .../gcc.target/loongarch/rotl-with-vrotr-b.c | 7 +++++ .../gcc.target/loongarch/rotl-with-vrotr-d.c | 7 +++++ .../gcc.target/loongarch/rotl-with-vrotr-h.c | 7 +++++ .../gcc.target/loongarch/rotl-with-vrotr-w.c | 28 ++++++++++++++++++ .../gcc.target/loongarch/rotl-with-xvrotr-b.c | 7 +++++ .../gcc.target/loongarch/rotl-with-xvrotr-d.c | 7 +++++ .../gcc.target/loongarch/rotl-with-xvrotr-h.c | 7 +++++ .../gcc.target/loongarch/rotl-with-xvrotr-w.c | 7 +++++ 11 files changed, 127 insertions(+) create mode 100644 gcc/testsuite/gcc.target/loongarch/rotl-with-rotr.c create mode 100644 gcc/testsuite/gcc.target/loongarch/rotl-with-vrotr-b.c create mode 100644 gcc/testsuite/gcc.target/loongarch/rotl-with-vrotr-d.c create mode 100644 gcc/testsuite/gcc.target/loongarch/rotl-with-vrotr-h.c create mode 100644 gcc/testsuite/gcc.target/loongarch/rotl-with-vrotr-w.c create mode 100644 gcc/testsuite/gcc.target/loongarch/rotl-with-xvrotr-b.c create mode 100644 gcc/testsuite/gcc.target/loongarch/rotl-with-xvrotr-d.c create mode 100644 gcc/testsuite/gcc.target/loongarch/rotl-with-xvrotr-h.c create mode 100644 gcc/testsuite/gcc.target/loongarch/rotl-with-xvrotr-w.c diff --git a/gcc/config/loongarch/loongarch.md b/gcc/config/loongarch/loongarch.md index 30025bf1908..939432b83e0 100644 --- a/gcc/config/loongarch/loongarch.md +++ b/gcc/config/loongarch/loongarch.md @@ -2903,6 +2903,18 @@ (define_insn "rotrsi3_extend" [(set_attr "type" "shift,shift") (set_attr "mode" "SI")]) +;; Expand left rotate to right rotate. +(define_expand "rotl3" + [(set (match_dup 3) + (neg:SI (match_operand:SI 2 "register_operand"))) + (set (match_operand:GPR 0 "register_operand") + (rotatert:GPR (match_operand:GPR 1 "register_operand") + (match_dup 3)))] + "" + { + operands[3] = gen_reg_rtx (SImode); + }); + ;; The following templates were added to generate "bstrpick.d + alsl.d" ;; instruction pairs. ;; It is required that the values of const_immalsl_operand and diff --git a/gcc/config/loongarch/simd.md b/gcc/config/loongarch/simd.md index 13202f79bee..93fb39abcf5 100644 --- a/gcc/config/loongarch/simd.md +++ b/gcc/config/loongarch/simd.md @@ -268,6 +268,35 @@ (define_insn "vrotr3" [(set_attr "type" "simd_int_arith") (set_attr "mode" "")]) +;; Expand left rotate to right rotate. +(define_expand "vrotl3" + [(set (match_dup 3) + (neg:IVEC (match_operand:IVEC 2 "register_operand"))) + (set (match_operand:IVEC 0 "register_operand") + (rotatert:IVEC (match_operand:IVEC 1 "register_operand") + (match_dup 3)))] + "" + { + operands[3] = gen_reg_rtx (mode); + }); + +;; Expand left rotate with a scalar amount to right rotate: negate the +;; scalar before broadcasting it because scalar negation is cheaper than +;; vector negation. +(define_expand "rotl3" + [(set (match_dup 3) + (neg:SI (match_operand:SI 2 "register_operand"))) + (set (match_dup 4) + (vec_duplicate:IVEC (subreg: (match_dup 3) 0))) + (set (match_operand:IVEC 0 "register_operand") + (rotatert:IVEC (match_operand:IVEC 1 "register_operand") + (match_dup 4)))] + "" + { + operands[3] = gen_reg_rtx (SImode); + operands[4] = gen_reg_rtx (mode); + }); + ;; vrotri.{b/h/w/d} (define_insn "rotr3" diff --git a/gcc/testsuite/gcc.target/loongarch/rotl-with-rotr.c b/gcc/testsuite/gcc.target/loongarch/rotl-with-rotr.c new file mode 100644 index 00000000000..84cc53cecaf --- /dev/null +++ b/gcc/testsuite/gcc.target/loongarch/rotl-with-rotr.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ +/* { dg-final { scan-assembler "rotr\\.w" } } */ + +unsigned +t (unsigned a, unsigned b) +{ + return a << b | a >> (32 - b); +} diff --git a/gcc/testsuite/gcc.target/loongarch/rotl-with-vrotr-b.c b/gcc/testsuite/gcc.target/loongarch/rotl-with-vrotr-b.c new file mode 100644 index 00000000000..14298bf9ee4 --- /dev/null +++ b/gcc/testsuite/gcc.target/loongarch/rotl-with-vrotr-b.c @@ -0,0 +1,7 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -mlsx -fno-vect-cost-model" } */ +/* { dg-final { scan-assembler-times "vrotr\\.b" 2 } } */ +/* { dg-final { scan-assembler-times "vneg\\.b" 1 } } */ + +#define TYPE char +#include "rotl-with-vrotr-w.c" diff --git a/gcc/testsuite/gcc.target/loongarch/rotl-with-vrotr-d.c b/gcc/testsuite/gcc.target/loongarch/rotl-with-vrotr-d.c new file mode 100644 index 00000000000..0e971b3235c --- /dev/null +++ b/gcc/testsuite/gcc.target/loongarch/rotl-with-vrotr-d.c @@ -0,0 +1,7 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -mlsx -fno-vect-cost-model" } */ +/* { dg-final { scan-assembler-times "vrotr\\.d" 2 } } */ +/* { dg-final { scan-assembler-times "vneg\\.d" 1 } } */ + +#define TYPE long long +#include "rotl-with-vrotr-w.c" diff --git a/gcc/testsuite/gcc.target/loongarch/rotl-with-vrotr-h.c b/gcc/testsuite/gcc.target/loongarch/rotl-with-vrotr-h.c new file mode 100644 index 00000000000..93216ebc245 --- /dev/null +++ b/gcc/testsuite/gcc.target/loongarch/rotl-with-vrotr-h.c @@ -0,0 +1,7 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -mlsx -fno-vect-cost-model" } */ +/* { dg-final { scan-assembler-times "vrotr\\.h" 2 } } */ +/* { dg-final { scan-assembler-times "vneg\\.h" 1 } } */ + +#define TYPE short +#include "rotl-with-vrotr-w.c" diff --git a/gcc/testsuite/gcc.target/loongarch/rotl-with-vrotr-w.c b/gcc/testsuite/gcc.target/loongarch/rotl-with-vrotr-w.c new file mode 100644 index 00000000000..d05b86f4716 --- /dev/null +++ b/gcc/testsuite/gcc.target/loongarch/rotl-with-vrotr-w.c @@ -0,0 +1,28 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -mlsx -fno-vect-cost-model" } */ +/* { dg-final { scan-assembler-times "vrotr\\.w" 2 } } */ +/* { dg-final { scan-assembler-times "vneg\\.w" 1 } } */ + +#ifndef VLEN +#define VLEN 16 +#endif + +#ifndef TYPE +#define TYPE int +#endif + +typedef unsigned TYPE V __attribute__ ((vector_size (VLEN))); +V a, b, c; + +void +test (int x) +{ + b = a << x | a >> ((int)sizeof (TYPE) * __CHAR_BIT__ - x); +} + +void +test2 (void) +{ + for (int i = 0; i < VLEN / sizeof (TYPE); i++) + c[i] = a[i] << b[i] | a[i] >> ((int)sizeof (TYPE) * __CHAR_BIT__ - b[i]); +} diff --git a/gcc/testsuite/gcc.target/loongarch/rotl-with-xvrotr-b.c b/gcc/testsuite/gcc.target/loongarch/rotl-with-xvrotr-b.c new file mode 100644 index 00000000000..2674b1b618c --- /dev/null +++ b/gcc/testsuite/gcc.target/loongarch/rotl-with-xvrotr-b.c @@ -0,0 +1,7 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -mlasx -fno-vect-cost-model" } */ +/* { dg-final { scan-assembler-times "xvrotr\\.b" 2 } } */ +/* { dg-final { scan-assembler-times "xvneg\\.b" 1 } } */ + +#define VLEN 32 +#include "rotl-with-vrotr-b.c" diff --git a/gcc/testsuite/gcc.target/loongarch/rotl-with-xvrotr-d.c b/gcc/testsuite/gcc.target/loongarch/rotl-with-xvrotr-d.c new file mode 100644 index 00000000000..e9440331594 --- /dev/null +++ b/gcc/testsuite/gcc.target/loongarch/rotl-with-xvrotr-d.c @@ -0,0 +1,7 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -mlasx -fno-vect-cost-model" } */ +/* { dg-final { scan-assembler-times "xvrotr\\.d" 2 } } */ +/* { dg-final { scan-assembler-times "xvneg\\.d" 1 } } */ + +#define VLEN 32 +#include "rotl-with-vrotr-d.c" diff --git a/gcc/testsuite/gcc.target/loongarch/rotl-with-xvrotr-h.c b/gcc/testsuite/gcc.target/loongarch/rotl-with-xvrotr-h.c new file mode 100644 index 00000000000..3d998941f92 --- /dev/null +++ b/gcc/testsuite/gcc.target/loongarch/rotl-with-xvrotr-h.c @@ -0,0 +1,7 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -mlasx -fno-vect-cost-model" } */ +/* { dg-final { scan-assembler-times "xvrotr\\.h" 2 } } */ +/* { dg-final { scan-assembler-times "xvneg\\.h" 1 } } */ + +#define VLEN 32 +#include "rotl-with-vrotr-h.c" diff --git a/gcc/testsuite/gcc.target/loongarch/rotl-with-xvrotr-w.c b/gcc/testsuite/gcc.target/loongarch/rotl-with-xvrotr-w.c new file mode 100644 index 00000000000..ca6aa7bae6c --- /dev/null +++ b/gcc/testsuite/gcc.target/loongarch/rotl-with-xvrotr-w.c @@ -0,0 +1,7 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -mlasx -fno-vect-cost-model" } */ +/* { dg-final { scan-assembler-times "xvrotr\\.w" 2 } } */ +/* { dg-final { scan-assembler-times "xvneg\\.w" 1 } } */ + +#define VLEN 32 +#include "rotl-with-vrotr-w.c"