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[2620:52:3:1:0:246e:9693:128c]) by mx.google.com with ESMTPS id qf8-20020a05620a660800b0077d85c98bb3si26748699qkn.194.2023.12.19.03.06.01 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 19 Dec 2023 03:06:02 -0800 (PST) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) client-ip=2620:52:3:1:0:246e:9693:128c; Authentication-Results: mx.google.com; arc=pass (i=1); spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org" Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id B9AE83860753 for ; Tue, 19 Dec 2023 11:06:01 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from eggs.gnu.org (eggs.gnu.org [IPv6:2001:470:142:3::10]) by sourceware.org (Postfix) with ESMTPS id 249833858C42 for ; Tue, 19 Dec 2023 11:05:34 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 249833858C42 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=loongson.cn Authentication-Results: sourceware.org; spf=fail smtp.mailfrom=loongson.cn ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 249833858C42 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=2001:470:142:3::10 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1702983937; cv=none; b=YQpoo71oIoaxtt2d2ER+4d48VkK/CMFUFSRxoSkqRHehQhVARfJ4sXvonKBpa9qG5tdPK1Pg2xzh0s9e9PMlT89ixowRmwBh/y10wtchbZsxQpdmFHcdWa3jLqhTlqMQw4XsbFu+tjVWs6a29Gb7NBBxeAYcLpsrRhdD4DOhkr8= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1702983937; c=relaxed/simple; bh=tLHZ9PVFGomiAAoXR6wWqWHDwV7vXh8Y9x4/3u1SM00=; h=From:To:Subject:Date:Message-Id:MIME-Version; b=QjqP+vO6OZQaPFFrBI0bcQTqbv1IHEwkUmkc75d55k2N7LEOGfL9Y5Q/Rr6KBVqcSr6ChXbwjG8VflncukUhZMpht+C58QvyMjcVdq8JGF05hplU0hXAZorNAAYji+/hH2QKNpLS5Ni8FYYLky6SFEur+iTkZwX2hqiHl68FGv0= ARC-Authentication-Results: i=1; server2.sourceware.org Received: from mail.loongson.cn ([114.242.206.163]) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rFXuj-0001ee-SZ for gcc-patches@gcc.gnu.org; Tue, 19 Dec 2023 06:05:32 -0500 Received: from loongson.cn (unknown [10.20.4.107]) by gateway (Coremail) with SMTP id _____8Cx9OrueIFlypUCAA--.8765S3; Tue, 19 Dec 2023 19:05:19 +0800 (CST) Received: from loongson-pc.loongson.cn (unknown [10.20.4.107]) by localhost.localdomain (Coremail) with SMTP id AQAAf8CxbOToeIFlqzIAAA--.1396S2; Tue, 19 Dec 2023 19:05:13 +0800 (CST) From: Lulu Cheng To: gcc-patches@gcc.gnu.org Cc: xry111@xry111.site, i@xen0n.name, xuchenghua@loongson.cn, chenglulu@loongson.cn Subject: [PATCH] LoongArch: Added TLS Le Relax support. Date: Tue, 19 Dec 2023 19:04:50 +0800 Message-Id: <20231219110449.30805-1-chenglulu@loongson.cn> X-Mailer: git-send-email 2.20.1 MIME-Version: 1.0 X-CM-TRANSID: AQAAf8CxbOToeIFlqzIAAA--.1396S2 X-CM-SenderInfo: xfkh0wpoxo3qxorr0wxvrqhubq/ X-Coremail-Antispam: 1Uk129KBj93XoWxtw15JFWkKw1kWr15WF47KFX_yoWfuFy8pr W7Zw1Yya18Grs3G397ta45Wr45ArsrGry2va9xJFWxCanrXr10vF4vyF9xX3WUXw4rWrya va4rK3Wa9a1DA3XCm3ZEXasCq-sJn29KB7ZKAUJUUUU8529EdanIXcx71UUUUU7KY7ZEXa sCq-sGcSsGvfJ3Ic02F40EFcxC0VAKzVAqx4xG6I80ebIjqfuFe4nvWSU5nxnvy29KBjDU 0xBIdaVrnRJUUUkFb4IE77IF4wAFF20E14v26r1j6r4UM7CY07I20VC2zVCF04k26cxKx2 IYs7xG6rWj6s0DM7CIcVAFz4kK6r1j6r18M28lY4IEw2IIxxk0rwA2F7IY1VAKz4vEj48v e4kI8wA2z4x0Y4vE2Ix0cI8IcVAFwI0_JFI_Gr1l84ACjcxK6xIIjxv20xvEc7CjxVAFwI 0_Gr0_Cr1l84ACjcxK6I8E87Iv67AKxVW8Jr0_Cr1UM28EF7xvwVC2z280aVCY1x0267AK xVW8Jr0_Cr1UM2AIxVAIcxkEcVAq07x20xvEncxIr21l57IF6xkI12xvs2x26I8E6xACxx 1l5I8CrVACY4xI64kE6c02F40Ex7xfMcIj6xIIjxv20xvE14v26r106r15McIj6I8E87Iv 67AKxVWUJVW8JwAm72CE4IkC6x0Yz7v_Jr0_Gr1lF7xvr2IYc2Ij64vIr41l42xK82IYc2 Ij64vIr41l4I8I3I0E4IkC6x0Yz7v_Jr0_Gr1lx2IqxVAqx4xG67AKxVWUJVWUGwC20s02 6x8GjcxK67AKxVWUGVWUWwC2zVAF1VAY17CE14v26r126r1DMIIYrxkI7VAKI48JMIIF0x vE2Ix0cI8IcVAFwI0_Jr0_JF4lIxAIcVC0I7IYx2IY6xkF7I0E14v26r1j6r4UMIIF0xvE 42xK8VAvwI8IcIk0rVWUJVWUCwCI42IY6I8E87Iv67AKxVWUJVW8JwCI42IY6I8E87Iv6x kF7I0E14v26r1j6r4UYxBIdaVFxhVjvjDU0xZFpf9x07UWHqcUUUUU= Received-SPF: pass client-ip=114.242.206.163; envelope-from=chenglulu@loongson.cn; helo=mail.loongson.cn X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-Spam-Status: No, score=-12.4 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, KAM_SHORT, KAM_STOCKGEN, SPF_FAIL, SPF_HELO_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1785708110668719911 X-GMAIL-MSGID: 1785708110668719911 Check whether the assembler supports tls le relax. If it supports it, the assembly instruction sequence of tls le relax will be generated by default. The original way to obtain the tls le symbol address: lu12i.w $rd, %le_hi20(sym) ori $rd, $rd, %le_lo12(sym) add.{w/d} $rd, $rd, $tp If the assembler supports tls le relax, the following sequence is generated: lu12i.w $rd, %le_hi20_r(sym) add.{w/d} $rd,$rd,$tp,%le_add_r(sym) addi.{w/d} $rd,$rd,%le_lo12_r(sym) gcc/ChangeLog: * config.in: Regenerate. * config/loongarch/loongarch-opts.h (HAVE_AS_TLS_LE_RELAXATION): Define. * config/loongarch/loongarch.cc (loongarch_legitimize_tls_address): Added TLS Le Relax support. (loongarch_print_operand_reloc): Add the output string of TLS Le Relax. * config/loongarch/loongarch.md (@add_tls_le_relax): New template. * configure: Regenerate. * configure.ac: Check if binutils supports TLS le relax. gcc/testsuite/ChangeLog: * lib/target-supports.exp: Add a function to check whether binutil supports TLS Le Relax. * gcc.target/loongarch/tls-le-relax.c: New test. --- gcc/config.in | 6 +++ gcc/config/loongarch/loongarch-opts.h | 4 ++ gcc/config/loongarch/loongarch.cc | 44 +++++++++++++++++-- gcc/config/loongarch/loongarch.md | 12 +++++ gcc/configure | 31 +++++++++++++ gcc/configure.ac | 5 +++ .../gcc.target/loongarch/tls-le-relax.c | 12 +++++ gcc/testsuite/lib/target-supports.exp | 12 +++++ 8 files changed, 123 insertions(+), 3 deletions(-) create mode 100644 gcc/testsuite/gcc.target/loongarch/tls-le-relax.c diff --git a/gcc/config.in b/gcc/config.in index fa40825d6d0..b499bbfdda7 100644 --- a/gcc/config.in +++ b/gcc/config.in @@ -793,6 +793,12 @@ #endif +/* Define if your assembler supports tls le relocation. */ +#ifndef USED_FOR_TARGET +#undef HAVE_AS_TLS_LE_RELAXATION +#endif + + /* Define if your assembler supports vl/vst/vlm/vstm with an optional alignment hint argument. */ #ifndef USED_FOR_TARGET diff --git a/gcc/config/loongarch/loongarch-opts.h b/gcc/config/loongarch/loongarch-opts.h index d091359300a..e46f79af390 100644 --- a/gcc/config/loongarch/loongarch-opts.h +++ b/gcc/config/loongarch/loongarch-opts.h @@ -114,4 +114,8 @@ struct loongarch_flags { #define HAVE_AS_TLS 0 #endif +#ifndef HAVE_AS_TLS_LE_RELAXATION +#define HAVE_AS_TLS_LE_RELAXATION 0 +#endif + #endif /* LOONGARCH_OPTS_H */ diff --git a/gcc/config/loongarch/loongarch.cc b/gcc/config/loongarch/loongarch.cc index 390e3206a17..22e41014f2c 100644 --- a/gcc/config/loongarch/loongarch.cc +++ b/gcc/config/loongarch/loongarch.cc @@ -2998,7 +2998,29 @@ loongarch_legitimize_tls_address (rtx loc) case TLS_MODEL_LOCAL_EXEC: { - /* la.tls.le; tp-relative add. */ + /* la.tls.le; tp-relative add. + + normal: + lu12i.w $rd, %le_hi20(sym) + ori $rd, $rd, %le_lo12(sym) + add.{w/d} $rd, $rd, $tp + (st.{w/d}/ld.{w/d} $rs, $rd, 0) + + tls le relax: + lu12i.w $rd, %le_hi20_r(sym) + add.{w/d} $rd,$rd,$tp + addi.{w/d} $rd,$rd,%le_lo12_r(sym) + (st.{w/d}/ld.{w/d} $rs, $rd, 0) + + extreme (When the code model is set to extreme, the TLS le Relax + instruction sequence is not generated): + lu12i.w $rd, %le_hi20(sym) + ori $rd, $rd, %le_lo12(sym) + lu32i.d $rd, %le64_lo20(sym) + lu52i.d $rd, $rd, %le64_hi12(sym) + add.d $rd, $rd, $tp + (st.{w/d}/ld.{w/d} $rs, $rd, 0) */ + tp = gen_rtx_REG (Pmode, THREAD_POINTER_REGNUM); tmp1 = gen_reg_rtx (Pmode); dest = gen_reg_rtx (Pmode); @@ -3009,7 +3031,18 @@ loongarch_legitimize_tls_address (rtx loc) tmp3 = gen_reg_rtx (Pmode); rtx high = gen_rtx_HIGH (Pmode, copy_rtx (tmp2)); high = loongarch_force_temporary (tmp3, high); - emit_insn (gen_ori_l_lo12 (Pmode, tmp1, high, tmp2)); + + /* The assembler does not implement tls le relax support when the + code model is extreme, so when the code model is extreme, the + old symbol address acquisition method is still used. */ + if (HAVE_AS_TLS_LE_RELAXATION && !TARGET_CMODEL_EXTREME) + { + emit_insn (gen_add_tls_le_relax (Pmode, dest, high, tp, loc)); + loongarch_emit_move (dest, gen_rtx_LO_SUM (Pmode, dest, tmp2)); + return dest; + } + else + emit_insn (gen_ori_l_lo12 (Pmode, tmp1, high, tmp2)); if (TARGET_CMODEL_EXTREME) { @@ -5992,7 +6025,12 @@ loongarch_print_operand_reloc (FILE *file, rtx op, bool hi64_part, gcc_unreachable (); } else - reloc = hi_reloc ? "%le_hi20" : "%le_lo12"; + { + if (HAVE_AS_TLS_LE_RELAXATION && !TARGET_CMODEL_EXTREME) + reloc = hi_reloc ? "%le_hi20_r" : "%le_lo12_r"; + else + reloc = hi_reloc ? "%le_hi20" : "%le_lo12"; + } break; case SYMBOL_TLSGD: diff --git a/gcc/config/loongarch/loongarch.md b/gcc/config/loongarch/loongarch.md index cb5b67aa5d9..1156d41d494 100644 --- a/gcc/config/loongarch/loongarch.md +++ b/gcc/config/loongarch/loongarch.md @@ -73,6 +73,7 @@ (define_c_enum "unspec" [ UNSPEC_LOAD_FROM_GOT UNSPEC_PCALAU12I UNSPEC_PCALAU12I_GR + UNSPEC_ADD_TLS_LE_RELAX UNSPEC_ORI_L_LO12 UNSPEC_LUI_L_HI20 UNSPEC_LUI_H_LO20 @@ -2442,6 +2443,17 @@ (define_insn "@pcalau12i_gr" "pcalau12i\t%0,%%pc_hi20(%1)" [(set_attr "type" "move")]) +(define_insn "@add_tls_le_relax" + [(set (match_operand:P 0 "register_operand" "=r") + (unspec:P [(match_operand:P 1 "register_operand" "r") + (match_operand:P 2 "register_operand" "r") + (match_operand:P 3 "symbolic_operand")] + UNSPEC_ADD_TLS_LE_RELAX))] + "" + "add.\t%0,%1,%2,%le_add_r(%3)" + [(set_attr "type" "move")] +) + (define_insn "@ori_l_lo12" [(set (match_operand:P 0 "register_operand" "=r") (unspec:P [(match_operand:P 1 "register_operand" "r") diff --git a/gcc/configure b/gcc/configure index de72cb1e1fe..996046f5198 100755 --- a/gcc/configure +++ b/gcc/configure @@ -31050,6 +31050,37 @@ if test $gcc_cv_as_loongarch_cond_branch_relax = yes; then $as_echo "#define HAVE_AS_COND_BRANCH_RELAXATION 1" >>confdefs.h +fi + + { $as_echo "$as_me:${as_lineno-$LINENO}: checking assembler for tls le relaxation support" >&5 +$as_echo_n "checking assembler for tls le relaxation support... " >&6; } +if ${gcc_cv_as_loongarch_tls_le_relaxation_support+:} false; then : + $as_echo_n "(cached) " >&6 +else + gcc_cv_as_loongarch_tls_le_relaxation_support=no + if test x$gcc_cv_as != x; then + $as_echo 'lu12i.w $t0,%le_hi20_r(a)' > conftest.s + if { ac_try='$gcc_cv_as $gcc_cv_as_flags -o conftest.o conftest.s >&5' + { { eval echo "\"\$as_me\":${as_lineno-$LINENO}: \"$ac_try\""; } >&5 + (eval $ac_try) 2>&5 + ac_status=$? + $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5 + test $ac_status = 0; }; } + then + gcc_cv_as_loongarch_tls_le_relaxation_support=yes + else + echo "configure: failed program was" >&5 + cat conftest.s >&5 + fi + rm -f conftest.o conftest.s + fi +fi +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $gcc_cv_as_loongarch_tls_le_relaxation_support" >&5 +$as_echo "$gcc_cv_as_loongarch_tls_le_relaxation_support" >&6; } +if test $gcc_cv_as_loongarch_tls_le_relaxation_support = yes; then + +$as_echo "#define HAVE_AS_TLS_LE_RELAXATION 1" >>confdefs.h + fi ;; diff --git a/gcc/configure.ac b/gcc/configure.ac index 21ba631482f..784be5bed59 100644 --- a/gcc/configure.ac +++ b/gcc/configure.ac @@ -5447,6 +5447,11 @@ x: beq $a0,$a1,a],, [AC_DEFINE(HAVE_AS_COND_BRANCH_RELAXATION, 1, [Define if your assembler supports conditional branch relaxation.])]) + gcc_GAS_CHECK_FEATURE([tls le relaxation support], + gcc_cv_as_loongarch_tls_le_relaxation_support,, + [lu12i.w $t0,%le_hi20_r(a)],, + [AC_DEFINE(HAVE_AS_TLS_LE_RELAXATION, 1, + [Define if your assembler supports tls le relocation.])]) ;; s390*-*-*) gcc_GAS_CHECK_FEATURE([.gnu_attribute support], diff --git a/gcc/testsuite/gcc.target/loongarch/tls-le-relax.c b/gcc/testsuite/gcc.target/loongarch/tls-le-relax.c new file mode 100644 index 00000000000..a9a404fc70a --- /dev/null +++ b/gcc/testsuite/gcc.target/loongarch/tls-le-relax.c @@ -0,0 +1,12 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -mcmodel=normal -mexplicit-relocs" } */ +/* { dg-final { scan-assembler "%le_add_r" { target tls_le_relax } } } */ + +__attribute__ ((tls_model ("local-exec"))) __thread int a; + +void +test (void) +{ + a = 10; +} + diff --git a/gcc/testsuite/lib/target-supports.exp b/gcc/testsuite/lib/target-supports.exp index 7f13ff0ca56..e5ebcd8fe05 100644 --- a/gcc/testsuite/lib/target-supports.exp +++ b/gcc/testsuite/lib/target-supports.exp @@ -13207,6 +13207,18 @@ proc check_effective_target_loongarch_call36_support { } { } ""] } +# Returns 1 if binutils supports TLS le Relax, 0 otherwise. +proc check_effective_target_tls_le_relax { } { + if [check_effective_target_tls_native] { + return [check_no_compiler_messages loongarch_tls_le_relax object { + /* Assembly code */ + lu12i.w $r12, %le_hi20_r(a) + }] + } + + return 0; +} + # Appends necessary Python flags to extra-tool-flags if Python.h is supported. # Otherwise, modifies dg-do-what. proc dg-require-python-h { args } {